From nobody Sat Sep 28 22:09:22 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1550847191300924.5542814838163; Fri, 22 Feb 2019 06:53:11 -0800 (PST) Received: from localhost ([127.0.0.1]:52049 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gxCCI-0003UM-UY for importer@patchew.org; Fri, 22 Feb 2019 09:53:06 -0500 Received: from eggs.gnu.org ([209.51.188.92]:40603) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gxBYb-0005K7-IT for qemu-devel@nongnu.org; Fri, 22 Feb 2019 09:12:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gxBYU-0007E1-5C for qemu-devel@nongnu.org; Fri, 22 Feb 2019 09:12:01 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:56022) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gxBY9-0006Qe-QT; Fri, 22 Feb 2019 09:11:38 -0500 Received: from tweenies.uni-paderborn.de ([131.234.189.21] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 spheron) id 1gxBY6-0001k2-Is; Fri, 22 Feb 2019 15:11:35 +0100 Received: from mail.uni-paderborn.de by tweenies with queue id 3137448-4; Fri, 22 Feb 2019 14:11:33 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Fri, 22 Feb 2019 15:10:06 +0100 Message-Id: <20190222141024.22217-17-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190222141024.22217-1-kbastian@mail.uni-paderborn.de> References: <20190222141024.22217-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.2.22.135717, AntiVirus-Engine: 5.58.0, AntiVirus-Data: 2019.2.22.5580002 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v8 16/34] target/riscv: Convert quadrant 0 of RVXC insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/Makefile.objs | 9 ++- target/riscv/insn16.decode | 55 ++++++++++++++++++ target/riscv/insn_trans/trans_rvc.inc.c | 75 +++++++++++++++++++++++++ target/riscv/translate.c | 53 ++++++----------- 4 files changed, 154 insertions(+), 38 deletions(-) create mode 100644 target/riscv/insn16.decode create mode 100644 target/riscv/insn_trans/trans_rvc.inc.c diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs index 05087a91bb..9c6c109327 100644 --- a/target/riscv/Makefile.objs +++ b/target/riscv/Makefile.objs @@ -10,4 +10,11 @@ target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODE= TREE) $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $(decode32-y), \ "GEN", $(TARGET_DIR)$@) =20 -target/riscv/translate.o: target/riscv/decode_insn32.inc.c +target/riscv/decode_insn16.inc.c: \ + $(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE) + $(call quiet-command, \ + $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn16 --insnwidth 16 $<,= \ + "GEN", $(TARGET_DIR)$@) + +target/riscv/translate.o: target/riscv/decode_insn32.inc.c \ + target/riscv/decode_insn16.inc.c diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode new file mode 100644 index 0000000000..558c0c41f0 --- /dev/null +++ b/target/riscv/insn16.decode @@ -0,0 +1,55 @@ +# +# RISC-V translation routines for the RVXI Base Integer Instruction Set. +# +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de +# Bastian Koppelmann, kbastian@mail.uni-paderborn.de +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2 or later, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along = with +# this program. If not, see . + +# Fields: +%rd 7:5 +%rs1_3 7:3 !function=3Dex_rvc_register +%rs2_3 2:3 !function=3Dex_rvc_register + +# Immediates: +%nzuimm_ciw 7:4 11:2 5:1 6:1 !function=3Dex_shift_2 +%uimm_cl_d 5:2 10:3 !function=3Dex_shift_3 +%uimm_cl_w 5:1 10:3 6:1 !function=3Dex_shift_2 + + +# Argument sets: +&cl rs1 rd +&cl_dw uimm rs1 rd +&ciw nzuimm rd +&cs rs1 rs2 +&cs_dw uimm rs1 rs2 + + +# Formats 16: +@ciw ... ........ ... .. &ciw nzuimm=3D%nzuimm_ciw rd= =3D%rs2_3 +@cl_d ... ... ... .. ... .. &cl_dw uimm=3D%uimm_cl_d rs1=3D%rs1_3 = rd=3D%rs2_3 +@cl_w ... ... ... .. ... .. &cl_dw uimm=3D%uimm_cl_w rs1=3D%rs1_3 = rd=3D%rs2_3 +@cl ... ... ... .. ... .. &cl rs1=3D%rs1_3 rd= =3D%rs2_3 +@cs ... ... ... .. ... .. &cs rs1=3D%rs1_3 rs= 2=3D%rs2_3 +@cs_d ... ... ... .. ... .. &cs_dw uimm=3D%uimm_cl_d rs1=3D%rs1_3 = rs2=3D%rs2_3 +@cs_w ... ... ... .. ... .. &cs_dw uimm=3D%uimm_cl_w rs1=3D%rs1_3 = rs2=3D%rs2_3 + + +# *** RV64C Standard Extension (Quadrant 0) *** +c_addi4spn 000 ........ ... 00 @ciw +c_fld 001 ... ... .. ... 00 @cl_d +c_lw 010 ... ... .. ... 00 @cl_w +c_flw_ld 011 --- ... -- ... 00 @cl #Note: Must parse uimm man= ually +c_fsd 101 ... ... .. ... 00 @cs_d +c_sw 110 ... ... .. ... 00 @cs_w +c_fsw_sd 111 --- ... -- ... 00 @cs #Note: Must parse uimm man= ually diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_tr= ans/trans_rvc.inc.c new file mode 100644 index 0000000000..93ec8aa30b --- /dev/null +++ b/target/riscv/insn_trans/trans_rvc.inc.c @@ -0,0 +1,75 @@ +/* + * RISC-V translation routines for the RVC Compressed Instruction Set. + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de + * Bastian Koppelmann, kbastian@mail.uni-paderborn.de + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a) +{ + if (a->nzuimm =3D=3D 0) { + /* Reserved in ISA */ + return false; + } + arg_addi arg =3D { .rd =3D a->rd, .rs1 =3D 2, .imm =3D a->nzuimm }; + return trans_addi(ctx, &arg); +} + +static bool trans_c_fld(DisasContext *ctx, arg_c_fld *a) +{ + arg_fld arg =3D { .rd =3D a->rd, .rs1 =3D a->rs1, .imm =3D a->uimm }; + return trans_fld(ctx, &arg); +} + +static bool trans_c_lw(DisasContext *ctx, arg_c_lw *a) +{ + arg_lw arg =3D { .rd =3D a->rd, .rs1 =3D a->rs1, .imm =3D a->uimm }; + return trans_lw(ctx, &arg); +} + +static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a) +{ +#ifdef TARGET_RISCV32 + /* C.FLW ( RV32FC-only ) */ + return false; +#else + /* C.LD ( RV64C/RV128C-only ) */ + return false; +#endif +} + +static bool trans_c_fsd(DisasContext *ctx, arg_c_fsd *a) +{ + arg_fsd arg =3D { .rs1 =3D a->rs1, .rs2 =3D a->rs2, .imm =3D a->uimm }; + return trans_fsd(ctx, &arg); +} + +static bool trans_c_sw(DisasContext *ctx, arg_c_sw *a) +{ + arg_sw arg =3D { .rs1 =3D a->rs1, .rs2 =3D a->rs2, .imm =3D a->uimm }; + return trans_sw(ctx, &arg); +} + +static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a) +{ +#ifdef TARGET_RISCV32 + /* C.FSW ( RV32FC-only ) */ + return false; +#else + /* C.SD ( RV64C/RV128C-only ) */ + return false; +#endif +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 02f64ed8a7..0106fa8d51 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -803,27 +803,6 @@ static void decode_RV32_64C0(DisasContext *ctx) uint8_t rs1s =3D GET_C_RS1S(ctx->opcode); =20 switch (funct3) { - case 0: - /* illegal */ - if (ctx->opcode =3D=3D 0) { - gen_exception_illegal(ctx); - } else { - /* C.ADDI4SPN -> addi rd', x2, zimm[9:2]*/ - gen_arith_imm(ctx, OPC_RISC_ADDI, rd_rs2, 2, - GET_C_ADDI4SPN_IMM(ctx->opcode)); - } - break; - case 1: - /* C.FLD -> fld rd', offset[7:3](rs1')*/ - gen_fp_load(ctx, OPC_RISC_FLD, rd_rs2, rs1s, - GET_C_LD_IMM(ctx->opcode)); - /* C.LQ(RV128) */ - break; - case 2: - /* C.LW -> lw rd', offset[6:2](rs1') */ - gen_load(ctx, OPC_RISC_LW, rd_rs2, rs1s, - GET_C_LW_IMM(ctx->opcode)); - break; case 3: #if defined(TARGET_RISCV64) /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/ @@ -835,21 +814,6 @@ static void decode_RV32_64C0(DisasContext *ctx) GET_C_LW_IMM(ctx->opcode)); #endif break; - case 4: - /* reserved */ - gen_exception_illegal(ctx); - break; - case 5: - /* C.FSD(RV32/64) -> fsd rs2', offset[7:3](rs1') */ - gen_fp_store(ctx, OPC_RISC_FSD, rs1s, rd_rs2, - GET_C_LD_IMM(ctx->opcode)); - /* C.SQ (RV128) */ - break; - case 6: - /* C.SW -> sw rs2', offset[6:2](rs1')*/ - gen_store(ctx, OPC_RISC_SW, rs1s, rd_rs2, - GET_C_LW_IMM(ctx->opcode)); - break; case 7: #if defined(TARGET_RISCV64) /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/ @@ -1079,6 +1043,8 @@ static void decode_RV32_64C(DisasContext *ctx) return imm << amount; \ } EX_SH(1) +EX_SH(2) +EX_SH(3) EX_SH(12) =20 #define REQUIRE_EXT(ctx, ext) do { \ @@ -1087,6 +1053,11 @@ EX_SH(12) } \ } while (0) =20 +static int ex_rvc_register(int reg) +{ + return 8 + reg; +} + bool decode_insn32(DisasContext *ctx, uint32_t insn); /* Include the auto-generated decoder for 32 bit insn */ #include "decode_insn32.inc.c" @@ -1098,6 +1069,11 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn); #include "insn_trans/trans_rvd.inc.c" #include "insn_trans/trans_privileged.inc.c" =20 +bool decode_insn16(DisasContext *ctx, uint16_t insn); +/* auto-generated decoder*/ +#include "decode_insn16.inc.c" +#include "insn_trans/trans_rvc.inc.c" + static void decode_RV32_64G(DisasContext *ctx) { int rs1, rd; @@ -1131,7 +1107,10 @@ static void decode_opc(DisasContext *ctx) gen_exception_illegal(ctx); } else { ctx->pc_succ_insn =3D ctx->base.pc_next + 2; - decode_RV32_64C(ctx); + if (!decode_insn16(ctx, ctx->opcode)) { + /* fall back to old decoder */ + decode_RV32_64C(ctx); + } } } else { ctx->pc_succ_insn =3D ctx->base.pc_next + 4; --=20 2.20.1