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X-Received-From: 2a00:1450:4864:20::434 Subject: [Qemu-devel] [PULL 15/21] hw/arm/armsse: Allow boards to specify init-svtor X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel/> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+importer=patchew.org@nongnu.org> X-ZohoMail-DKIM: fail (Header signature does not verify) The Musca boards have DAPLink firmware that sets the initial secure VTOR value (the location of the vector table) differently depending on the boot mode (from flash, from RAM, etc). Export the init-svtor as a QOM property of the ARMSSE object so that the board can change it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> --- include/hw/arm/armsse.h | 3 +++ hw/arm/armsse.c | 8 ++++---- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 444605b44dc..84879f40dd8 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -48,6 +48,8 @@ * if necessary.) * + QOM property "SRAM_ADDR_WIDTH" sets the number of bits used for the * address of each SRAM bank (and thus the total amount of internal SRA= M) + * + QOM property "init-svtor" sets the initial value of the CPU SVTOR re= gister + * (where it expects to load the PC and SP from the vector table on res= et) * + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CP= U 0, * which are wired to its NVIC lines 32 .. n+32 * + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts f= or @@ -204,6 +206,7 @@ typedef struct ARMSSE { uint32_t exp_numirq; uint32_t mainclk_frq; uint32_t sram_addr_width; + uint32_t init_svtor; } ARMSSE; =20 typedef struct ARMSSEInfo ARMSSEInfo; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index d0207dbabc7..50da41f64c5 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -505,11 +505,10 @@ static void armsse_realize(DeviceState *dev, Error **= errp) * the INITSVTOR* registers before powering up the CPUs in any cas= e, * so the hardware's default value doesn't matter. QEMU doesn't em= ulate * the control processor, so instead we behave in the way that the - * firmware does. All boards currently known about have firmware t= hat - * sets the INITSVTOR0 and INITSVTOR1 registers to 0x10000000, lik= e the - * IoTKit default. We can make this more configurable if necessary. + * firmware does. The initial value is configurable by the board c= ode + * to match whatever its firmware does. */ - qdev_prop_set_uint32(cpudev, "init-svtor", 0x10000000); + qdev_prop_set_uint32(cpudev, "init-svtor", s->init_svtor); /* * Start all CPUs except CPU0 powered down. In real hardware it is * a configurable property of the SSE-200 which CPUs start powered= up @@ -1187,6 +1186,7 @@ static Property armsse_properties[] =3D { DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0), DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), + DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), DEFINE_PROP_END_OF_LIST() }; =20 --=20 2.20.1