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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id c18sm29065085wre.32.2019.02.21.10.57.56 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 Feb 2019 10:57:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=CV0XuO7Jmju7b92elRHfSbeU/noy4D/dxWzQMm7SpKg=; b=LjkCOz6T+XgqaFiCPz0iM+efAj/5H4jwwW7ipWg05MP3ZttOP65tlnVyIkVTK712lZ T6zZpPuuCyCOEN1Wkixu3aLiGpzl0J9fkGR6pc9FryPmfWjhUPCx9cAqs9s7Q0IIxYIU TROwgnnfPrw0XgwYg6s3mdNuQPQFlfFaruF5O6lL0bOaIZDL8T1ZOKhpn5H6TFqj2oZZ oF2FSVNfo8tiR7pU2JJKTrOiOAsplWoRaVfj1KVZyUBihRMxn/It80PYRW1r4tVi0kL7 zQp1r5S+91wNYXb4kdSirCB2WHrThVvE0uenebB0AZH+FcHoCSk6eEwHAVeSQrxp4Rxr Z08Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CV0XuO7Jmju7b92elRHfSbeU/noy4D/dxWzQMm7SpKg=; b=K2j/3+tofi13NrebmchB04UP2FMSA6RldpX4Pp8oBOwcy0Snkw3N8fNHT0bGwQL4XA Q78oqIxyv/USsdu515q51V1lCGS9tyleO9EDmcYUkfd95kR8K618FRQ5gnPXM2psqwzM rtjyglGfQvbxsYxhNFZQmbhPcdWp15kstnow0yumn2kvpDe1yQJjlqKocqr+aVcPMJM6 4gZBEKQCiy26CgtnlKqIeVehGkV1e4ga7uXgUyRXGkuq2M8r8JGNADFEdf+pOI3AtKU2 N0LclK8nIw2lb4iF5YHohuIaXdq8CVHlTrQ/6uRImdh1yFk+9XrzLLf0IbdQOAur7YAz iuCw== X-Gm-Message-State: AHQUAubgtCdGKoTjSFeyShOWiUhxXxZ7hGztxkrHoXqxGbETJlywngQa CJXmdhGVTZoggxhENt+yTlpUvEZ7BT0= X-Google-Smtp-Source: AHgI3IY9B2k6wC/M5l8cQ2cx/ykSmGId2xrxE0rC52S33b9t/DiWgWOcDJXCgrg9hjwkrnQ8V2ZvUw== X-Received: by 2002:a1c:c282:: with SMTP id s124mr11158899wmf.105.1550775477726; Thu, 21 Feb 2019 10:57:57 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 21 Feb 2019 18:57:30 +0000 Message-Id: <20190221185739.25362-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190221185739.25362-1-peter.maydell@linaro.org> References: <20190221185739.25362-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PULL 12/21] hw/char/pl011: Support all interrupt lines X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The PL011 UART has six interrupt lines: * RX (receive data) * TX (transmit data) * RT (receive timeout) * MS (modem status) * E (errors) * combined (logical OR of all the above) So far we have only emulated the combined interrupt line; add support for the others, so that boards that wire them up to different interrupt controller inputs can do so. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/char/pl011.h | 2 +- hw/char/pl011.c | 46 +++++++++++++++++++++++++++++++++++++++-- 2 files changed, 45 insertions(+), 3 deletions(-) diff --git a/include/hw/char/pl011.h b/include/hw/char/pl011.h index 1b52bfd5c90..dad3cf29121 100644 --- a/include/hw/char/pl011.h +++ b/include/hw/char/pl011.h @@ -45,7 +45,7 @@ typedef struct PL011State { int read_count; int read_trigger; CharBackend chr; - qemu_irq irq; + qemu_irq irq[6]; const unsigned char *id; } PL011State; =20 diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 0c4711e4027..29f4e5eb224 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -7,6 +7,17 @@ * This code is licensed under the GPL. */ =20 +/* + * QEMU interface: + * + sysbus MMIO region 0: device registers + * + sysbus IRQ 0: UARTINTR (combined interrupt line) + * + sysbus IRQ 1: UARTRXINTR (receive FIFO interrupt line) + * + sysbus IRQ 2: UARTTXINTR (transmit FIFO interrupt line) + * + sysbus IRQ 3: UARTRTINTR (receive timeout interrupt line) + * + sysbus IRQ 4: UARTMSINTR (momem status interrupt line) + * + sysbus IRQ 5: UARTEINTR (error interrupt line) + */ + #include "qemu/osdep.h" #include "hw/char/pl011.h" #include "hw/sysbus.h" @@ -22,18 +33,46 @@ #define PL011_FLAG_TXFF 0x20 #define PL011_FLAG_RXFE 0x10 =20 +/* Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC */ +#define INT_OE (1 << 10) +#define INT_BE (1 << 9) +#define INT_PE (1 << 8) +#define INT_FE (1 << 7) +#define INT_RT (1 << 6) +#define INT_TX (1 << 5) +#define INT_RX (1 << 4) +#define INT_DSR (1 << 3) +#define INT_DCD (1 << 2) +#define INT_CTS (1 << 1) +#define INT_RI (1 << 0) +#define INT_E (INT_OE | INT_BE | INT_PE | INT_FE) +#define INT_MS (INT_RI | INT_DSR | INT_DCD | INT_CTS) + static const unsigned char pl011_id_arm[8] =3D { 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; static const unsigned char pl011_id_luminary[8] =3D { 0x11, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 }; =20 +/* Which bits in the interrupt status matter for each outbound IRQ line ? = */ +static const uint32_t irqmask[] =3D { + INT_E | INT_MS | INT_RT | INT_TX | INT_RX, /* combined IRQ */ + INT_RX, + INT_TX, + INT_RT, + INT_MS, + INT_E, +}; + static void pl011_update(PL011State *s) { uint32_t flags; + int i; =20 flags =3D s->int_level & s->int_enabled; trace_pl011_irq_state(flags !=3D 0); - qemu_set_irq(s->irq, flags !=3D 0); + for (i =3D 0; i < ARRAY_SIZE(s->irq); i++) { + qemu_set_irq(s->irq[i], (flags & irqmask[i]) !=3D 0); + } } =20 static uint64_t pl011_read(void *opaque, hwaddr offset, @@ -284,10 +323,13 @@ static void pl011_init(Object *obj) { SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); PL011State *s =3D PL011(obj); + int i; =20 memory_region_init_io(&s->iomem, OBJECT(s), &pl011_ops, s, "pl011", 0x= 1000); sysbus_init_mmio(sbd, &s->iomem); - sysbus_init_irq(sbd, &s->irq); + for (i =3D 0; i < ARRAY_SIZE(s->irq); i++) { + sysbus_init_irq(sbd, &s->irq[i]); + } =20 s->read_trigger =3D 1; s->ifl =3D 0x12; --=20 2.20.1