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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id k1sm23481857pgq.45.2019.02.20.15.50.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 20 Feb 2019 15:50:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=s2dodzZxHCDnrDgtvvvXGKkz5WlHrjD/GbbAljmEm3E=; b=QmtJ1RJSOZJSTa7Qz0CUPkm8VGFQf2gQinb5tMc+n/WdUH0NkZ+yquXB7J+0Hve8c/ hbmAoLLIbu82tyuXNIjfaDNPGM68lHTJMCB8dvETzPiyPTJ/IcnSqlGOqKPZ6AhVrhb9 rhhBcy5AWvK9zA/dsDOWbx1gm4oLJ/wNmblJT5bOd6UFsHkj4t4u8wcJQxiIB9qYXRWL MmkgeIlbUe4XlXU9CJDvKNnz68RJqSmJZjKlA8+vREUWPb1NxlAAJpnS5jQDNCQj0A2f UPKQxNXwfzvxTRbtfDN9NV4dCRnIWYTvrN8UWZpN0xjOhWsx63KsGJlCpHl7fsiJCJ2C VO4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=s2dodzZxHCDnrDgtvvvXGKkz5WlHrjD/GbbAljmEm3E=; b=thR+9N3jU36qTaNadYbKxsUcJT+52EHLBVSITIVGCamqQfsyMVO0QAG6nGJ2mLUf5Z 6jhSo6Pd0K9Fgglk8HEq0BDSxXtW/b/vqeb3f9HgLUu86nf7VuM3KloJWaYGRNpr/ThQ 7K6iOwkgIf/3IZFN1Y6CNRxmMa7ORUYx/M4PYiStO6HdPjj2M4i4sWyDRNUaM0fQLuB7 ImSmXy+6A1ALA9vn8jVCYNon0W2QUamlxzOavYo6OVIwxrslaOrefmG/S9BXatKipqPd sP2+hGn2peuy7tCeJsrhIivK+HYV2ivS6opUj+pu1gWJcC3GS/9wxtu5VxVB2kKqqE08 tNkA== X-Gm-Message-State: AHQUAuaSclj60ci9P3iUW3gOlqjcWfbcaEz+WyqA3I0bTUo0nJYb4jCK 9Qi1H3C+7zYODRcq4pFY7ru5zk1v0W0= X-Google-Smtp-Source: AHgI3IZkxwJj8jkiyp+YYCyrQUEWxiUAeWTBUdu8gBJF65bfFi1U2dK2MYiaouMknpMwcVo1q1thng== X-Received: by 2002:a62:2a4b:: with SMTP id q72mr36995453pfq.61.1550706621068; Wed, 20 Feb 2019 15:50:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 20 Feb 2019 15:50:16 -0800 Message-Id: <20190220235017.1060-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190220235017.1060-1-richard.henderson@linaro.org> References: <20190220235017.1060-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH 1/2] target/arm: Implement ARMv8.0-SB X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/cpu.h | 10 ++++++++++ linux-user/elfload.c | 1 + target/arm/cpu.c | 1 + target/arm/cpu64.c | 2 ++ target/arm/translate-a64.c | 14 ++++++++++++++ target/arm/translate.c | 22 ++++++++++++++++++++++ 6 files changed, 50 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0480f9baba..76d6a73c0e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3302,6 +3302,11 @@ static inline bool isar_feature_aa32_dp(const ARMISA= Registers *id) return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) !=3D 0; } =20 +static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) !=3D 0; +} + static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) { /* @@ -3405,6 +3410,11 @@ static inline bool isar_feature_aa64_pauth(const ARM= ISARegisters *id) FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) !=3D 0; } =20 +static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) !=3D 0; +} + static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) { /* We always set the AdvSIMD and FP fields identically wrt FP16. */ diff --git a/linux-user/elfload.c b/linux-user/elfload.c index ef7138839d..02ba705e73 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -603,6 +603,7 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE_ID(aa64_sve, ARM_HWCAP_A64_SVE); GET_FEATURE_ID(aa64_pauth, ARM_HWCAP_A64_PACA | ARM_HWCAP_A64_PACG); GET_FEATURE_ID(aa64_condm_4, ARM_HWCAP_A64_FLAGM); + GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB); =20 #undef GET_FEATURE_ID =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a5599ae19f..5cd27f2f64 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2027,6 +2027,7 @@ static void arm_max_initfn(Object *obj) =20 t =3D cpu->isar.id_isar6; t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); cpu->isar.id_isar6 =3D t; =20 t =3D cpu->id_mmfr4; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index fc54734256..95c6ee4cda 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -343,6 +343,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR1, API, 0); t =3D FIELD_DP64(t, ID_AA64ISAR1, GPA, 1); t =3D FIELD_DP64(t, ID_AA64ISAR1, GPI, 0); + t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); cpu->isar.id_aa64isar1 =3D t; =20 t =3D cpu->isar.id_aa64pfr0; @@ -373,6 +374,7 @@ static void aarch64_max_initfn(Object *obj) =20 u =3D cpu->isar.id_isar6; u =3D FIELD_DP32(u, ID_ISAR6, DP, 1); + u =3D FIELD_DP32(u, ID_ISAR6, SB, 1); cpu->isar.id_isar6 =3D u; =20 /* diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 1d9bf81c0e..40c4f2fe54 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1638,7 +1638,21 @@ static void handle_sync(DisasContext *s, uint32_t in= sn, reset_btype(s); gen_goto_tb(s, 0, s->pc); return; + + case 7: /* SB */ + if (crm !=3D 0 || !dc_isar_feature(aa64_sb, s)) { + goto do_unallocated; + } + /* + * TODO: There is no speculation barrier opcode for TCG; + * MB and end the TB instead. + */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + s->base.is_jmp =3D DISAS_TOO_MANY; + return; + default: + do_unallocated: unallocated_encoding(s); return; } diff --git a/target/arm/translate.c b/target/arm/translate.c index 92f0c8d557..796ba2df43 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9192,6 +9192,17 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) */ gen_goto_tb(s, 0, s->pc & ~1); return; + case 7: /* sb */ + if (!dc_isar_feature(aa32_sb, s)) { + goto illegal_op; + } + /* + * TODO: There is no speculation barrier opcode + * for TCG; MB and end the TB instead. + */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + s->base.is_jmp =3D DISAS_TOO_MANY; + return; default: goto illegal_op; } @@ -11810,6 +11821,17 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) */ gen_goto_tb(s, 0, s->pc & ~1); break; + case 7: /* sb */ + if (!dc_isar_feature(aa32_sb, s)) { + goto illegal_op; + } + /* + * TODO: There is no speculation barrier opcode + * for TCG; MB and end the TB instead. + */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + s->base.is_jmp =3D DISAS_TOO_MANY; + break; default: goto illegal_op; } --=20 2.17.2 From nobody Sun Nov 9 11:39:55 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id k1sm23481857pgq.45.2019.02.20.15.50.21 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 20 Feb 2019 15:50:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xt1nYlp2eDwGcgAYWlANS9A7Z4PMSwb2UDIXUx77QYk=; b=wpZzb/MU1UReKoszNHWxnwyGv5PAX+nka4L4JLk2wcfw6+SnOkod8BjFPgVnUTBTJg BcHysvLWhcKNYUvu3pBfIv1dLYVnZC5tWTJNKfvaxt7QtyW4j4/lEFdRyeqhNB4HSX4V bazaeEtT4JxJm8mC7gUYF0GNpvW+lNBmLjRyhskfq8kLRlIb74Q2cXbks0J/R+F4e8X8 eLaJ1XVUmLJT+3Klto1xfD2rpRiaw/ggOuFCMiGhOIp9xeM44frBPIWqwHy7vsMBaD6d ZmdFwtFD3iTCH9b9SIhLiEHq60lXNxPPjl3PeiQMgX2KnB+19fzBHeDn8/DplFlMklxE XXpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xt1nYlp2eDwGcgAYWlANS9A7Z4PMSwb2UDIXUx77QYk=; b=oFDTr5pU/wlElGkKQGaWePK8cyTkGpAqRq9ZesjF4xrNJDYZ1wFt6LDoqCpT75o34O vfoLZ4Tcg6aXAaxHIPzbcQga06jToNJ4xQE7ucwPhqpOplP7+1sJmDoYeb6ASjUe/cGf 3Duhx820uPmxZDC2KyOCVaYc/3fz7UZ8XZ+iVzmjZCUhHtCKK7rtxQaxlLg3e1o0LC1A cbOdQ+6D+52NNF7rebIBIkc2MiUvU8T0I6kk7c/ZNlu8aLG+QFCKrxBXVBPr+L2wneZ7 BKqF0vKOAnqz2CNB17bLSTtvCf2qI4HHse/nzRNM6R4qUHTjCIc6ywJLfnjGAc17+vge MsmA== X-Gm-Message-State: AHQUAuYRAJw4HNzTkr85tHpYo9REc6EWeCWgudrpVB+B+VPQ3kj+XvO8 rkZ3vexN8cRdBfNu/JKpnJ5A3mqjOp4= X-Google-Smtp-Source: AHgI3IYWd5ZyTak700yHCBzJRtSzJJxDhmjSLnt/DNRbNrQDGnH0Pogcc77bY0J2ln0KZ6AEHrvOUQ== X-Received: by 2002:a62:9913:: with SMTP id d19mr37348611pfe.107.1550706622316; Wed, 20 Feb 2019 15:50:22 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 20 Feb 2019 15:50:17 -0800 Message-Id: <20190220235017.1060-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190220235017.1060-1-richard.henderson@linaro.org> References: <20190220235017.1060-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::536 Subject: [Qemu-devel] [PATCH 2/2] target/arm: Implement ARMv8.0-PredRes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is named "Execution and Data prediction restriction instructions" within the ARMv8.5 manual, and given the name "PredRes" by binutils. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 11 ++++++++++ target/arm/cpu.c | 1 + target/arm/cpu64.c | 2 ++ target/arm/helper.c | 49 +++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 63 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 76d6a73c0e..202ff1f1ea 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1074,6 +1074,7 @@ void pmu_init(ARMCPU *cpu); #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ #define SCTLR_F (1U << 10) /* up to v6 */ #define SCTLR_SW (1U << 10) /* v7, RES0 in v8 */ +#define SCTLR_EnRCTX (1U << 10) /* in v8.0-specres */ #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ #define SCTLR_I (1U << 12) @@ -3307,6 +3308,11 @@ static inline bool isar_feature_aa32_sb(const ARMISA= Registers *id) return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) !=3D 0; } =20 +static inline bool isar_feature_aa32_specres(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) !=3D 0; +} + static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) { /* @@ -3415,6 +3421,11 @@ static inline bool isar_feature_aa64_sb(const ARMISA= Registers *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) !=3D 0; } =20 +static inline bool isar_feature_aa64_specres(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) !=3D 0; +} + static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) { /* We always set the AdvSIMD and FP fields identically wrt FP16. */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5cd27f2f64..c1d2848baa 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2028,6 +2028,7 @@ static void arm_max_initfn(Object *obj) t =3D cpu->isar.id_isar6; t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); cpu->isar.id_isar6 =3D t; =20 t =3D cpu->id_mmfr4; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 95c6ee4cda..5f273399db 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -344,6 +344,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR1, GPA, 1); t =3D FIELD_DP64(t, ID_AA64ISAR1, GPI, 0); t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); cpu->isar.id_aa64isar1 =3D t; =20 t =3D cpu->isar.id_aa64pfr0; @@ -375,6 +376,7 @@ static void aarch64_max_initfn(Object *obj) u =3D cpu->isar.id_isar6; u =3D FIELD_DP32(u, ID_ISAR6, DP, 1); u =3D FIELD_DP32(u, ID_ISAR6, SB, 1); + u =3D FIELD_DP32(u, ID_ISAR6, SPECRES, 1); cpu->isar.id_isar6 =3D u; =20 /* diff --git a/target/arm/helper.c b/target/arm/helper.c index a2ab300051..c34b1401bd 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5884,6 +5884,50 @@ static const ARMCPRegInfo mte_reginfo[] =3D { }; #endif =20 +static CPAccessResult access_specres(CPUARMState *env, const ARMCPRegInfo = *ri, + bool isread) +{ + int el =3D arm_current_el(env); + + if (el =3D=3D 0) { + uint64_t sctlr =3D arm_sctlr(env, el); + if (!(sctlr & SCTLR_EnRCTX)) { + return CP_ACCESS_TRAP; + } + } else if (el =3D=3D 1) { + uint64_t hcr =3D arm_hcr_el2_eff(env); + if (hcr & HCR_NV) { + return CP_ACCESS_TRAP_EL2; + } + } + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo specres_reginfo[] =3D { + { .name =3D "CFP_RCTX", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 3, .opc2 =3D 4, + .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_specre= s }, + { .name =3D "DVP_RCTX", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 3, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_specre= s }, + { .name =3D "CPP_RCTX", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 3, .opc2 =3D 7, + .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_specre= s }, + /* + * Note the AArch32 opcodes have a different OPC1. + */ + { .name =3D "CFPRCTX", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 3, .opc2 =3D 4, + .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_specre= s }, + { .name =3D "DVPRCTX", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 3, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_specre= s }, + { .name =3D "CPPRCTX", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 3, .opc2 =3D 7, + .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_specre= s }, + REGINFO_SENTINEL +}; + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -6786,6 +6830,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, mte_reginfo); } #endif + + /* All v8.0-a cpus support aarch64. */ + if (cpu_isar_feature(aa64_specres, cpu)) { + define_arm_cp_regs(cpu, specres_reginfo); + } } =20 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) --=20 2.17.2