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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id l184sm24356988pfc.41.2019.02.19.15.34.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Feb 2019 15:34:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xNPxzqFIHE0gMEyUUC0ehr09JL/Fyw0bCZU6XF8Rpg0=; b=EH6v2f5JEtEPFDghDlJtlFIlyJehStKJcTuKFSpHVNANsupbSbY3KgwViaYLDY7jiG rvdkH1t5Ooa3p/O/XktFdcY8KwfBtVabOd4oESYYaDRMeX1GBbcu7OOmuffCjzHcKWI+ 1St3/Dkq/x4ywksLjqhbSxPnb/w8q9NWovNcTtuRUN6hNv1KE4+ocQ+j/GvO6uoZtIRu J+KbLKUxa8P/pJDp6HSjhYGjs8dfoQudPDRXotbnaDvtHLdlfqJ3/Xnm3/KrCEZJY+1d 9jCis7Hx10CSNEBRGCqPF8p+Mwb8E0EQRmtR+F1vzHsn6LAgetOJKaOXyBOsoCFbfC4A 79xw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xNPxzqFIHE0gMEyUUC0ehr09JL/Fyw0bCZU6XF8Rpg0=; b=aCGIYQAIJwR+tzafS9SYveVDTppcbauuFoqfXY0iB5RWy5lXgfSaz/mTEy+KfUBHNx zMOg8mECuXJDn9V7Ns0pWsbZYmMWP9unuDAXt+U4wQ6qyPNcJ764kIhJOHHJgXbc9+xB 8v9CZO+8yOKB2xLwFJdiNk/qIEUH7zzs9zA1oFri9wbhoS3ulTDilzPwYoFdb5p0s4C4 iMtQCsZaZn9K48qw6WZ1Q6/5AZByKlIX8NlZ5pyBssQZhpsPwauxohhs5lDgktXNDOyq z0nunNFMocMvIqRKD7umtHCHdMQzXkhUVQVsNj8IYVokR/a1kMFCpc2AMBCSN4xQ5cti oJ2g== X-Gm-Message-State: AHQUAubxLom5gE2fGKhMNxy3d4a58ihc2e0IEt7JhHHpx81xmY+6PiQ8 FStXLGs3aRr+BUbub3DFn2vqGzn6oc8= X-Google-Smtp-Source: AHgI3IZk9bLhVPKrw4S0UtFtWxwvYsBzKRECGfTWICOiMe2bSsilJvFFBWQIv4D8tcuQYAStB5tKfQ== X-Received: by 2002:a17:902:14e:: with SMTP id 72mr33790276plb.287.1550619264814; Tue, 19 Feb 2019 15:34:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 19 Feb 2019 15:34:19 -0800 Message-Id: <20190219233421.388-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190219233421.388-1-richard.henderson@linaro.org> References: <20190219233421.388-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::636 Subject: [Qemu-devel] [PATCH v2 1/3] target/arm: Split out recompute_hflags et al X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, cota@braap.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) We will use these to minimize the computation for every call to cpu_get_tb_cpu_state. For now, the env->hflags variable is not used. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/arm/cpu.h | 22 +++- target/arm/helper.h | 3 + target/arm/internals.h | 3 + target/arm/helper.c | 267 ++++++++++++++++++++++++----------------- 4 files changed, 179 insertions(+), 116 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 84ae6849c2..848f0926eb 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -240,6 +240,9 @@ typedef struct CPUARMState { uint32_t pstate; uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.n= RW */ =20 + /* Cached TBFLAGS state. See below for which bits are included. */ + uint32_t hflags; + /* Frequently accessed CPSR bits are stored separately for efficiency. This contains all the other bits. Use cpsr_{read,write} to access the whole CPSR. */ @@ -3065,25 +3068,28 @@ static inline bool arm_cpu_data_is_big_endian(CPUAR= MState *env) =20 #include "exec/cpu-all.h" =20 -/* Bit usage in the TB flags field: bit 31 indicates whether we are +/* + * Bit usage in the TB flags field: bit 31 indicates whether we are * in 32 or 64 bit mode. The meaning of the other bits depends on that. * We put flags which are shared between 32 and 64 bit mode at the top * of the word, and flags which apply to only one mode at the bottom. + * + * Unless otherwise noted, these bits are cached in env->hflags. */ FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) FIELD(TBFLAG_ANY, MMUIDX, 28, 3) FIELD(TBFLAG_ANY, SS_ACTIVE, 27, 1) -FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) +FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) /* Not cached. */ /* Target EL if we take a floating-point-disabled exception */ FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2) FIELD(TBFLAG_ANY, BE_DATA, 23, 1) =20 /* Bit usage when in AArch32 state: */ -FIELD(TBFLAG_A32, THUMB, 0, 1) +FIELD(TBFLAG_A32, THUMB, 0, 1) /* Not cached. */ FIELD(TBFLAG_A32, VECLEN, 1, 3) FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) FIELD(TBFLAG_A32, VFPEN, 7, 1) -FIELD(TBFLAG_A32, CONDEXEC, 8, 8) +FIELD(TBFLAG_A32, CONDEXEC, 8, 8) /* Not cached. */ FIELD(TBFLAG_A32, SCTLR_B, 16, 1) /* We store the bottom two bits of the CPAR as TB flags and handle * checks on the other bits at runtime @@ -3105,7 +3111,7 @@ FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) FIELD(TBFLAG_A64, BT, 9, 1) -FIELD(TBFLAG_A64, BTYPE, 10, 2) +FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ FIELD(TBFLAG_A64, TBID, 12, 2) =20 static inline bool bswap_code(bool sctlr_b) @@ -3190,6 +3196,12 @@ void arm_register_pre_el_change_hook(ARMCPU *cpu, AR= MELChangeHookFn *hook, void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void *opaque); =20 +/** + * arm_rebuild_hflags: + * Rebuild the cached TBFLAGS for arbitrary changed processor state. + */ +void arm_rebuild_hflags(CPUARMState *env); + /** * aa32_vfp_dreg: * Return a pointer to the Dn register within env in 32-bit mode. diff --git a/target/arm/helper.h b/target/arm/helper.h index 923e8e1525..bbc1a48089 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -89,6 +89,9 @@ DEF_HELPER_4(msr_banked, void, env, i32, i32, i32) DEF_HELPER_2(get_user_reg, i32, env, i32) DEF_HELPER_3(set_user_reg, void, env, i32, i32) =20 +DEF_HELPER_FLAGS_2(rebuild_hflags_a32, TCG_CALL_NO_RWG, void, env, i32) +DEF_HELPER_FLAGS_2(rebuild_hflags_a64, TCG_CALL_NO_RWG, void, env, i32) + DEF_HELPER_1(vfp_get_fpscr, i32, env) DEF_HELPER_2(vfp_set_fpscr, void, env, i32) =20 diff --git a/target/arm/internals.h b/target/arm/internals.h index a4bd1becb7..8c1b813364 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -968,4 +968,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *en= v, uint64_t va, ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data); =20 +uint32_t rebuild_hflags_a32(CPUARMState *env, int el); +uint32_t rebuild_hflags_a64(CPUARMState *env, int el); + #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index a018eb23fe..189e97a083 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13886,122 +13886,15 @@ ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) } #endif =20 -void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, - target_ulong *cs_base, uint32_t *pflags) +static uint32_t common_hflags(CPUARMState *env, int el, ARMMMUIdx mmu_idx, + int fp_el, uint32_t flags) { - ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); - int current_el =3D arm_current_el(env); - int fp_el =3D fp_exception_el(env, current_el); - uint32_t flags =3D 0; - - if (is_a64(env)) { - ARMCPU *cpu =3D arm_env_get_cpu(env); - uint64_t sctlr; - - *pc =3D env->pc; - flags =3D FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); - - /* Get control bits for tagged addresses. */ - { - ARMMMUIdx stage1 =3D stage_1_mmu_idx(mmu_idx); - ARMVAParameters p0 =3D aa64_va_parameters_both(env, 0, stage1); - int tbii, tbid; - - /* FIXME: ARMv8.1-VHE S2 translation regime. */ - if (regime_el(env, stage1) < 2) { - ARMVAParameters p1 =3D aa64_va_parameters_both(env, -1, st= age1); - tbid =3D (p1.tbi << 1) | p0.tbi; - tbii =3D tbid & ~((p1.tbid << 1) | p0.tbid); - } else { - tbid =3D p0.tbi; - tbii =3D tbid & !p0.tbid; - } - - flags =3D FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); - flags =3D FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); - } - - if (cpu_isar_feature(aa64_sve, cpu)) { - int sve_el =3D sve_exception_el(env, current_el); - uint32_t zcr_len; - - /* If SVE is disabled, but FP is enabled, - * then the effective len is 0. - */ - if (sve_el !=3D 0 && fp_el =3D=3D 0) { - zcr_len =3D 0; - } else { - zcr_len =3D sve_zcr_len_for_el(env, current_el); - } - flags =3D FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el); - flags =3D FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); - } - - if (current_el =3D=3D 0) { - /* FIXME: ARMv8.1-VHE S2 translation regime. */ - sctlr =3D env->cp15.sctlr_el[1]; - } else { - sctlr =3D env->cp15.sctlr_el[current_el]; - } - if (cpu_isar_feature(aa64_pauth, cpu)) { - /* - * In order to save space in flags, we record only whether - * pauth is "inactive", meaning all insns are implemented as - * a nop, or "active" when some action must be performed. - * The decision of which action to take is left to a helper. - */ - if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB= )) { - flags =3D FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1); - } - } - - if (cpu_isar_feature(aa64_bti, cpu)) { - /* Note that SCTLR_EL[23].BT =3D=3D SCTLR_BT1. */ - if (sctlr & (current_el =3D=3D 0 ? SCTLR_BT0 : SCTLR_BT1)) { - flags =3D FIELD_DP32(flags, TBFLAG_A64, BT, 1); - } - flags =3D FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); - } - } else { - *pc =3D env->regs[15]; - flags =3D FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); - flags =3D FIELD_DP32(flags, TBFLAG_A32, VECLEN, env->vfp.vec_len); - flags =3D FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_st= ride); - flags =3D FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bi= ts); - flags =3D FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env)); - flags =3D FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env= )); - if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) - || arm_el_is_aa64(env, 1)) { - flags =3D FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); - } - flags =3D FIELD_DP32(flags, TBFLAG_A32, XSCALE_CPAR, env->cp15.c15= _cpar); - } - flags =3D FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, arm_to_core_mmu_idx(mm= u_idx)); + flags =3D FIELD_DP32(flags, TBFLAG_ANY, FPEXC_EL, fp_el); =20 - /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine - * states defined in the ARM ARM for software singlestep: - * SS_ACTIVE PSTATE.SS State - * 0 x Inactive (the TB flag for SS is always 0) - * 1 0 Active-pending - * 1 1 Active-not-pending - */ - if (arm_singlestep_active(env)) { - flags =3D FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1); - if (is_a64(env)) { - if (env->pstate & PSTATE_SS) { - flags =3D FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); - } - } else { - if (env->uncached_cpsr & PSTATE_SS) { - flags =3D FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); - } - } - } if (arm_cpu_data_is_big_endian(env)) { flags =3D FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); } - flags =3D FIELD_DP32(flags, TBFLAG_ANY, FPEXC_EL, fp_el); =20 if (arm_v7m_is_handler_mode(env)) { flags =3D FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1); @@ -14017,8 +13910,160 @@ void cpu_get_tb_cpu_state(CPUARMState *env, targe= t_ulong *pc, flags =3D FIELD_DP32(flags, TBFLAG_A32, STACKCHECK, 1); } =20 - *pflags =3D flags; + if (arm_singlestep_active(env)) { + flags =3D FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1); + } + + return flags; +} + +uint32_t rebuild_hflags_a32(CPUARMState *env, int el) +{ + uint32_t flags =3D 0; + ARMMMUIdx mmu_idx; + int fp_el; + + flags =3D FIELD_DP32(flags, TBFLAG_A32, VECLEN, env->vfp.vec_len); + flags =3D FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_stride= ); + flags =3D FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env)); + flags =3D FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env)); + if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) + || arm_el_is_aa64(env, 1)) { + flags =3D FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); + } + flags =3D FIELD_DP32(flags, TBFLAG_A32, XSCALE_CPAR, env->cp15.c15_cpa= r); + + mmu_idx =3D arm_mmu_idx(env); + fp_el =3D fp_exception_el(env, el); + return common_hflags(env, el, mmu_idx, fp_el, flags); +} + +uint32_t rebuild_hflags_a64(CPUARMState *env, int el) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); + ARMMMUIdx stage1 =3D stage_1_mmu_idx(mmu_idx); + ARMVAParameters p0 =3D aa64_va_parameters_both(env, 0, stage1); + int fp_el =3D fp_exception_el(env, el); + uint32_t flags =3D 0; + uint64_t sctlr; + int tbii, tbid; + + flags =3D FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); + + /* Get control bits for tagged addresses. */ + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + if (regime_el(env, stage1) < 2) { + ARMVAParameters p1 =3D aa64_va_parameters_both(env, -1, stage1); + tbid =3D (p1.tbi << 1) | p0.tbi; + tbii =3D tbid & ~((p1.tbid << 1) | p0.tbid); + } else { + tbid =3D p0.tbi; + tbii =3D tbid & !p0.tbid; + } + + flags =3D FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); + flags =3D FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); + + if (cpu_isar_feature(aa64_sve, cpu)) { + int sve_el =3D sve_exception_el(env, el); + uint32_t zcr_len; + + /* If SVE is disabled, but FP is enabled, + * then the effective len is 0. + */ + if (sve_el !=3D 0 && fp_el =3D=3D 0) { + zcr_len =3D 0; + } else { + zcr_len =3D sve_zcr_len_for_el(env, el); + } + flags =3D FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el); + flags =3D FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); + } + + if (el =3D=3D 0) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + sctlr =3D env->cp15.sctlr_el[1]; + } else { + sctlr =3D env->cp15.sctlr_el[el]; + } + if (cpu_isar_feature(aa64_pauth, cpu)) { + /* + * In order to save space in flags, we record only whether + * pauth is "inactive", meaning all insns are implemented as + * a nop, or "active" when some action must be performed. + * The decision of which action to take is left to a helper. + */ + if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { + flags =3D FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1); + } + } + + if (cpu_isar_feature(aa64_bti, cpu)) { + /* Note that SCTLR_EL[23].BT =3D=3D SCTLR_BT1. */ + if (sctlr & (el =3D=3D 0 ? SCTLR_BT0 : SCTLR_BT1)) { + flags =3D FIELD_DP32(flags, TBFLAG_A64, BT, 1); + } + } + + return common_hflags(env, el, mmu_idx, fp_el, flags); +} + +void arm_rebuild_hflags(CPUARMState *env) +{ + int el =3D arm_current_el(env); + env->hflags =3D (is_a64(env) + ? rebuild_hflags_a64(env, el) + : rebuild_hflags_a32(env, el)); +} + +void HELPER(rebuild_hflags_a32)(CPUARMState *env, uint32_t el) +{ + tcg_debug_assert(!is_a64(env)); + env->hflags =3D rebuild_hflags_a32(env, el); +} + +void HELPER(rebuild_hflags_a64)(CPUARMState *env, uint32_t el) +{ + tcg_debug_assert(is_a64(env)); + env->hflags =3D rebuild_hflags_a64(env, el); +} + +void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, + target_ulong *cs_base, uint32_t *pflags) +{ + int current_el =3D arm_current_el(env); + uint32_t flags; + uint32_t pstate_for_ss; + *cs_base =3D 0; + if (is_a64(env)) { + *pc =3D env->pc; + flags =3D rebuild_hflags_a64(env, current_el); + flags =3D FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); + pstate_for_ss =3D env->pstate; + } else { + *pc =3D env->regs[15]; + flags =3D rebuild_hflags_a32(env, current_el); + flags =3D FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); + flags =3D FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bi= ts); + pstate_for_ss =3D env->uncached_cpsr; + } + + /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine + * states defined in the ARM ARM for software singlestep: + * SS_ACTIVE PSTATE.SS State + * 0 x Inactive (the TB flag for SS is always 0) + * 1 0 Active-pending + * 1 1 Active-not-pending + * SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB. + */ + if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE) + && (pstate_for_ss & PSTATE_SS)) { + flags =3D FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); + } + + *pflags =3D flags; } =20 #ifdef TARGET_AARCH64 --=20 2.17.1 From nobody Sun May 5 23:59:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1550619406326744.5066228327283; Tue, 19 Feb 2019 15:36:46 -0800 (PST) Received: from localhost ([127.0.0.1]:56593 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gwEwH-0000C2-7S for importer@patchew.org; Tue, 19 Feb 2019 18:36:37 -0500 Received: from eggs.gnu.org ([209.51.188.92]:57496) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gwEuK-0007Xr-LB for qemu-devel@nongnu.org; Tue, 19 Feb 2019 18:34:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gwEuJ-0001WZ-IN for qemu-devel@nongnu.org; Tue, 19 Feb 2019 18:34:36 -0500 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:38557) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gwEuI-0001RL-IU for qemu-devel@nongnu.org; Tue, 19 Feb 2019 18:34:35 -0500 Received: by mail-pf1-x442.google.com with SMTP id n125so3674815pfn.5 for ; Tue, 19 Feb 2019 15:34:27 -0800 (PST) Received: from localhost.localdomain (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id l184sm24356988pfc.41.2019.02.19.15.34.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Feb 2019 15:34:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VSVGBr1WAPnIab8WbZvX9jtmivC+xkyA82Y++ZHcefc=; b=YL7wa7Kzxny5NS0BtB2aCuYCaIcjolPNCoKL/G4qQUkOjtzQFoEyhkq8XBr2v6Mfgs D78rarRNUAf9KKY5oH2SQ7Tz8fMg/Dpbz2+RaWQXM32AcuLX24sBb3uTBrErpY0fjINx uf0Vp9+f59YqsJvHVkDBLaI7ZBR8UYEze7lEj7oAflEPMbQBuRTV8uK4Khs2YxzUIMB0 9OLXDc618N96h+YQKbZHj4EGHAiSF+Zc9DZzv6PjLbJV1MnH3j6CemNV8z20UyTFRHdR 6aIuY3ZE4aiZQySi0iBMCHwJkSNwuV+pFsWXaXS8rAzhaY+pdSuAJiRUnhMUQ+3auXpH yvvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VSVGBr1WAPnIab8WbZvX9jtmivC+xkyA82Y++ZHcefc=; b=fuxZwGQ2C5P/PT4NKFxIvK3xOQbxLkr1NezfJzYgXkqMrGTZ5p5uDBmpHG4hUMoO6x WlVCO5qTilfctgY4Ynf+vCxel6yytN+zGpCZ9q21e0J4Vg3cN1nRavqZzA5IwlOX8CbK PV+geCoeOvoeBqXPC2rCFhNqAyZH36JRhXP6SM1yntp474vRJQszvc/r3lO4ofyOSB2d NkIqcLW7CiiU6WtALNZRQa3n9mlr0Oyg2w3KXlWIOp+1ZykL9gqGoRAw5zvFRVENOepN YYykddKXvbuw7e89p4PkWd6c7pOC1qglsjJ/fTglr7EWdwadHq7uoEi4QTyq9+f9Jl8f STDg== X-Gm-Message-State: AHQUAuZYFWc9JcrfJ5R8KRO8V4zbyNAMePisYF4Vh0Txk+RAryXg+2Qk hxL5mmh1i7NQwDQsoPhCqcH31PuYrPY= X-Google-Smtp-Source: AHgI3IapWZqGS7/3ntzN2ahwd24yml0Pqkb2deIbTAbB6bPxyPSbdTOHZ7vUgWAxtCJhbo42T/ONIw== X-Received: by 2002:a63:4d4f:: with SMTP id n15mr26380521pgl.327.1550619265814; Tue, 19 Feb 2019 15:34:25 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 19 Feb 2019 15:34:20 -0800 Message-Id: <20190219233421.388-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190219233421.388-1-richard.henderson@linaro.org> References: <20190219233421.388-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v2 2/3] target/arm: Rebuild hflags at el changes and MSR writes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, cota@braap.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Now setting, but not relying upon, env->hflags. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- v2: Fixed partial conversion to assignment to env->hflags. --- target/arm/internals.h | 1 + linux-user/syscall.c | 1 + target/arm/cpu.c | 1 + target/arm/helper-a64.c | 3 +++ target/arm/helper.c | 2 ++ target/arm/machine.c | 1 + target/arm/op_helper.c | 1 + target/arm/translate-a64.c | 6 +++++- target/arm/translate.c | 14 ++++++++++++-- 9 files changed, 27 insertions(+), 3 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 8c1b813364..235f4fafec 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -970,5 +970,6 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, ui= nt64_t va, =20 uint32_t rebuild_hflags_a32(CPUARMState *env, int el); uint32_t rebuild_hflags_a64(CPUARMState *env, int el); +void rebuild_hflags_any(CPUARMState *env); =20 #endif diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 5bbb72f3d5..123f342bdc 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -9691,6 +9691,7 @@ static abi_long do_syscall1(void *cpu_env, int num, a= bi_long arg1, aarch64_sve_narrow_vq(env, vq); } env->vfp.zcr_el[1] =3D vq - 1; + arm_rebuild_hflags(env); ret =3D vq * 16; } return ret; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index edf6e0e1f1..e4da513eb3 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -390,6 +390,7 @@ static void arm_cpu_reset(CPUState *s) =20 hw_breakpoint_update_all(cpu); hw_watchpoint_update_all(cpu); + arm_rebuild_hflags(env); } =20 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 70850e564d..17200f1288 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -995,6 +995,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_= t new_pc) } else { env->regs[15] =3D new_pc & ~0x3; } + env->hflags =3D rebuild_hflags_a32(env, new_el); qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " "AArch32 EL%d PC 0x%" PRIx32 "\n", cur_el, new_el, env->regs[15]); @@ -1006,10 +1007,12 @@ void HELPER(exception_return)(CPUARMState *env, uin= t64_t new_pc) } aarch64_restore_sp(env, new_el); env->pc =3D new_pc; + env->hflags =3D rebuild_hflags_a64(env, new_el); qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " "AArch64 EL%d PC 0x%" PRIx64 "\n", cur_el, new_el, env->pc); } + /* * Note that cur_el can never be 0. If new_el is 0, then * el0_a64 is return_to_aa64, else el0_a64 is ignored. diff --git a/target/arm/helper.c b/target/arm/helper.c index 189e97a083..909535a3e3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9201,6 +9201,7 @@ static void take_aarch32_exception(CPUARMState *env, = int new_mode, env->regs[14] =3D env->regs[15] + offset; } env->regs[15] =3D newpc; + env->hflags =3D rebuild_hflags_a32(env, arm_current_el(env)); } =20 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) @@ -9546,6 +9547,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) =20 pstate_write(env, PSTATE_DAIF | new_mode); env->aarch64 =3D 1; + env->hflags =3D rebuild_hflags_a64(env, new_el); aarch64_restore_sp(env, new_el); =20 env->pc =3D addr; diff --git a/target/arm/machine.c b/target/arm/machine.c index 124192bfc2..e944d6b736 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -743,6 +743,7 @@ static int cpu_post_load(void *opaque, int version_id) if (!kvm_enabled()) { pmu_op_finish(&cpu->env); } + arm_rebuild_hflags(&cpu->env); =20 return 0; } diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index c998eadfaa..f82eeae7e4 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -571,6 +571,7 @@ void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t= val) */ env->regs[15] &=3D (env->thumb ? ~1 : ~3); =20 + env->hflags =3D rebuild_hflags_a32(env, arm_current_el(env)); qemu_mutex_lock_iothread(); arm_call_el_change_hook(arm_env_get_cpu(env)); qemu_mutex_unlock_iothread(); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index af8e4fd4be..a786c7ef5f 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1841,11 +1841,15 @@ static void handle_sys(DisasContext *s, uint32_t in= sn, bool isread, /* I/O operations must end the TB here (whether read or write) */ gen_io_end(); s->base.is_jmp =3D DISAS_UPDATE; - } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { + } + if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { /* We default to ending the TB on a coprocessor register write, * but allow this to be suppressed by the register definition * (usually only necessary to work around guest bugs). */ + TCGv_i32 tcg_el =3D tcg_const_i32(s->current_el); + gen_helper_rebuild_hflags_a64(cpu_env, tcg_el); + tcg_temp_free_i32(tcg_el); s->base.is_jmp =3D DISAS_UPDATE; } } diff --git a/target/arm/translate.c b/target/arm/translate.c index dac737f6ca..1cdb575ccd 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8563,6 +8563,8 @@ static int disas_coproc_insn(DisasContext *s, uint32_= t insn) ri =3D get_arm_cp_reginfo(s->cp_regs, ENCODE_CP_REG(cpnum, is64, s->ns, crn, crm, opc1, opc2)); if (ri) { + bool need_exit_tb; + /* Check access permissions */ if (!cp_access_ok(s->current_el, ri, isread)) { return 1; @@ -8735,15 +8737,23 @@ static int disas_coproc_insn(DisasContext *s, uint3= 2_t insn) } } =20 + need_exit_tb =3D false; if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_= IO)) { /* I/O operations must end the TB here (whether read or write)= */ gen_io_end(); - gen_lookup_tb(s); - } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { + need_exit_tb =3D true; + } + if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { /* We default to ending the TB on a coprocessor register write, * but allow this to be suppressed by the register definition * (usually only necessary to work around guest bugs). */ + TCGv_i32 tcg_el =3D tcg_const_i32(s->current_el); + gen_helper_rebuild_hflags_a32(cpu_env, tcg_el); + tcg_temp_free_i32(tcg_el); + need_exit_tb =3D true; + } + if (need_exit_tb) { gen_lookup_tb(s); } =20 --=20 2.17.1 From nobody Sun May 5 23:59:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1550619487420317.2617582506306; Tue, 19 Feb 2019 15:38:07 -0800 (PST) Received: from localhost ([127.0.0.1]:56606 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gwExg-0001Hb-Gg for importer@patchew.org; Tue, 19 Feb 2019 18:38:04 -0500 Received: from eggs.gnu.org ([209.51.188.92]:57490) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gwEuK-0007Xh-Bo for qemu-devel@nongnu.org; Tue, 19 Feb 2019 18:34:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gwEuJ-0001Wd-If for qemu-devel@nongnu.org; Tue, 19 Feb 2019 18:34:36 -0500 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:33000) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gwEuH-0001Rn-MF for qemu-devel@nongnu.org; Tue, 19 Feb 2019 18:34:35 -0500 Received: by mail-pg1-x542.google.com with SMTP id h11so8511917pgl.0 for ; Tue, 19 Feb 2019 15:34:28 -0800 (PST) Received: from localhost.localdomain (97-113-188-82.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v2 3/3] target/arm: Rely on hflags correct in cpu_get_tb_cpu_state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, cota@braap.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is the payoff. From perf record -g data of ubuntu 18 boot and shutdown: BEFORE: - 23.02% 2.82% qemu-system-aar [.] helper_lookup_tb_ptr - 20.22% helper_lookup_tb_ptr + 10.05% tb_htable_lookup - 9.13% cpu_get_tb_cpu_state 3.20% aa64_va_parameters_both 0.55% fp_exception_el - 11.66% 4.74% qemu-system-aar [.] cpu_get_tb_cpu_state - 6.96% cpu_get_tb_cpu_state 3.63% aa64_va_parameters_both 0.60% fp_exception_el 0.53% sve_exception_el AFTER: - 16.40% 3.40% qemu-system-aar [.] helper_lookup_tb_ptr - 13.03% helper_lookup_tb_ptr + 11.19% tb_htable_lookup 0.55% cpu_get_tb_cpu_state 0.98% 0.71% qemu-system-aar [.] cpu_get_tb_cpu_state 0.87% 0.24% qemu-system-aar [.] rebuild_hflags_a64 Before, helper_lookup_tb_ptr is the second hottest function in the application, consuming almost a quarter of the runtime. Within the entire execution, cpu_get_tb_cpu_state consumes about 12%. After, helper_lookup_tb_ptr has dropped to the fourth hottest function, with consumption dropping to a sixth of the runtime. Within the entire execution, cpu_get_tb_cpu_state has dropped below 1%, and the supporting function to rebuild hflags also consumes about 1%. Assertions are retained for --enable-debug-tcg. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Tested-by: Alex Benn=C3=A9e --- v2: Retain asserts for future debugging. --- target/arm/helper.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 909535a3e3..990a87876f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -14034,19 +14034,29 @@ void HELPER(rebuild_hflags_a64)(CPUARMState *env,= uint32_t el) void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { - int current_el =3D arm_current_el(env); - uint32_t flags; + uint32_t flags =3D env->hflags; uint32_t pstate_for_ss; =20 +#ifdef CONFIG_DEBUG_TCG + { + int el =3D arm_current_el(env); + uint32_t check_flags; + if (is_a64(env)) { + check_flags =3D rebuild_hflags_a64(env, el); + } else { + check_flags =3D rebuild_hflags_a32(env, el); + } + g_assert_cmphex(flags, =3D=3D, check_flags); + } +#endif + *cs_base =3D 0; - if (is_a64(env)) { + if (FIELD_EX32(flags, TBFLAG_ANY, AARCH64_STATE)) { *pc =3D env->pc; - flags =3D rebuild_hflags_a64(env, current_el); flags =3D FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); pstate_for_ss =3D env->pstate; } else { *pc =3D env->regs[15]; - flags =3D rebuild_hflags_a32(env, current_el); flags =3D FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); flags =3D FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bi= ts); pstate_for_ss =3D env->uncached_cpsr; --=20 2.17.1