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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id 20sm12530778pfs.182.2019.02.19.14.29.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Feb 2019 14:29:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cIgoi5ZJpcl3zdEbaiu1gS68e0aZGSDVr5lAbw6TYaY=; b=kccKPx75yp+bom/DITnf27fcqRp7W+VaVMufEjA8i5djFgftda002uuZf4NLNbQoZQ pyzgiJXvtkdoDC5HxqqGguV9eUIvdlYlqbAeukUVBEZt1SF/A6yyDA9ekq16VSAmmKnt Z5k42+tRave9EQdQ5tzxeNXYtzSNOntkwhyWIoDxbwd9Mf9QgnjFUQvg2J/xqeSjaWZb m15aBdZO98kwQegmVf9P7UPQikzNjc8rBSmVy50UV+3QaGA7os2s8AkKUXj4vVGx5Ka0 jKN5566xiTEo2soB0D/8S5KC5OBgHpP7Jj4OJLvqTDmwWopf6K7sLO5R22r1+27IQrxO dl9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cIgoi5ZJpcl3zdEbaiu1gS68e0aZGSDVr5lAbw6TYaY=; b=HSCmcyJi9BmUhiUjCtzkQNGYwwvNgu0kAfiiWWgR9XD2szwRjRD7+SYezl42OZiMsR gG9WhT2eiwZYTembBMNEStnjzARAxg5h4HMhnSdiuJwQLrFkPlv199un4gUHIG6AAgQG 2aVjzdykIdh7NaddL1mEoOAkhZsHsr7Rcf0xLSPxd+98sUiwnn80NosmS0LWlzFqNdIz FczHbYF9K92u/thrVbrYjF4ALYimhg96OYOWz8sm16ziDIEJjGCFLaCUh80BLRgA9ZRU NCgbKFfEhMUDrAj26f7ITDQJssF9nMUketOKc7t0awQJ2uesvf+kTGCHjtti0csacZEL wWsw== X-Gm-Message-State: AHQUAua1V7pWTQjVYs2h/L845PJoqgdYEiLwzJMNBkJsfK594tvtjeB7 e0phPVZLsKnVX2m/9KhEjJVd5A+c2i0= X-Google-Smtp-Source: AHgI3IZFvVPhwmwffuKjHTg11WaH7VPB40EF8Hizx7ATaE5hXHgHFx+saTVgl1QdlS3mI4UTqD2fqA== X-Received: by 2002:a17:902:bc3:: with SMTP id 61mr33496699plr.15.1550615396528; Tue, 19 Feb 2019 14:29:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 19 Feb 2019 14:29:48 -0800 Message-Id: <20190219222952.22183-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190219222952.22183-1-richard.henderson@linaro.org> References: <20190219222952.22183-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v5 1/5] target/arm: Add helpers for FMLAL X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Note that float16_to_float32 rightly squashes SNaN to QNaN. But of course pickNaNMulAdd, for ARM, selects SNaNs first. So we have to preserve SNaN long enough for the correct NaN to be selected. Thus float16_to_float32_by_bits. Signed-off-by: Richard Henderson --- target/arm/helper.h | 9 +++ target/arm/vec_helper.c | 148 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 157 insertions(+) diff --git a/target/arm/helper.h b/target/arm/helper.h index 747cb64d29..d363904278 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -677,6 +677,15 @@ DEF_HELPER_FLAGS_5(gvec_sqsub_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_sqsub_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_5(gvec_fmlal_a32, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_fmlal_a64, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a32, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a64, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + #ifdef TARGET_AARCH64 #include "helper-a64.h" #include "helper-sve.h" diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index dfc635cf9a..dedef62403 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -898,3 +898,151 @@ void HELPER(gvec_sqsub_d)(void *vd, void *vq, void *v= n, } clear_tail(d, oprsz, simd_maxsz(desc)); } + +/* + * Convert float16 to float32, raising no exceptions and + * preserving exceptional values, including SNaN. + * This is effectively an unpack+repack operation. + */ +static float32 float16_to_float32_by_bits(uint32_t f16, bool fz16) +{ + const int f16_bias =3D 15; + const int f32_bias =3D 127; + uint32_t sign =3D extract32(f16, 15, 1); + uint32_t exp =3D extract32(f16, 10, 5); + uint32_t frac =3D extract32(f16, 0, 10); + + if (exp =3D=3D 0x1f) { + /* Inf or NaN */ + exp =3D 0xff; + } else if (exp =3D=3D 0) { + /* Zero or denormal. */ + if (frac !=3D 0) { + if (fz16) { + frac =3D 0; + } else { + /* + * Denormal; these are all normal float32. + * Shift the fraction so that the msb is at bit 11, + * then remove bit 11 as the implicit bit of the + * normalized float32. Note that we still go through + * the shift for normal numbers below, to put the + * float32 fraction at the right place. + */ + int shift =3D clz32(frac) - 21; + frac =3D (frac << shift) & 0x3ff; + exp =3D f32_bias - f16_bias - shift + 1; + } + } + } else { + /* Normal number; adjust the bias. */ + exp +=3D f32_bias - f16_bias; + } + sign <<=3D 31; + exp <<=3D 23; + frac <<=3D 23 - 10; + + return sign | exp | frac; +} + +static uint64_t load4_f16(uint64_t *ptr, int is_q, int is_2) +{ + /* + * Branchless load of u32[0], u64[0], u32[1], or u64[1]. + * Load the 2nd qword iff is_q & is_2. + * Shift to the 2nd dword iff !is_q & is_2. + * For !is_q & !is_2, the upper bits of the result are garbage. + */ + return ptr[is_q & is_2] >> ((is_2 & ~is_q) << 5); +} + +/* + * Note that FMLAL requires oprsz =3D=3D 8 or oprsz =3D=3D 16, + * as there is not yet SVE versions that might use blocking. + */ + +static void do_fmlal(float32 *d, void *vn, void *vm, float_status *fpst, + uint32_t desc, bool fz16) +{ + intptr_t i, oprsz =3D simd_oprsz(desc); + int is_s =3D extract32(desc, SIMD_DATA_SHIFT, 1); + int is_2 =3D extract32(desc, SIMD_DATA_SHIFT + 1, 1); + int is_q =3D oprsz =3D=3D 16; + uint64_t n_4, m_4; + + /* Pre-load all of the f16 data, avoiding overlap issues. */ + n_4 =3D load4_f16(vn, is_q, is_2); + m_4 =3D load4_f16(vm, is_q, is_2); + + /* Negate all inputs for FMLSL at once. */ + if (is_s) { + n_4 ^=3D 0x8000800080008000ull; + } + + for (i =3D 0; i < oprsz / 4; i++) { + float32 n_1 =3D float16_to_float32_by_bits(n_4 >> (i * 16), fz16); + float32 m_1 =3D float16_to_float32_by_bits(m_4 >> (i * 16), fz16); + d[H4(i)] =3D float32_muladd(n_1, m_1, d[H4(i)], 0, fpst); + } + clear_tail(d, oprsz, simd_maxsz(desc)); +} + +void HELPER(gvec_fmlal_a32)(void *vd, void *vn, void *vm, + void *venv, uint32_t desc) +{ + CPUARMState *env =3D venv; + do_fmlal(vd, vn, vm, &env->vfp.standard_fp_status, desc, + get_flush_inputs_to_zero(&env->vfp.fp_status_f16)); +} + +void HELPER(gvec_fmlal_a64)(void *vd, void *vn, void *vm, + void *venv, uint32_t desc) +{ + CPUARMState *env =3D venv; + do_fmlal(vd, vn, vm, &env->vfp.fp_status, desc, + get_flush_inputs_to_zero(&env->vfp.fp_status_f16)); +} + +static void do_fmlal_idx(float32 *d, void *vn, void *vm, float_status *fps= t, + uint32_t desc, bool fz16) +{ + intptr_t i, oprsz =3D simd_oprsz(desc); + int is_s =3D extract32(desc, SIMD_DATA_SHIFT, 1); + int is_2 =3D extract32(desc, SIMD_DATA_SHIFT + 1, 1); + int index =3D extract32(desc, SIMD_DATA_SHIFT + 2, 3); + int is_q =3D oprsz =3D=3D 16; + uint64_t n_4; + float32 m_1; + + /* Pre-load all of the f16 data, avoiding overlap issues. */ + n_4 =3D load4_f16(vn, is_q, is_2); + + /* Negate all inputs for FMLSL at once. */ + if (is_s) { + n_4 ^=3D 0x8000800080008000ull; + } + + m_1 =3D float16_to_float32_by_bits(((float16 *)vm)[H2(index)], fz16); + + for (i =3D 0; i < oprsz / 4; i++) { + float32 n_1 =3D float16_to_float32_by_bits(n_4 >> (i * 16), fz16); + d[H4(i)] =3D float32_muladd(n_1, m_1, d[H4(i)], 0, fpst); + } + clear_tail(d, oprsz, simd_maxsz(desc)); +} + +void HELPER(gvec_fmlal_idx_a32)(void *vd, void *vn, void *vm, + void *venv, uint32_t desc) +{ + CPUARMState *env =3D venv; + do_fmlal_idx(vd, vn, vm, &env->vfp.standard_fp_status, desc, + get_flush_inputs_to_zero(&env->vfp.fp_status_f16)); +} + +void HELPER(gvec_fmlal_idx_a64)(void *vd, void *vn, void *vm, + void *venv, uint32_t desc) +{ + CPUARMState *env =3D venv; + do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status, desc, + get_flush_inputs_to_zero(&env->vfp.fp_status_f16)); +} --=20 2.17.2