From nobody Sat Feb 7 06:55:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1550581542102459.5665253808978; Tue, 19 Feb 2019 05:05:42 -0800 (PST) Received: from localhost ([127.0.0.1]:48004 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gw55a-0007Jp-KR for importer@patchew.org; Tue, 19 Feb 2019 08:05:34 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53328) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gw4yy-00024D-6F for qemu-devel@nongnu.org; Tue, 19 Feb 2019 07:58:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gw4yw-0002yq-Uc for qemu-devel@nongnu.org; Tue, 19 Feb 2019 07:58:43 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:41482) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gw4yp-0002rS-Dh for qemu-devel@nongnu.org; Tue, 19 Feb 2019 07:58:38 -0500 Received: by mail-wr1-x42b.google.com with SMTP id n2so9701400wrw.8 for ; Tue, 19 Feb 2019 04:58:21 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id e75sm5226113wmg.32.2019.02.19.04.58.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Feb 2019 04:58:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=h7p/j2bF8mRYbAEayArl2bX6oWoA1v9jlyX/daxOJvc=; b=PpNqtpeGj5dalW1H3GxIQJB9JGiU/qnLn4PA3sE1sNUmypvkQfbxLw4LRUOFBrHI5A BRImZNFFUk+3kUXO1LhH2iSFkBr3jwIyNVypFMJU5OM2Iuw9095sjRTUiMjxmOEBDBFO ZpB8EcQuqdQBACwumD2yXS4sSR9jBhZnw5EZq47dQMC9laORTtbhAKy+wQc8LHCXfU+J ptjOVqwcmROFYYA6hLty6nupnss92CNBemxw1P1zlnEdpOE2EuimwlybpaVOBLl3suwE L8onE1y3tnmNymXGic9+8FNFDW348q+/2998hjkLycXAP9JtRmpo3nMxD8kQ4Lk3ziMs 1lMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=h7p/j2bF8mRYbAEayArl2bX6oWoA1v9jlyX/daxOJvc=; b=YC1kA72ah6CUpZZHvqgNvv5UAF2igiLgQ7W3MjJ4QwFEWmHouG5QdjIakelHOGA4L4 ISn5ZdBluGOTD/eSek7/M38zKlU54mkA7x+d9bkF6N7giBzoJX37aVRlMoyGOa7J+aI1 c2QUEBGXtJerLR/U0j6mJ1Fndjb5pN9IS3Ar4E4RwUxUUDk9P1EFrimLqpta7jc5g+OR arGFZ73R1XWbqsqE20Dte8x0ylIUB80xTICtj/lbVd9AbHmNcFpHRZfxFSEpIHiS2FXF PRegwJSujlcsxwi6SIJqwMQkdJVmYfCMXsC4MAZSDXISuLXerAZf2ZhMkMtw4Najk1mC tA2A== X-Gm-Message-State: AHQUAuZzPkAU3S9HtKQHevmfZJfdnJlMcdCfCh+LNV4m9lrz0RCrNrAN NmNWsKkRnGqW4Q7tgJYwFXfhHroiBxpQYQ== X-Google-Smtp-Source: AHgI3IaCxkq9FiyT6YwNGynv/gb04ItksS4MYAB9baGciuz6nwHQOiwbBNch0Fu0xYEcFrZOd20N2g== X-Received: by 2002:a5d:4841:: with SMTP id n1mr19444389wrs.85.1550581100559; Tue, 19 Feb 2019 04:58:20 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 19 Feb 2019 12:58:07 +0000 Message-Id: <20190219125808.25174-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190219125808.25174-1-peter.maydell@linaro.org> References: <20190219125808.25174-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42b Subject: [Qemu-devel] [PATCH 7/8] hw/arm/iotkit-sysctl: Implement CPUWAIT and INITSVTOR* X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The CPUWAIT register acts as a sort of power-control: if a bit in it is 1 then the CPU will have been forced into waiting when the system was reset (which in QEMU we model as the CPU starting powered off). Writing a 0 to the register will allow the CPU to boot (for QEMU, we model this as powering it on). Note that writing 0 to the register does not power off a CPU. For this to work correctly we need to also honour the INITSVTOR* registers, which let the guest control where the CPU will load its SP and PC from when it comes out of reset. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/misc/iotkit-sysctl.c | 41 +++++++++++++++++++++++++++++++++++++---- 1 file changed, 37 insertions(+), 4 deletions(-) diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c index 05606017fc2..e333c8169a3 100644 --- a/hw/misc/iotkit-sysctl.c +++ b/hw/misc/iotkit-sysctl.c @@ -25,6 +25,8 @@ #include "hw/sysbus.h" #include "hw/registerfields.h" #include "hw/misc/iotkit-sysctl.h" +#include "target/arm/arm-powerctl.h" +#include "target/arm/cpu.h" =20 REG32(SECDBGSTAT, 0x0) REG32(SECDBGSET, 0x4) @@ -69,6 +71,21 @@ static const int sysctl_id[] =3D { 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ }; =20 +/* + * Set the initial secure vector table offset address for the core. + * This will take effect when the CPU next resets. + */ +static void set_init_vtor(uint64_t cpuid, uint32_t vtor) +{ + Object *cpuobj =3D OBJECT(arm_get_cpu_by_id(cpuid)); + + if (cpuobj) { + if (object_property_find(cpuobj, "init-svtor", NULL)) { + object_property_set_uint(cpuobj, vtor, "init-svtor", &error_ab= ort); + } + } +} + static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset, unsigned size) { @@ -229,11 +246,18 @@ static void iotkit_sysctl_write(void *opaque, hwaddr = offset, s->gretreg =3D value; break; case A_INITSVTOR0: - qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVTOR0 unimplemented\n= "); s->initsvtor0 =3D value; + set_init_vtor(0, s->initsvtor0); break; case A_CPUWAIT: - qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CPUWAIT unimplemented\n"); + if ((s->cpuwait & 1) && !(value & 1)) { + /* Powering up CPU 0 */ + arm_set_cpu_on_and_reset(0); + } + if ((s->cpuwait & 2) && !(value & 2)) { + /* Powering up CPU 1 */ + arm_set_cpu_on_and_reset(1); + } s->cpuwait =3D value; break; case A_WICCTRL: @@ -287,8 +311,8 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, if (!s->is_sse200) { goto bad_offset; } - qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVTOR1 unimplemented\n= "); s->initsvtor1 =3D value; + set_init_vtor(1, s->initsvtor1); break; case A_EWCTRL: if (!s->is_sse200) { @@ -382,7 +406,16 @@ static void iotkit_sysctl_reset(DeviceState *dev) s->gretreg =3D 0; s->initsvtor0 =3D 0x10000000; s->initsvtor1 =3D 0x10000000; - s->cpuwait =3D 0; + if (s->is_sse200) { + /* + * CPU 0 starts on, CPU 1 starts off. In real hardware this is + * configurable by the SoC integrator as a verilog parameter. + */ + s->cpuwait =3D 2; + } else { + /* CPU 0 starts on */ + s->cpuwait =3D 0; + } s->wicctrl =3D 0; s->scsecctrl =3D 0; s->fclk_div =3D 0; --=20 2.20.1