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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id e75sm5226113wmg.32.2019.02.19.04.58.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Feb 2019 04:58:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CskMvrDB6k+X6606gwOi32bS+lwdD+6mC4UiTntWILM=; b=TDXoa5Mk+X1ggmu0Exz8Bf9dMBYY60wSaEKxvzObfmU4Z7YhOHRrRK33LYcec8W2Bn 7vPiuyfiJF3H5hcV3aHgd3AGxxrNcgdxbya9c7maIBNEh3mn3ftGXCacsVQb4/YOkAVr 2Rl03hEf3jsv6t5trKxoDElMgoK6hmtWOy6XtpxW8I4CllQ1YH/bDJR+RM1xR9gvgjq0 NdpB4tAYgczPKERq98EAXC5rd4RP6MMWSazLtPZUtdYNgILmRUY5txlxCzlYMw1RSFk3 ItfdIA+APTxFgTMzrmBmlZRDOUUzKsJ8bBA7XA4TrGHcPb+d+PDKZu0fxJXguWSh0yw6 k1vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CskMvrDB6k+X6606gwOi32bS+lwdD+6mC4UiTntWILM=; b=NewUZ9Jp6GPZaghN+MhduSlhRsMGhP5BHHk8Jo+SQnnQc34/L2By+UM5XqkrYVV66c DTPkhubcCG4VqojryY5LTV6zpY32LwoPZCJk/0A2v02b2A8HhwkkaAN53Nlv2eWxdu86 uH9WF9F+aE8E2S0hWp2cjMLWqrMPwnWYRGkew+9HyGlEux70YolstAexp7H6KIT+olx8 DtP9E20jpDdmdBPYvyDSsHa2xa1ZZ7CDycE3IwX4Y97J7t1Na6l/oYv7GDq2E7L4h3/X BwYCI0JXh47dB1SYRoaYk4C2IXLJDR8R+nslBjhEu+LBF2uZiBcgyZPo3EG4xdHJgxzW heyw== X-Gm-Message-State: AHQUAuZnFQ7g0OilQ3NCL9Yibf4KdTirfe7Xqnv4EZQLmt+3TjLaU3Sj C5xu4wTWSWSn0YLCveTP/cprDg== X-Google-Smtp-Source: AHgI3Ia1mFrucc9qmVbsGh3x4osw1oyDaS4ocA82/SamxWZ8cShFOU7+piO5gp9UQtbW18y/1Jn4SQ== X-Received: by 2002:adf:ec8f:: with SMTP id z15mr20066773wrn.290.1550581099459; Tue, 19 Feb 2019 04:58:19 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 19 Feb 2019 12:58:06 +0000 Message-Id: <20190219125808.25174-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190219125808.25174-1-peter.maydell@linaro.org> References: <20190219125808.25174-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH 6/8] hw/arm/iotkit-sysctl: Add SSE-200 registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The SYSCTL block in the SSE-200 has some extra registers that are not present in the IoTKit version. Add these registers (as reads-as-written stubs), enabled by a new QOM property. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/misc/iotkit-sysctl.h | 20 +++ hw/arm/armsse.c | 2 + hw/misc/iotkit-sysctl.c | 245 +++++++++++++++++++++++++++++++- 3 files changed, 262 insertions(+), 5 deletions(-) diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysct= l.h index 17a145517a4..9c2f23ecd28 100644 --- a/include/hw/misc/iotkit-sysctl.h +++ b/include/hw/misc/iotkit-sysctl.h @@ -17,6 +17,9 @@ * "system control register" blocks. * * QEMU interface: + * + QOM property "SYS_VERSION": value of the SYS_VERSION register of the + * system information block of the SSE + * (used to identify whether to provide SSE-200-only registers) * + sysbus MMIO region 0: the system information register bank * + sysbus MMIO region 1: the system control register bank */ @@ -44,6 +47,23 @@ typedef struct IoTKitSysCtl { uint32_t initsvtor0; uint32_t cpuwait; uint32_t wicctrl; + uint32_t scsecctrl; + uint32_t fclk_div; + uint32_t sysclk_div; + uint32_t clock_force; + uint32_t initsvtor1; + uint32_t nmi_enable; + uint32_t ewctrl; + uint32_t pdcm_pd_sys_sense; + uint32_t pdcm_pd_sram0_sense; + uint32_t pdcm_pd_sram1_sense; + uint32_t pdcm_pd_sram2_sense; + uint32_t pdcm_pd_sram3_sense; + + /* Properties */ + uint32_t sys_version; + + bool is_sse200; } IoTKitSysCtl; =20 #endif diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 5768d6fbf8b..7c946564ebc 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -997,6 +997,8 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) /* System information registers */ sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysinfo), 0, 0x40020000); /* System control registers */ + object_property_set_int(OBJECT(&s->sysctl), info->sys_version, + "SYS_VERSION", &err); object_property_set_bool(OBJECT(&s->sysctl), true, "realized", &err); if (err) { error_propagate(errp, err); diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c index 8c85aea9309..05606017fc2 100644 --- a/hw/misc/iotkit-sysctl.c +++ b/hw/misc/iotkit-sysctl.c @@ -17,6 +17,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/bitops.h" #include "qemu/log.h" #include "trace.h" #include "qapi/error.h" @@ -28,15 +29,26 @@ REG32(SECDBGSTAT, 0x0) REG32(SECDBGSET, 0x4) REG32(SECDBGCLR, 0x8) +REG32(SCSECCTRL, 0xc) +REG32(FCLK_DIV, 0x10) +REG32(SYSCLK_DIV, 0x14) +REG32(CLOCK_FORCE, 0x18) REG32(RESET_SYNDROME, 0x100) REG32(RESET_MASK, 0x104) REG32(SWRESET, 0x108) FIELD(SWRESET, SWRESETREQ, 9, 1) REG32(GRETREG, 0x10c) REG32(INITSVTOR0, 0x110) +REG32(INITSVTOR1, 0x114) REG32(CPUWAIT, 0x118) -REG32(BUSWAIT, 0x11c) +REG32(NMI_ENABLE, 0x11c) /* BUSWAIT in IoTKit */ REG32(WICCTRL, 0x120) +REG32(EWCTRL, 0x124) +REG32(PDCM_PD_SYS_SENSE, 0x200) +REG32(PDCM_PD_SRAM0_SENSE, 0x20c) +REG32(PDCM_PD_SRAM1_SENSE, 0x210) +REG32(PDCM_PD_SRAM2_SENSE, 0x214) +REG32(PDCM_PD_SRAM3_SENSE, 0x218) REG32(PID4, 0xfd0) REG32(PID5, 0xfd4) REG32(PID6, 0xfd8) @@ -67,6 +79,30 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr = offset, case A_SECDBGSTAT: r =3D s->secure_debug; break; + case A_SCSECCTRL: + if (!s->is_sse200) { + goto bad_offset; + } + r =3D s->scsecctrl; + break; + case A_FCLK_DIV: + if (!s->is_sse200) { + goto bad_offset; + } + r =3D s->fclk_div; + break; + case A_SYSCLK_DIV: + if (!s->is_sse200) { + goto bad_offset; + } + r =3D s->sysclk_div; + break; + case A_CLOCK_FORCE: + if (!s->is_sse200) { + goto bad_offset; + } + r =3D s->clock_force; + break; case A_RESET_SYNDROME: r =3D s->reset_syndrome; break; @@ -79,16 +115,62 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwadd= r offset, case A_INITSVTOR0: r =3D s->initsvtor0; break; + case A_INITSVTOR1: + if (!s->is_sse200) { + goto bad_offset; + } + r =3D s->initsvtor1; + break; case A_CPUWAIT: r =3D s->cpuwait; break; - case A_BUSWAIT: - /* In IoTKit BUSWAIT is reserved, R/O, zero */ - r =3D 0; + case A_NMI_ENABLE: + /* In IoTKit this is named BUSWAIT but is marked reserved, R/O, ze= ro */ + if (!s->is_sse200) { + r =3D 0; + break; + } + r =3D s->nmi_enable; break; case A_WICCTRL: r =3D s->wicctrl; break; + case A_EWCTRL: + if (!s->is_sse200) { + goto bad_offset; + } + r =3D s->ewctrl; + break; + case A_PDCM_PD_SYS_SENSE: + if (!s->is_sse200) { + goto bad_offset; + } + r =3D s->pdcm_pd_sys_sense; + break; + case A_PDCM_PD_SRAM0_SENSE: + if (!s->is_sse200) { + goto bad_offset; + } + r =3D s->pdcm_pd_sram0_sense; + break; + case A_PDCM_PD_SRAM1_SENSE: + if (!s->is_sse200) { + goto bad_offset; + } + r =3D s->pdcm_pd_sram1_sense; + break; + case A_PDCM_PD_SRAM2_SENSE: + if (!s->is_sse200) { + goto bad_offset; + } + r =3D s->pdcm_pd_sram2_sense; + break; + case A_PDCM_PD_SRAM3_SENSE: + if (!s->is_sse200) { + goto bad_offset; + } + r =3D s->pdcm_pd_sram3_sense; + break; case A_PID4 ... A_CID3: r =3D sysctl_id[(offset - A_PID4) / 4]; break; @@ -101,6 +183,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, r =3D 0; break; default: + bad_offset: qemu_log_mask(LOG_GUEST_ERROR, "IoTKit SysCtl read: bad offset %x\n", (int)offset); r =3D 0; @@ -172,14 +255,105 @@ static void iotkit_sysctl_write(void *opaque, hwaddr= offset, qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); } break; - case A_BUSWAIT: /* In IoTKit BUSWAIT is reserved, R/O, zero */ + case A_SCSECCTRL: + if (!s->is_sse200) { + goto bad_offset; + } + qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SCSECCTRL unimplemented\n"= ); + s->scsecctrl =3D value; + break; + case A_FCLK_DIV: + if (!s->is_sse200) { + goto bad_offset; + } + qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl FCLK_DIV unimplemented\n"); + s->fclk_div =3D value; + break; + case A_SYSCLK_DIV: + if (!s->is_sse200) { + goto bad_offset; + } + qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SYSCLK_DIV unimplemented\n= "); + s->sysclk_div =3D value; + break; + case A_CLOCK_FORCE: + if (!s->is_sse200) { + goto bad_offset; + } + qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CLOCK_FORCE unimplemented\= n"); + s->clock_force =3D value; + break; + case A_INITSVTOR1: + if (!s->is_sse200) { + goto bad_offset; + } + qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVTOR1 unimplemented\n= "); + s->initsvtor1 =3D value; + break; + case A_EWCTRL: + if (!s->is_sse200) { + goto bad_offset; + } + qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl EWCTRL unimplemented\n"); + s->ewctrl =3D value; + break; + case A_PDCM_PD_SYS_SENSE: + if (!s->is_sse200) { + goto bad_offset; + } + qemu_log_mask(LOG_UNIMP, + "IoTKit SysCtl PDCM_PD_SYS_SENSE unimplemented\n"); + s->pdcm_pd_sys_sense =3D value; + break; + case A_PDCM_PD_SRAM0_SENSE: + if (!s->is_sse200) { + goto bad_offset; + } + qemu_log_mask(LOG_UNIMP, + "IoTKit SysCtl PDCM_PD_SRAM0_SENSE unimplemented\n"); + s->pdcm_pd_sram0_sense =3D value; + break; + case A_PDCM_PD_SRAM1_SENSE: + if (!s->is_sse200) { + goto bad_offset; + } + qemu_log_mask(LOG_UNIMP, + "IoTKit SysCtl PDCM_PD_SRAM1_SENSE unimplemented\n"); + s->pdcm_pd_sram1_sense =3D value; + break; + case A_PDCM_PD_SRAM2_SENSE: + if (!s->is_sse200) { + goto bad_offset; + } + qemu_log_mask(LOG_UNIMP, + "IoTKit SysCtl PDCM_PD_SRAM2_SENSE unimplemented\n"); + s->pdcm_pd_sram2_sense =3D value; + break; + case A_PDCM_PD_SRAM3_SENSE: + if (!s->is_sse200) { + goto bad_offset; + } + qemu_log_mask(LOG_UNIMP, + "IoTKit SysCtl PDCM_PD_SRAM3_SENSE unimplemented\n"); + s->pdcm_pd_sram3_sense =3D value; + break; + case A_NMI_ENABLE: + /* In IoTKit this is BUSWAIT: reserved, R/O, zero */ + if (!s->is_sse200) { + goto ro_offset; + } + qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl NMI_ENABLE unimplemented\n= "); + s->nmi_enable =3D value; + break; case A_SECDBGSTAT: case A_PID4 ... A_CID3: + ro_offset: qemu_log_mask(LOG_GUEST_ERROR, "IoTKit SysCtl write: write of RO offset %x\n", (int)offset); break; default: + bad_offset: qemu_log_mask(LOG_GUEST_ERROR, "IoTKit SysCtl write: bad offset %x\n", (int)offset); break; @@ -207,8 +381,20 @@ static void iotkit_sysctl_reset(DeviceState *dev) s->reset_mask =3D 0; s->gretreg =3D 0; s->initsvtor0 =3D 0x10000000; + s->initsvtor1 =3D 0x10000000; s->cpuwait =3D 0; s->wicctrl =3D 0; + s->scsecctrl =3D 0; + s->fclk_div =3D 0; + s->sysclk_div =3D 0; + s->clock_force =3D 0; + s->nmi_enable =3D 0; + s->ewctrl =3D 0; + s->pdcm_pd_sys_sense =3D 0x7f; + s->pdcm_pd_sram0_sense =3D 0; + s->pdcm_pd_sram1_sense =3D 0; + s->pdcm_pd_sram2_sense =3D 0; + s->pdcm_pd_sram3_sense =3D 0; } =20 static void iotkit_sysctl_init(Object *obj) @@ -221,6 +407,44 @@ static void iotkit_sysctl_init(Object *obj) sysbus_init_mmio(sbd, &s->iomem); } =20 +static void iotkit_sysctl_realize(DeviceState *dev, Error **errp) +{ + IoTKitSysCtl *s =3D IOTKIT_SYSCTL(dev); + + /* The top 4 bits of the SYS_VERSION register tell us if we're an SSE-= 200 */ + if (extract32(s->sys_version, 28, 4) =3D=3D 2) { + s->is_sse200 =3D true; + } +} + +static bool sse200_needed(void *opaque) +{ + IoTKitSysCtl *s =3D IOTKIT_SYSCTL(opaque); + + return s->is_sse200; +} + +static const VMStateDescription iotkit_sysctl_sse200_vmstate =3D { + .name =3D "iotkit-sysctl/sse-200", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D sse200_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(scsecctrl, IoTKitSysCtl), + VMSTATE_UINT32(fclk_div, IoTKitSysCtl), + VMSTATE_UINT32(sysclk_div, IoTKitSysCtl), + VMSTATE_UINT32(clock_force, IoTKitSysCtl), + VMSTATE_UINT32(initsvtor1, IoTKitSysCtl), + VMSTATE_UINT32(nmi_enable, IoTKitSysCtl), + VMSTATE_UINT32(pdcm_pd_sys_sense, IoTKitSysCtl), + VMSTATE_UINT32(pdcm_pd_sram0_sense, IoTKitSysCtl), + VMSTATE_UINT32(pdcm_pd_sram1_sense, IoTKitSysCtl), + VMSTATE_UINT32(pdcm_pd_sram2_sense, IoTKitSysCtl), + VMSTATE_UINT32(pdcm_pd_sram3_sense, IoTKitSysCtl), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription iotkit_sysctl_vmstate =3D { .name =3D "iotkit-sysctl", .version_id =3D 1, @@ -234,15 +458,26 @@ static const VMStateDescription iotkit_sysctl_vmstate= =3D { VMSTATE_UINT32(cpuwait, IoTKitSysCtl), VMSTATE_UINT32(wicctrl, IoTKitSysCtl), VMSTATE_END_OF_LIST() + }, + .subsections =3D (const VMStateDescription*[]) { + &iotkit_sysctl_sse200_vmstate, + NULL } }; =20 +static Property iotkit_sysctl_props[] =3D { + DEFINE_PROP_UINT32("SYS_VERSION", IoTKitSysCtl, sys_version, 0), + DEFINE_PROP_END_OF_LIST() +}; + static void iotkit_sysctl_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->vmsd =3D &iotkit_sysctl_vmstate; dc->reset =3D iotkit_sysctl_reset; + dc->props =3D iotkit_sysctl_props; + dc->realize =3D iotkit_sysctl_realize; } =20 static const TypeInfo iotkit_sysctl_info =3D { --=20 2.20.1