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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id e75sm5226113wmg.32.2019.02.19.04.58.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Feb 2019 04:58:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yXhjNBRfk4bgBthdgKq2jkIg12QhrODqy/sEJjyPMGI=; b=Y3BDzJJ+PbAW8IfpHbGIAdSi/a28nybW5Mqyrqom8pwlh/+DJGgnSBDdHd83Q1NbvE XEDrtbSx+m3mSmU8jM+Dt6OgDcJCD0z29/+7UWutfCi82HiXogtJVKLDsjhiwKWM1bwK 3sa7JEFp6jv7uSfnpsQYIkqsWK3obbhNEWtn4BFDnYvY4hunvnH0AKewcvCEnWPiCpLu B583iYokjOv0tVPKZmYqGMGW+qSrJ2C5zFiTz8SYrUWyDnlxn45UEja1BAus9O6/X2y4 WWTNJ7khUR3dVj/khvsHIVKWUV2SSd41M4Uq97flSI9ShUtfn7UdguKxh5v5D91iSidl 8NfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yXhjNBRfk4bgBthdgKq2jkIg12QhrODqy/sEJjyPMGI=; b=L+Ks5tdpsHXAH6r4p3/+28rpGFLC2c2UaR8oNNhQ0ig2fMK3KVAsKXatqY3D6jeQaZ rSt3w87vGYbh6SslaRbqYnUAtVpF+CD+zCk/rTnrBmGmd+Gq2xWVHba97+C4dTLS1VgT Yw05N+FBPEEiFzuc9rkA0KUVVFcfDmAu5N6Rwqjn0cHPObzOIvyPGalMOJP3RCQxL49r KCYUtLGW4D/zRhrBMtU+f9Ie5ke3Jf9nVeqpgNHzBGZBq3cn8GaDxt2U8YOfxrezDiSl ahWBQTCwvOZCqDDcsUW1xI52U9YwwU0toY9A5uKKwjfWYc+yWjNwRl2VJHYhYP/4i0Pn BGDw== X-Gm-Message-State: AHQUAubFt1jtX5fSPHp4cB7snSZ+TJg5OU2hYREpAofeLPlVGVzrowO7 aqbqNj4VrCLPguEmae9N0+FHGA== X-Google-Smtp-Source: AHgI3IY4o761reJR0VBS7xw9+7xROGA3gHginVnT1RnCEkb/ZcZklT6uc/Z2PMB50YPSJUKuaJ4ndA== X-Received: by 2002:a5d:500c:: with SMTP id e12mr7667572wrt.27.1550581096927; Tue, 19 Feb 2019 04:58:16 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 19 Feb 2019 12:58:04 +0000 Message-Id: <20190219125808.25174-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190219125808.25174-1-peter.maydell@linaro.org> References: <20190219125808.25174-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH 4/8] target/arm/arm-powerctl: Add new arm_set_cpu_on_and_reset() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Currently the Arm arm-powerctl.h APIs allow: * arm_set_cpu_on(), which powers on a CPU and sets its initial PC and other startup state * arm_reset_cpu(), which resets a CPU which is already on (and fails if the CPU is powered off) but there is no way to say "power on a CPU as if it had just come out of reset and don't do anything else to it". Add a new function arm_set_cpu_on_and_reset(), which does this. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/arm-powerctl.h | 16 +++++++++++ target/arm/arm-powerctl.c | 56 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 72 insertions(+) diff --git a/target/arm/arm-powerctl.h b/target/arm/arm-powerctl.h index 04353923c06..37c8a04f0a9 100644 --- a/target/arm/arm-powerctl.h +++ b/target/arm/arm-powerctl.h @@ -74,4 +74,20 @@ int arm_set_cpu_off(uint64_t cpuid); */ int arm_reset_cpu(uint64_t cpuid); =20 +/* + * arm_set_cpu_on_and_reset: + * @cpuid: the id of the CPU we want to star + * + * Start the cpu designated by @cpuid and put it through its normal + * CPU reset process. The CPU will start in the way it is architected + * to start after a power-on reset. + * + * Returns: QEMU_ARM_POWERCTL_RET_SUCCESS on success. + * QEMU_ARM_POWERCTL_INVALID_PARAM if there is no CPU with that ID. + * QEMU_ARM_POWERCTL_ALREADY_ON if the CPU is already on. + * QEMU_ARM_POWERCTL_ON_PENDING if the CPU is already partway through + * powering on. + */ +int arm_set_cpu_on_and_reset(uint64_t cpuid); + #endif diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c index f9de5164e55..f77a950db67 100644 --- a/target/arm/arm-powerctl.c +++ b/target/arm/arm-powerctl.c @@ -228,6 +228,62 @@ int arm_set_cpu_on(uint64_t cpuid, uint64_t entry, uin= t64_t context_id, return QEMU_ARM_POWERCTL_RET_SUCCESS; } =20 +static void arm_set_cpu_on_and_reset_async_work(CPUState *target_cpu_state, + run_on_cpu_data data) +{ + ARMCPU *target_cpu =3D ARM_CPU(target_cpu_state); + + /* Initialize the cpu we are turning on */ + cpu_reset(target_cpu_state); + target_cpu_state->halted =3D 0; + + /* Finally set the power status */ + assert(qemu_mutex_iothread_locked()); + target_cpu->power_state =3D PSCI_ON; +} + +int arm_set_cpu_on_and_reset(uint64_t cpuid) +{ + CPUState *target_cpu_state; + ARMCPU *target_cpu; + + assert(qemu_mutex_iothread_locked()); + + /* Retrieve the cpu we are powering up */ + target_cpu_state =3D arm_get_cpu_by_id(cpuid); + if (!target_cpu_state) { + /* The cpu was not found */ + return QEMU_ARM_POWERCTL_INVALID_PARAM; + } + + target_cpu =3D ARM_CPU(target_cpu_state); + if (target_cpu->power_state =3D=3D PSCI_ON) { + qemu_log_mask(LOG_GUEST_ERROR, + "[ARM]%s: CPU %" PRId64 " is already on\n", + __func__, cpuid); + return QEMU_ARM_POWERCTL_ALREADY_ON; + } + + /* + * If another CPU has powered the target on we are in the state + * ON_PENDING and additional attempts to power on the CPU should + * fail (see 6.6 Implementation CPU_ON/CPU_OFF races in the PSCI + * spec) + */ + if (target_cpu->power_state =3D=3D PSCI_ON_PENDING) { + qemu_log_mask(LOG_GUEST_ERROR, + "[ARM]%s: CPU %" PRId64 " is already powering on\n", + __func__, cpuid); + return QEMU_ARM_POWERCTL_ON_PENDING; + } + + async_run_on_cpu(target_cpu_state, arm_set_cpu_on_and_reset_async_work, + RUN_ON_CPU_NULL); + + /* We are good to go */ + return QEMU_ARM_POWERCTL_RET_SUCCESS; +} + static void arm_set_cpu_off_async_work(CPUState *target_cpu_state, run_on_cpu_data data) { --=20 2.20.1