From nobody Fri May 3 12:59:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1550581208419345.1784067553874; Tue, 19 Feb 2019 05:00:08 -0800 (PST) Received: from localhost ([127.0.0.1]:47721 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gw50F-0002xE-GJ for importer@patchew.org; Tue, 19 Feb 2019 08:00:03 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53137) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gw4yW-0001fV-7y for qemu-devel@nongnu.org; Tue, 19 Feb 2019 07:58:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gw4yU-0002n1-Mx for qemu-devel@nongnu.org; Tue, 19 Feb 2019 07:58:16 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:39247) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gw4yU-0002mS-D3 for qemu-devel@nongnu.org; Tue, 19 Feb 2019 07:58:14 -0500 Received: by mail-wr1-x444.google.com with SMTP id l5so20769199wrw.6 for ; Tue, 19 Feb 2019 04:58:14 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id e75sm5226113wmg.32.2019.02.19.04.58.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Feb 2019 04:58:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=B8tKueiUEpLkUPEUz3rtGmcp4sKBv8bSzBMqRMa4eyM=; b=tPDMN7kEyXR9l3GuCrxdO6QgVhxP6HxYjS6sbo4xlcuH4C9iryBqsBzzhUsX5vTeWO TDVxYYO0YZjEf15Of+vil/Wae5PDgJmEgnHIpGvlpqxLrvnYFazapGlgpfeQfadW9Kml BjhjnNpWwNUqp/eqnX2PS8OeGWz2Oz+z11ZJ/KBO+oAx7xffwJcli6YgJ9sgUYYZdsjL UqBaauUqIl/OpdsMC+QAwvTXA44O/nw4Jvou6ftEp4mb3pa09mXE0PpPJNFd+53Hwk2Q GWW0V+GO9h93YB4pGmQNkKoIso0C8owSJ1IjwHzt6EgrX66yc3CdtUEAfvaEolJ3+sXy JZNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=B8tKueiUEpLkUPEUz3rtGmcp4sKBv8bSzBMqRMa4eyM=; b=jhKuhX/ZNlorFIIc3c1MDtbguADlrcvMHv/dwq5ejVHTka2fJ3jQyscECXhGXcRYSe pP3GBTD7ne6cmjWmfVefevU1+RxjNJkmYdR8Z+ehBca4Dx6+Vbzqezu0SPTNdxqhODSd QbJYq6tzPrwfCKLZfHYs7YIpZYwUnsYmyeefaz1U2NQll9khrkdmhzq1Yyl8rvixfIKQ 7y3Z1gdMaKOLaAApH+67kSxvIUg5REGa0deCtdIJpqHlhH2um+hZpZc/0px2lOnsAl63 npZQbdaq/kkXYw8+VTuB6ffZTc2+I3QH+2W0tkyKNct1hmFEg2FiEVHcM+wAQfOGCza7 LonA== X-Gm-Message-State: AHQUAubT0c2ljk4RqYVE2VC+MVmwdmrifBshMmDVMmFH9lDcZ1BWim8M T3GgHh/uyZ90bLUYL7QAC0V7hg== X-Google-Smtp-Source: AHgI3IZlUJ7b7kqpP94GS+R+w/qJGEWPjnEWhUYMJ3YwUvuH2CGzLsZMx6FkLLaOnx2PeMuaZ5WY9w== X-Received: by 2002:a5d:464b:: with SMTP id j11mr19889798wrs.307.1550581093205; Tue, 19 Feb 2019 04:58:13 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 19 Feb 2019 12:58:01 +0000 Message-Id: <20190219125808.25174-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190219125808.25174-1-peter.maydell@linaro.org> References: <20190219125808.25174-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH 1/8] hw/misc/armsse-mhu.c: Model the SSE-200 Message Handling Unit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Implement a model of the Message Handling Unit (MHU) found in the Arm SSE-200. This is a simple device which just contains some registers which allow the two cores of the SSE-200 to raise interrupts on each other. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/misc/Makefile.objs | 1 + include/hw/misc/armsse-mhu.h | 44 +++++++ hw/misc/armsse-mhu.c | 198 ++++++++++++++++++++++++++++++++ MAINTAINERS | 2 + default-configs/arm-softmmu.mak | 1 + hw/misc/trace-events | 4 + 6 files changed, 250 insertions(+) create mode 100644 include/hw/misc/armsse-mhu.h create mode 100644 hw/misc/armsse-mhu.c diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index 74c91d250c8..c71e07ae35d 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -70,6 +70,7 @@ obj-$(CONFIG_IOTKIT_SECCTL) +=3D iotkit-secctl.o obj-$(CONFIG_IOTKIT_SYSCTL) +=3D iotkit-sysctl.o obj-$(CONFIG_IOTKIT_SYSINFO) +=3D iotkit-sysinfo.o obj-$(CONFIG_ARMSSE_CPUID) +=3D armsse-cpuid.o +obj-$(CONFIG_ARMSSE_MHU) +=3D armsse-mhu.o =20 obj-$(CONFIG_PVPANIC) +=3D pvpanic.o obj-$(CONFIG_AUX) +=3D auxbus.o diff --git a/include/hw/misc/armsse-mhu.h b/include/hw/misc/armsse-mhu.h new file mode 100644 index 00000000000..e57eafc2521 --- /dev/null +++ b/include/hw/misc/armsse-mhu.h @@ -0,0 +1,44 @@ +/* + * ARM SSE-200 Message Handling Unit (MHU) + * + * Copyright (c) 2019 Linaro Limited + * Written by Peter Maydell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +/* + * This is a model of the Message Handling Unit (MHU) which is part of the + * Arm SSE-200 and documented in + * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/core= link_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_0= 0_en.pdf + * + * QEMU interface: + * + sysbus MMIO region 0: the system information register bank + * + sysbus IRQ 0: interrupt for CPU 0 + * + sysbus IRQ 1: interrupt for CPU 1 + */ + +#ifndef HW_MISC_SSE_MHU_H +#define HW_MISC_SSE_MHU_H + +#include "hw/sysbus.h" + +#define TYPE_ARMSSE_MHU "armsse-mhu" +#define ARMSSE_MHU(obj) OBJECT_CHECK(ARMSSEMHU, (obj), TYPE_ARMSSE_MHU) + +typedef struct ARMSSEMHU { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion iomem; + qemu_irq cpu0irq; + qemu_irq cpu1irq; + + uint32_t cpu0intr; + uint32_t cpu1intr; +} ARMSSEMHU; + +#endif diff --git a/hw/misc/armsse-mhu.c b/hw/misc/armsse-mhu.c new file mode 100644 index 00000000000..9ebca32e9aa --- /dev/null +++ b/hw/misc/armsse-mhu.c @@ -0,0 +1,198 @@ +/* + * ARM SSE-200 Message Handling Unit (MHU) + * + * Copyright (c) 2019 Linaro Limited + * Written by Peter Maydell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +/* + * This is a model of the Message Handling Unit (MHU) which is part of the + * Arm SSE-200 and documented in + * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/core= link_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_0= 0_en.pdf + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "trace.h" +#include "qapi/error.h" +#include "sysemu/sysemu.h" +#include "hw/sysbus.h" +#include "hw/registerfields.h" +#include "hw/misc/armsse-mhu.h" + +REG32(CPU0INTR_STAT, 0x0) +REG32(CPU0INTR_SET, 0x4) +REG32(CPU0INTR_CLR, 0x8) +REG32(CPU1INTR_STAT, 0x10) +REG32(CPU1INTR_SET, 0x14) +REG32(CPU1INTR_CLR, 0x18) +REG32(PID4, 0xfd0) +REG32(PID5, 0xfd4) +REG32(PID6, 0xfd8) +REG32(PID7, 0xfdc) +REG32(PID0, 0xfe0) +REG32(PID1, 0xfe4) +REG32(PID2, 0xfe8) +REG32(PID3, 0xfec) +REG32(CID0, 0xff0) +REG32(CID1, 0xff4) +REG32(CID2, 0xff8) +REG32(CID3, 0xffc) + +/* Valid bits in the interrupt registers. If any are set the IRQ is raised= */ +#define INTR_MASK 0xf + +/* PID/CID values */ +static const int armsse_mhu_id[] =3D { + 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */ + 0x56, 0xb8, 0x0b, 0x00, /* PID0..PID3 */ + 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ +}; + +static void armsse_mhu_update(ARMSSEMHU *s) +{ + qemu_set_irq(s->cpu0irq, s->cpu0intr !=3D 0); + qemu_set_irq(s->cpu1irq, s->cpu1intr !=3D 0); +} + +static uint64_t armsse_mhu_read(void *opaque, hwaddr offset, unsigned size) +{ + ARMSSEMHU *s =3D ARMSSE_MHU(opaque); + uint64_t r; + + switch (offset) { + case A_CPU0INTR_STAT: + r =3D s->cpu0intr; + break; + + case A_CPU1INTR_STAT: + r =3D s->cpu1intr; + break; + + case A_PID4 ... A_CID3: + r =3D armsse_mhu_id[(offset - A_PID4) / 4]; + break; + + case A_CPU0INTR_SET: + case A_CPU0INTR_CLR: + case A_CPU1INTR_SET: + case A_CPU1INTR_CLR: + qemu_log_mask(LOG_GUEST_ERROR, + "SSE MHU: read of write-only register at offset 0x%x= \n", + (int)offset); + r =3D 0; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "SSE MHU read: bad offset 0x%x\n", (int)offset); + r =3D 0; + break; + } + trace_armsse_mhu_read(offset, r, size); + return r; +} + +static void armsse_mhu_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + ARMSSEMHU *s =3D ARMSSE_MHU(opaque); + + trace_armsse_mhu_write(offset, value, size); + + switch (offset) { + case A_CPU0INTR_SET: + s->cpu0intr |=3D (value & INTR_MASK); + break; + case A_CPU0INTR_CLR: + s->cpu0intr &=3D ~(value & INTR_MASK); + break; + case A_CPU1INTR_SET: + s->cpu1intr |=3D (value & INTR_MASK); + break; + case A_CPU1INTR_CLR: + s->cpu1intr &=3D ~(value & INTR_MASK); + break; + + case A_CPU0INTR_STAT: + case A_CPU1INTR_STAT: + case A_PID4 ... A_CID3: + qemu_log_mask(LOG_GUEST_ERROR, + "SSE MHU: write to read-only register at offset 0x%x= \n", + (int)offset); + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "SSE MHU write: bad offset 0x%x\n", (int)offset); + break; + } + + armsse_mhu_update(s); +} + +static const MemoryRegionOps armsse_mhu_ops =3D { + .read =3D armsse_mhu_read, + .write =3D armsse_mhu_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, +}; + +static void armsse_mhu_reset(DeviceState *dev) +{ + ARMSSEMHU *s =3D ARMSSE_MHU(dev); + + s->cpu0intr =3D 0; + s->cpu1intr =3D 0; +} + +static const VMStateDescription armsse_mhu_vmstate =3D { + .name =3D "armsse-mhu", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(cpu0intr, ARMSSEMHU), + VMSTATE_UINT32(cpu1intr, ARMSSEMHU), + VMSTATE_END_OF_LIST() + }, +}; + +static void armsse_mhu_init(Object *obj) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + ARMSSEMHU *s =3D ARMSSE_MHU(obj); + + memory_region_init_io(&s->iomem, obj, &armsse_mhu_ops, + s, "armsse-mhu", 0x1000); + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(sbd, &s->cpu0irq); + sysbus_init_irq(sbd, &s->cpu1irq); +} + +static void armsse_mhu_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->reset =3D armsse_mhu_reset; + dc->vmsd =3D &armsse_mhu_vmstate; +} + +static const TypeInfo armsse_mhu_info =3D { + .name =3D TYPE_ARMSSE_MHU, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(ARMSSEMHU), + .instance_init =3D armsse_mhu_init, + .class_init =3D armsse_mhu_class_init, +}; + +static void armsse_mhu_register_types(void) +{ + type_register_static(&armsse_mhu_info); +} + +type_init(armsse_mhu_register_types); diff --git a/MAINTAINERS b/MAINTAINERS index 770b2eaaf91..f198d510e89 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -633,6 +633,8 @@ F: hw/misc/iotkit-sysinfo.c F: include/hw/misc/iotkit-sysinfo.h F: hw/misc/armsse-cpuid.c F: include/hw/misc/armsse-cpuid.h +F: hw/misc/armsse-mhu.c +F: include/hw/misc/armsse-mhu.h =20 Musca M: Peter Maydell diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.= mak index 87ad2674946..bd6943b691a 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -119,6 +119,7 @@ CONFIG_IOTKIT_SECCTL=3Dy CONFIG_IOTKIT_SYSCTL=3Dy CONFIG_IOTKIT_SYSINFO=3Dy CONFIG_ARMSSE_CPUID=3Dy +CONFIG_ARMSSE_MHU=3Dy =20 CONFIG_VERSATILE=3Dy CONFIG_VERSATILE_PCI=3Dy diff --git a/hw/misc/trace-events b/hw/misc/trace-events index b0701bddd3c..c1795bb54b8 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -136,3 +136,7 @@ iotkit_sysctl_reset(void) "IoTKit SysCtl: reset" # hw/misc/armsse-cpuid.c armsse_cpuid_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 = CPU_IDENTITY read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" armsse_cpuid_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200= CPU_IDENTITY write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" + +# hw/misc/armsse-mhu.c +armsse_mhu_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MH= U read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" +armsse_mhu_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 M= HU write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" --=20 2.20.1 From nobody Fri May 3 12:59:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id e75sm5226113wmg.32.2019.02.19.04.58.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Feb 2019 04:58:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=z9u5w0T0Lwyuy9HIkprGJsanlIZ38qvna0IXR0Nck2w=; b=mSakjBRXHRlXXmvnr6vFCvEDHDQr0i2028unf3LImD0wKHCFwL1pVKYRvSd4vvlC+h Bkblz/7IFGAdBuc6RmehQJYoDEznKnMB5Q7Ifc8Q8np/gawvkw1zg3IXm7gOJJaK89c2 qlCuI2i8xzELfpSLFKEPy+WbQctIQh/NyhBF6jnQNjLqUD0WaAbYkacJRmIfavORqHHq Ld1uKORUb0oXOTAgNzP2zCiGZleclK7rBM8t08zuhsGz1jVRuTFblydUq2vqxhyrbdyj 7LtWMw8QKvZ2F0cbcRex/aIf4MexqBr2+TXWzfpXFCU5+YzSRz85djrwC2MHkh12jB4s Z4hQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=z9u5w0T0Lwyuy9HIkprGJsanlIZ38qvna0IXR0Nck2w=; b=p3geWA3GJ7xos3zceog6430aBTw0X0WvX1yE4LAvYDoSn6AxTisCkpux2E5kjlL24e rXGINo5i6U2y5VGBF6Y2m/azVx4dzcvCjx4CSt/wG8WIEJYjVn0he4fXX8O7Yc+hObVG +Ec84JIkfT4AT4Jy+L4g27KVhVyXsP50UgmID01jCalUiDJGVg9j7h9RidkErS0uSKfI 297YC3aUvzAjGdGP8nWHReIoHuaZR3wgugTk51dnbOX8EPxF6k20VIO/OP3N4sqMHYYN eivZwgQhxOqETm/JLkUtVQJlr7z1uqRLTbJFqAoWVR7wNnWYiPNbXhDKwjicfMzaw7jt qxeg== X-Gm-Message-State: AHQUAubkJ43hRh/f/8Ks4GcAMcqvSUJHY7XZiCOG4lpwC47XygA+/uWN cUe1+LL0+vJlKfzmMSoVrHrU3Y2CyHiEIQ== X-Google-Smtp-Source: AHgI3IbImsZWtvWXEHH2zlApWUOfadVlMx7ON2VE4B/L5I14hmY/OSD4TRf30VIYWih9oGnM2reMjA== X-Received: by 2002:adf:9123:: with SMTP id j32mr21805495wrj.122.1550581094393; Tue, 19 Feb 2019 04:58:14 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 19 Feb 2019 12:58:02 +0000 Message-Id: <20190219125808.25174-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190219125808.25174-1-peter.maydell@linaro.org> References: <20190219125808.25174-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH 2/8] hw/arm/armsse: Wire up the MHUs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Create and connect the MHUs in the SSE-200. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/arm/armsse.h | 3 ++- hw/arm/armsse.c | 40 ++++++++++++++++++++++++++++++---------- 2 files changed, 32 insertions(+), 11 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 7ef871c7dfe..81e082cccf8 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -95,6 +95,7 @@ #include "hw/misc/iotkit-sysctl.h" #include "hw/misc/iotkit-sysinfo.h" #include "hw/misc/armsse-cpuid.h" +#include "hw/misc/armsse-mhu.h" #include "hw/misc/unimp.h" #include "hw/or-irq.h" #include "hw/core/split-irq.h" @@ -166,7 +167,7 @@ typedef struct ARMSSE { IoTKitSysCtl sysctl; IoTKitSysCtl sysinfo; =20 - UnimplementedDeviceState mhu[2]; + ARMSSEMHU mhu[2]; UnimplementedDeviceState ppu[NUM_PPUS]; UnimplementedDeviceState cachectrl[SSE_MAX_CPUS]; UnimplementedDeviceState cpusecctrl[SSE_MAX_CPUS]; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 129e7ea7fe0..5768d6fbf8b 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -282,9 +282,9 @@ static void armsse_init(Object *obj) sizeof(s->sysinfo), TYPE_IOTKIT_SYSINFO); if (info->has_mhus) { sysbus_init_child_obj(obj, "mhu0", &s->mhu[0], sizeof(s->mhu[0]), - TYPE_UNIMPLEMENTED_DEVICE); + TYPE_ARMSSE_MHU); sysbus_init_child_obj(obj, "mhu1", &s->mhu[1], sizeof(s->mhu[1]), - TYPE_UNIMPLEMENTED_DEVICE); + TYPE_ARMSSE_MHU); } if (info->has_ppus) { for (i =3D 0; i < info->num_cpus; i++) { @@ -766,22 +766,28 @@ static void armsse_realize(DeviceState *dev, Error **= errp) } =20 if (info->has_mhus) { - for (i =3D 0; i < ARRAY_SIZE(s->mhu); i++) { - char *name; - char *port; + /* + * An SSE-200 with only one CPU should have only one MHU created, + * with the region where the second MHU usually is being RAZ/WI. + * We don't implement that SSE-200 config; if we want to support + * it then this code needs to be enhanced to handle creating the + * RAZ/WI region instead of the second MHU. + */ + assert(info->num_cpus > 1); + + for (i =3D 0; i < ARRAY_SIZE(s->mhu); i++) { + char *port; + int cpunum; + SysBusDevice *mhu_sbd =3D SYS_BUS_DEVICE(&s->mhu[i]); =20 - name =3D g_strdup_printf("MHU%d", i); - qdev_prop_set_string(DEVICE(&s->mhu[i]), "name", name); - qdev_prop_set_uint64(DEVICE(&s->mhu[i]), "size", 0x1000); object_property_set_bool(OBJECT(&s->mhu[i]), true, "realized", &err); - g_free(name); if (err) { error_propagate(errp, err); return; } port =3D g_strdup_printf("port[%d]", i + 3); - mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mhu[i]), 0); + mr =3D sysbus_mmio_get_region(mhu_sbd, 0); object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), port, &err); g_free(port); @@ -789,6 +795,20 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) error_propagate(errp, err); return; } + + /* + * Each MHU has an irq line for each CPU: + * MHU 0 irq line 0 -> CPU 0 IRQ 6 + * MHU 0 irq line 1 -> CPU 1 IRQ 6 + * MHU 1 irq line 0 -> CPU 0 IRQ 7 + * MHU 1 irq line 1 -> CPU 1 IRQ 7 + */ + for (cpunum =3D 0; cpunum < info->num_cpus; cpunum++) { + DeviceState *cpudev =3D DEVICE(&s->armv7m[cpunum]); + + sysbus_connect_irq(mhu_sbd, cpunum, + qdev_get_gpio_in(cpudev, 6 + i)); + } } } =20 --=20 2.20.1 From nobody Fri May 3 12:59:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15505812203351010.9725948383598; Tue, 19 Feb 2019 05:00:20 -0800 (PST) Received: from localhost ([127.0.0.1]:47723 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gw50R-00038L-71 for importer@patchew.org; Tue, 19 Feb 2019 08:00:15 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53189) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gw4yX-0001gL-Vc for qemu-devel@nongnu.org; Tue, 19 Feb 2019 07:58:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gw4yW-0002od-US for qemu-devel@nongnu.org; Tue, 19 Feb 2019 07:58:17 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:36255) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gw4yW-0002nz-N9 for qemu-devel@nongnu.org; Tue, 19 Feb 2019 07:58:16 -0500 Received: by mail-wr1-x441.google.com with SMTP id o17so21882740wrw.3 for ; Tue, 19 Feb 2019 04:58:16 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id e75sm5226113wmg.32.2019.02.19.04.58.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Feb 2019 04:58:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+7hrcQXswMt8u3DqhSZ2esGYAUAMYuaF4oZO23FfjSM=; b=DS2amq8jdXrXtWOfFJggiEtrJGMsH+G+jKafRTkoiKJa5++2mlLssdWEPHJPg8ZyI9 LPldjrg0jzeMRwI+2tI8USr2S+E0OpG3WGVkgpNFH4akv9o+UpwlPsJOF3lWVxTVoEsw UnYU+y1oB3IJ0xqwKE1E5vrs3iUTY/sdZbdCc03/mswhRvijSurICFU5olmHAtVZGLyk t+PTCWdXF/5zw1NE9uDFKVILmZv0uL1HJD9VvYolWrrni0xDPnXuBYLJIhC4XWxamUzW WyUflwwPpEdDs1ymbHk6qeXLfFMX6mK57S28Q5ipNZJB1pJxd3880CENLi0/vR+FsJ/x TC1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+7hrcQXswMt8u3DqhSZ2esGYAUAMYuaF4oZO23FfjSM=; b=nCRdlxm7PXRZe0DeWaffdF90TTfWJt/0vq7fmO70uQrG53vzMmNMTQnemC46d1OE5A +oW7CHJ1j0VBrImTYR4uILy1CWswgNE0MuyeU4g5KAwkRcB+LdVa4qp5NEy7/qEwatmY 5ufmxJmirr5kGI5xQBQ7gooy7A6ap3EHLdQ4KorrFjerNb9nTx8tepb4rLEK+G1gITt6 g+EnTqS/ZGNWoArysTWi23Noh2fT9Mf/4BAjJsfOG/hMmU2jMYE8CuwkxtXWkpfiZb+R 6/zhm3rHwvMwoBi7E7k/V2fShW/JEXFYt2Ou/CbN41cEVHRkjIv5mmVML72NuDIZ+yIY 1jPQ== X-Gm-Message-State: AHQUAuZoiQ9jVnrWGvySXVU2+sOjpVUNlWVQ5pIORZd+bwShl18orUUh fSqnHxA6dPar/ArVvzwoLPSieg== X-Google-Smtp-Source: AHgI3IZQSI0aNtzhbWttA2ULGJxG1Xru+g8kE6xqvY7yEQnK9IXMXBCcLqzZFlNh6269T/wyaRbF3g== X-Received: by 2002:a5d:51cd:: with SMTP id n13mr19934551wrv.310.1550581095787; Tue, 19 Feb 2019 04:58:15 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 19 Feb 2019 12:58:03 +0000 Message-Id: <20190219125808.25174-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190219125808.25174-1-peter.maydell@linaro.org> References: <20190219125808.25174-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH 3/8] target/arm/cpu: Allow init-svtor property to be set after realize X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Make the M-profile "init-svtor" property be settable after realize. This matches the hardware, where this is a config signal which is sampled on CPU reset and can thus be changed between one reset and another. To do this we have to change the API we use to add the property. (We will need this capability for the SSE-200.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.c | 29 ++++++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index edf6e0e1f1c..a418ac5cc32 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -22,6 +22,7 @@ #include "target/arm/idau.h" #include "qemu/error-report.h" #include "qapi/error.h" +#include "qapi/visitor.h" #include "cpu.h" #include "internals.h" #include "qemu-common.h" @@ -771,9 +772,21 @@ static Property arm_cpu_pmsav7_dregion_property =3D pmsav7_dregion, qdev_prop_uint32, uint32_t); =20 -/* M profile: initial value of the Secure VTOR */ -static Property arm_cpu_initsvtor_property =3D - DEFINE_PROP_UINT32("init-svtor", ARMCPU, init_svtor, 0); +static void arm_get_init_svtor(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + visit_type_uint32(v, name, &cpu->init_svtor, errp); +} + +static void arm_set_init_svtor(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + visit_type_uint32(v, name, &cpu->init_svtor, errp); +} =20 void arm_cpu_post_init(Object *obj) { @@ -845,8 +858,14 @@ void arm_cpu_post_init(Object *obj) qdev_prop_allow_set_link_before_realize, OBJ_PROP_LINK_STRONG, &error_abort); - qdev_property_add_static(DEVICE(obj), &arm_cpu_initsvtor_property, - &error_abort); + /* + * M profile: initial value of the Secure VTOR. We can't just use + * a simple DEFINE_PROP_UINT32 for this because we want to permit + * the property to be set after realize. + */ + object_property_add(obj, "init-svtor", "uint32", + arm_get_init_svtor, arm_set_init_svtor, + NULL, NULL, &error_abort); } =20 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, --=20 2.20.1 From nobody Fri May 3 12:59:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1550581595338727.3116532319244; Tue, 19 Feb 2019 05:06:35 -0800 (PST) Received: from localhost ([127.0.0.1]:48040 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gw56X-0008AR-EH for importer@patchew.org; Tue, 19 Feb 2019 08:06:33 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53216) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gw4yZ-0001hd-9n for qemu-devel@nongnu.org; Tue, 19 Feb 2019 07:58:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gw4yY-0002pm-6C for qemu-devel@nongnu.org; Tue, 19 Feb 2019 07:58:19 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:38250) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gw4yX-0002pB-Tl for qemu-devel@nongnu.org; Tue, 19 Feb 2019 07:58:18 -0500 Received: by mail-wr1-x444.google.com with SMTP id v13so21841278wrw.5 for ; Tue, 19 Feb 2019 04:58:17 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id e75sm5226113wmg.32.2019.02.19.04.58.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Feb 2019 04:58:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yXhjNBRfk4bgBthdgKq2jkIg12QhrODqy/sEJjyPMGI=; b=Y3BDzJJ+PbAW8IfpHbGIAdSi/a28nybW5Mqyrqom8pwlh/+DJGgnSBDdHd83Q1NbvE XEDrtbSx+m3mSmU8jM+Dt6OgDcJCD0z29/+7UWutfCi82HiXogtJVKLDsjhiwKWM1bwK 3sa7JEFp6jv7uSfnpsQYIkqsWK3obbhNEWtn4BFDnYvY4hunvnH0AKewcvCEnWPiCpLu B583iYokjOv0tVPKZmYqGMGW+qSrJ2C5zFiTz8SYrUWyDnlxn45UEja1BAus9O6/X2y4 WWTNJ7khUR3dVj/khvsHIVKWUV2SSd41M4Uq97flSI9ShUtfn7UdguKxh5v5D91iSidl 8NfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yXhjNBRfk4bgBthdgKq2jkIg12QhrODqy/sEJjyPMGI=; b=L+Ks5tdpsHXAH6r4p3/+28rpGFLC2c2UaR8oNNhQ0ig2fMK3KVAsKXatqY3D6jeQaZ rSt3w87vGYbh6SslaRbqYnUAtVpF+CD+zCk/rTnrBmGmd+Gq2xWVHba97+C4dTLS1VgT Yw05N+FBPEEiFzuc9rkA0KUVVFcfDmAu5N6Rwqjn0cHPObzOIvyPGalMOJP3RCQxL49r KCYUtLGW4D/zRhrBMtU+f9Ie5ke3Jf9nVeqpgNHzBGZBq3cn8GaDxt2U8YOfxrezDiSl ahWBQTCwvOZCqDDcsUW1xI52U9YwwU0toY9A5uKKwjfWYc+yWjNwRl2VJHYhYP/4i0Pn BGDw== X-Gm-Message-State: AHQUAubFt1jtX5fSPHp4cB7snSZ+TJg5OU2hYREpAofeLPlVGVzrowO7 aqbqNj4VrCLPguEmae9N0+FHGA== X-Google-Smtp-Source: AHgI3IY4o761reJR0VBS7xw9+7xROGA3gHginVnT1RnCEkb/ZcZklT6uc/Z2PMB50YPSJUKuaJ4ndA== X-Received: by 2002:a5d:500c:: with SMTP id e12mr7667572wrt.27.1550581096927; Tue, 19 Feb 2019 04:58:16 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 19 Feb 2019 12:58:04 +0000 Message-Id: <20190219125808.25174-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190219125808.25174-1-peter.maydell@linaro.org> References: <20190219125808.25174-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH 4/8] target/arm/arm-powerctl: Add new arm_set_cpu_on_and_reset() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Currently the Arm arm-powerctl.h APIs allow: * arm_set_cpu_on(), which powers on a CPU and sets its initial PC and other startup state * arm_reset_cpu(), which resets a CPU which is already on (and fails if the CPU is powered off) but there is no way to say "power on a CPU as if it had just come out of reset and don't do anything else to it". Add a new function arm_set_cpu_on_and_reset(), which does this. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/arm-powerctl.h | 16 +++++++++++ target/arm/arm-powerctl.c | 56 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 72 insertions(+) diff --git a/target/arm/arm-powerctl.h b/target/arm/arm-powerctl.h index 04353923c06..37c8a04f0a9 100644 --- a/target/arm/arm-powerctl.h +++ b/target/arm/arm-powerctl.h @@ -74,4 +74,20 @@ int arm_set_cpu_off(uint64_t cpuid); */ int arm_reset_cpu(uint64_t cpuid); =20 +/* + * arm_set_cpu_on_and_reset: + * @cpuid: the id of the CPU we want to star + * + * Start the cpu designated by @cpuid and put it through its normal + * CPU reset process. The CPU will start in the way it is architected + * to start after a power-on reset. + * + * Returns: QEMU_ARM_POWERCTL_RET_SUCCESS on success. + * QEMU_ARM_POWERCTL_INVALID_PARAM if there is no CPU with that ID. + * QEMU_ARM_POWERCTL_ALREADY_ON if the CPU is already on. + * QEMU_ARM_POWERCTL_ON_PENDING if the CPU is already partway through + * powering on. + */ +int arm_set_cpu_on_and_reset(uint64_t cpuid); + #endif diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c index f9de5164e55..f77a950db67 100644 --- a/target/arm/arm-powerctl.c +++ b/target/arm/arm-powerctl.c @@ -228,6 +228,62 @@ int arm_set_cpu_on(uint64_t cpuid, uint64_t entry, uin= t64_t context_id, return QEMU_ARM_POWERCTL_RET_SUCCESS; } =20 +static void arm_set_cpu_on_and_reset_async_work(CPUState *target_cpu_state, + run_on_cpu_data data) +{ + ARMCPU *target_cpu =3D ARM_CPU(target_cpu_state); + + /* Initialize the cpu we are turning on */ + cpu_reset(target_cpu_state); + target_cpu_state->halted =3D 0; + + /* Finally set the power status */ + assert(qemu_mutex_iothread_locked()); + target_cpu->power_state =3D PSCI_ON; +} + +int arm_set_cpu_on_and_reset(uint64_t cpuid) +{ + CPUState *target_cpu_state; + ARMCPU *target_cpu; + + assert(qemu_mutex_iothread_locked()); + + /* Retrieve the cpu we are powering up */ + target_cpu_state =3D arm_get_cpu_by_id(cpuid); + if (!target_cpu_state) { + /* The cpu was not found */ + return QEMU_ARM_POWERCTL_INVALID_PARAM; + } + + target_cpu =3D ARM_CPU(target_cpu_state); + if (target_cpu->power_state =3D=3D PSCI_ON) { + qemu_log_mask(LOG_GUEST_ERROR, + "[ARM]%s: CPU %" PRId64 " is already on\n", + __func__, cpuid); + return QEMU_ARM_POWERCTL_ALREADY_ON; + } + + /* + * If another CPU has powered the target on we are in the state + * ON_PENDING and additional attempts to power on the CPU should + * fail (see 6.6 Implementation CPU_ON/CPU_OFF races in the PSCI + * spec) + */ + if (target_cpu->power_state =3D=3D PSCI_ON_PENDING) { + qemu_log_mask(LOG_GUEST_ERROR, + "[ARM]%s: CPU %" PRId64 " is already powering on\n", + __func__, cpuid); + return QEMU_ARM_POWERCTL_ON_PENDING; + } + + async_run_on_cpu(target_cpu_state, arm_set_cpu_on_and_reset_async_work, + RUN_ON_CPU_NULL); + + /* We are good to go */ + return QEMU_ARM_POWERCTL_RET_SUCCESS; +} + static void arm_set_cpu_off_async_work(CPUState *target_cpu_state, run_on_cpu_data data) { --=20 2.20.1 From nobody Fri May 3 12:59:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1550581807120291.2840242711346; Tue, 19 Feb 2019 05:10:07 -0800 (PST) Received: from localhost ([127.0.0.1]:48169 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gw59v-000271-Pv for importer@patchew.org; Tue, 19 Feb 2019 08:10:03 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53241) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gw4yd-0001m5-U2 for qemu-devel@nongnu.org; Tue, 19 Feb 2019 07:58:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gw4yZ-0002ql-FF for qemu-devel@nongnu.org; Tue, 19 Feb 2019 07:58:21 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:33549) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gw4yZ-0002pz-3m for qemu-devel@nongnu.org; Tue, 19 Feb 2019 07:58:19 -0500 Received: by mail-wr1-x441.google.com with SMTP id i12so21930184wrw.0 for ; Tue, 19 Feb 2019 04:58:19 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id e75sm5226113wmg.32.2019.02.19.04.58.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Feb 2019 04:58:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iZHCSzTkSeN8DcccRbnTD25aOJeO0Zlug61irY5xm5Y=; b=R18UcBLuW+SuT147FoUqm0L6wVhtjS5flqth3PgBXWX71RzO2HfFcU9YZtz23ilpTz 8+ABH8FakWmLIK9LjjMjmNAdhk/0X7sNwc7GYI59MY5ZkMtSg0SGU8UbN5n2zC3gS5S3 mhO6lqVHcUAMAJH2WN6LPQcbirAQV6SE0j47LalDutNH4W8gwEHnwyrlML3eoKPOLar4 8v/Oys2yB2hcrehj8At+5+z2FuTigJ7zIUnB1RBXtoFfgQh9dkqatvQLQR7mMisBi2t4 xF73pO+TKT/WYFw2kVkTOktkMESZvrH6yn62WahEeUNXu8VH39okjC4j5ssQL4flnU0B osEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iZHCSzTkSeN8DcccRbnTD25aOJeO0Zlug61irY5xm5Y=; b=tiEWpy5pddhnPFrVleHawBCKDzFKQFb0II/f6NSwgMvJhy6FI6Qg9oeu3SE4EpJ8TY 8O0bKJRJT9w33HPXRiXzTd8ZzJOKQc2nrCw5TUc1w5mnH1H6LnFebFnJWqZVEACnGiy9 dKTbbbMNt8Q/c+/XOrkNmJ8ZR8p0J8uf5jzPry2LYadCgHJj/wYl55b/VRu1ZZ0QL96o eQFYZDQHD23OSQuUWH79JdHNKWfAN4Sj/Yl37bLv3ZO/PgygwZbe0ND3iusn7W5VCL6L Dz4LkA1PDpbg18w0f/1lyp2o1+hF898+MjHkaR1hbMxFOjowehf7vJ4+yjReXvfiIqCw Eb6A== X-Gm-Message-State: AHQUAuZAGDfjbbr6rk1W1iiBsFuzpTWFxo0J4fMxwMPW3EZBFCv6VtAe kErcw/dw9lMg7piJwoaw+oatN150yhOh/Q== X-Google-Smtp-Source: AHgI3IZtFQRGknsJw2Dcnq853lCRfUtddAl15rTO3Pk7Bw4t2LJDk/c9fV9cLdrgVk5mQRgjeZhTXg== X-Received: by 2002:adf:e487:: with SMTP id i7mr14322375wrm.202.1550581098128; Tue, 19 Feb 2019 04:58:18 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 19 Feb 2019 12:58:05 +0000 Message-Id: <20190219125808.25174-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190219125808.25174-1-peter.maydell@linaro.org> References: <20190219125808.25174-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH 5/8] hw/misc/iotkit-sysctl: Correct typo in INITSVTOR0 register name X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The iotkit-sysctl device has a register it names INITSVRTOR0. This is actually a typo present in the IoTKit documentation and also in part of the SSE-200 documentation: it should be INITSVTOR0 because it is specifying the initial value of the Secure VTOR register in the CPU. Correct the typo. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/misc/iotkit-sysctl.h | 2 +- hw/misc/iotkit-sysctl.c | 16 ++++++++-------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysct= l.h index e36613cb5ee..17a145517a4 100644 --- a/include/hw/misc/iotkit-sysctl.h +++ b/include/hw/misc/iotkit-sysctl.h @@ -41,7 +41,7 @@ typedef struct IoTKitSysCtl { uint32_t reset_syndrome; uint32_t reset_mask; uint32_t gretreg; - uint32_t initsvrtor0; + uint32_t initsvtor0; uint32_t cpuwait; uint32_t wicctrl; } IoTKitSysCtl; diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c index a21d8bd6789..8c85aea9309 100644 --- a/hw/misc/iotkit-sysctl.c +++ b/hw/misc/iotkit-sysctl.c @@ -33,7 +33,7 @@ REG32(RESET_MASK, 0x104) REG32(SWRESET, 0x108) FIELD(SWRESET, SWRESETREQ, 9, 1) REG32(GRETREG, 0x10c) -REG32(INITSVRTOR0, 0x110) +REG32(INITSVTOR0, 0x110) REG32(CPUWAIT, 0x118) REG32(BUSWAIT, 0x11c) REG32(WICCTRL, 0x120) @@ -76,8 +76,8 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr o= ffset, case A_GRETREG: r =3D s->gretreg; break; - case A_INITSVRTOR0: - r =3D s->initsvrtor0; + case A_INITSVTOR0: + r =3D s->initsvtor0; break; case A_CPUWAIT: r =3D s->cpuwait; @@ -145,9 +145,9 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, */ s->gretreg =3D value; break; - case A_INITSVRTOR0: - qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVRTOR0 unimplemented\= n"); - s->initsvrtor0 =3D value; + case A_INITSVTOR0: + qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVTOR0 unimplemented\n= "); + s->initsvtor0 =3D value; break; case A_CPUWAIT: qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CPUWAIT unimplemented\n"); @@ -206,7 +206,7 @@ static void iotkit_sysctl_reset(DeviceState *dev) s->reset_syndrome =3D 1; s->reset_mask =3D 0; s->gretreg =3D 0; - s->initsvrtor0 =3D 0x10000000; + s->initsvtor0 =3D 0x10000000; s->cpuwait =3D 0; s->wicctrl =3D 0; } @@ -230,7 +230,7 @@ static const VMStateDescription iotkit_sysctl_vmstate = =3D { VMSTATE_UINT32(reset_syndrome, IoTKitSysCtl), VMSTATE_UINT32(reset_mask, IoTKitSysCtl), VMSTATE_UINT32(gretreg, IoTKitSysCtl), - VMSTATE_UINT32(initsvrtor0, IoTKitSysCtl), + VMSTATE_UINT32(initsvtor0, IoTKitSysCtl), VMSTATE_UINT32(cpuwait, IoTKitSysCtl), VMSTATE_UINT32(wicctrl, IoTKitSysCtl), VMSTATE_END_OF_LIST() --=20 2.20.1 From nobody Fri May 3 12:59:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1550581985421276.0726591852149; Tue, 19 Feb 2019 05:13:05 -0800 (PST) Received: from localhost ([127.0.0.1]:48243 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gw5Co-0004hF-9i for importer@patchew.org; Tue, 19 Feb 2019 08:13:02 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53277) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gw4yn-0001ui-I1 for qemu-devel@nongnu.org; Tue, 19 Feb 2019 07:58:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gw4yj-0002uR-Si for qemu-devel@nongnu.org; Tue, 19 Feb 2019 07:58:32 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:36256) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gw4yd-0002r3-UF for qemu-devel@nongnu.org; Tue, 19 Feb 2019 07:58:27 -0500 Received: by mail-wr1-x442.google.com with SMTP id o17so21882967wrw.3 for ; Tue, 19 Feb 2019 04:58:20 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id e75sm5226113wmg.32.2019.02.19.04.58.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Feb 2019 04:58:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CskMvrDB6k+X6606gwOi32bS+lwdD+6mC4UiTntWILM=; b=TDXoa5Mk+X1ggmu0Exz8Bf9dMBYY60wSaEKxvzObfmU4Z7YhOHRrRK33LYcec8W2Bn 7vPiuyfiJF3H5hcV3aHgd3AGxxrNcgdxbya9c7maIBNEh3mn3ftGXCacsVQb4/YOkAVr 2Rl03hEf3jsv6t5trKxoDElMgoK6hmtWOy6XtpxW8I4CllQ1YH/bDJR+RM1xR9gvgjq0 NdpB4tAYgczPKERq98EAXC5rd4RP6MMWSazLtPZUtdYNgILmRUY5txlxCzlYMw1RSFk3 ItfdIA+APTxFgTMzrmBmlZRDOUUzKsJ8bBA7XA4TrGHcPb+d+PDKZu0fxJXguWSh0yw6 k1vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CskMvrDB6k+X6606gwOi32bS+lwdD+6mC4UiTntWILM=; b=NewUZ9Jp6GPZaghN+MhduSlhRsMGhP5BHHk8Jo+SQnnQc34/L2By+UM5XqkrYVV66c DTPkhubcCG4VqojryY5LTV6zpY32LwoPZCJk/0A2v02b2A8HhwkkaAN53Nlv2eWxdu86 uH9WF9F+aE8E2S0hWp2cjMLWqrMPwnWYRGkew+9HyGlEux70YolstAexp7H6KIT+olx8 DtP9E20jpDdmdBPYvyDSsHa2xa1ZZ7CDycE3IwX4Y97J7t1Na6l/oYv7GDq2E7L4h3/X BwYCI0JXh47dB1SYRoaYk4C2IXLJDR8R+nslBjhEu+LBF2uZiBcgyZPo3EG4xdHJgxzW heyw== X-Gm-Message-State: AHQUAuZnFQ7g0OilQ3NCL9Yibf4KdTirfe7Xqnv4EZQLmt+3TjLaU3Sj C5xu4wTWSWSn0YLCveTP/cprDg== X-Google-Smtp-Source: AHgI3Ia1mFrucc9qmVbsGh3x4osw1oyDaS4ocA82/SamxWZ8cShFOU7+piO5gp9UQtbW18y/1Jn4SQ== X-Received: by 2002:adf:ec8f:: with SMTP id z15mr20066773wrn.290.1550581099459; Tue, 19 Feb 2019 04:58:19 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 19 Feb 2019 12:58:06 +0000 Message-Id: <20190219125808.25174-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190219125808.25174-1-peter.maydell@linaro.org> References: <20190219125808.25174-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH 6/8] hw/arm/iotkit-sysctl: Add SSE-200 registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The SYSCTL block in the SSE-200 has some extra registers that are not present in the IoTKit version. Add these registers (as reads-as-written stubs), enabled by a new QOM property. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/misc/iotkit-sysctl.h | 20 +++ hw/arm/armsse.c | 2 + hw/misc/iotkit-sysctl.c | 245 +++++++++++++++++++++++++++++++- 3 files changed, 262 insertions(+), 5 deletions(-) diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysct= l.h index 17a145517a4..9c2f23ecd28 100644 --- a/include/hw/misc/iotkit-sysctl.h +++ b/include/hw/misc/iotkit-sysctl.h @@ -17,6 +17,9 @@ * "system control register" blocks. * * QEMU interface: + * + QOM property "SYS_VERSION": value of the SYS_VERSION register of the + * system information block of the SSE + * (used to identify whether to provide SSE-200-only registers) * + sysbus MMIO region 0: the system information register bank * + sysbus MMIO region 1: the system control register bank */ @@ -44,6 +47,23 @@ typedef struct IoTKitSysCtl { uint32_t initsvtor0; uint32_t cpuwait; uint32_t wicctrl; + uint32_t scsecctrl; + uint32_t fclk_div; + uint32_t sysclk_div; + uint32_t clock_force; + uint32_t initsvtor1; + uint32_t nmi_enable; + uint32_t ewctrl; + uint32_t pdcm_pd_sys_sense; + uint32_t pdcm_pd_sram0_sense; + uint32_t pdcm_pd_sram1_sense; + uint32_t pdcm_pd_sram2_sense; + uint32_t pdcm_pd_sram3_sense; + + /* Properties */ + uint32_t sys_version; + + bool is_sse200; } IoTKitSysCtl; =20 #endif diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 5768d6fbf8b..7c946564ebc 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -997,6 +997,8 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) /* System information registers */ sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysinfo), 0, 0x40020000); /* System control registers */ + object_property_set_int(OBJECT(&s->sysctl), info->sys_version, + "SYS_VERSION", &err); object_property_set_bool(OBJECT(&s->sysctl), true, "realized", &err); if (err) { error_propagate(errp, err); diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c index 8c85aea9309..05606017fc2 100644 --- a/hw/misc/iotkit-sysctl.c +++ b/hw/misc/iotkit-sysctl.c @@ -17,6 +17,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/bitops.h" #include "qemu/log.h" #include "trace.h" #include "qapi/error.h" @@ -28,15 +29,26 @@ REG32(SECDBGSTAT, 0x0) REG32(SECDBGSET, 0x4) REG32(SECDBGCLR, 0x8) +REG32(SCSECCTRL, 0xc) +REG32(FCLK_DIV, 0x10) +REG32(SYSCLK_DIV, 0x14) +REG32(CLOCK_FORCE, 0x18) REG32(RESET_SYNDROME, 0x100) REG32(RESET_MASK, 0x104) REG32(SWRESET, 0x108) FIELD(SWRESET, SWRESETREQ, 9, 1) REG32(GRETREG, 0x10c) REG32(INITSVTOR0, 0x110) +REG32(INITSVTOR1, 0x114) REG32(CPUWAIT, 0x118) -REG32(BUSWAIT, 0x11c) +REG32(NMI_ENABLE, 0x11c) /* BUSWAIT in IoTKit */ REG32(WICCTRL, 0x120) +REG32(EWCTRL, 0x124) +REG32(PDCM_PD_SYS_SENSE, 0x200) +REG32(PDCM_PD_SRAM0_SENSE, 0x20c) +REG32(PDCM_PD_SRAM1_SENSE, 0x210) +REG32(PDCM_PD_SRAM2_SENSE, 0x214) +REG32(PDCM_PD_SRAM3_SENSE, 0x218) REG32(PID4, 0xfd0) REG32(PID5, 0xfd4) REG32(PID6, 0xfd8) @@ -67,6 +79,30 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr = offset, case A_SECDBGSTAT: r =3D s->secure_debug; break; + case A_SCSECCTRL: + if (!s->is_sse200) { + goto bad_offset; + } + r =3D s->scsecctrl; + break; + case A_FCLK_DIV: + if (!s->is_sse200) { + goto bad_offset; + } + r =3D s->fclk_div; + break; + case A_SYSCLK_DIV: + if (!s->is_sse200) { + goto bad_offset; + } + r =3D s->sysclk_div; + break; + case A_CLOCK_FORCE: + if (!s->is_sse200) { + goto bad_offset; + } + r =3D s->clock_force; + break; case A_RESET_SYNDROME: r =3D s->reset_syndrome; break; @@ -79,16 +115,62 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwadd= r offset, case A_INITSVTOR0: r =3D s->initsvtor0; break; + case A_INITSVTOR1: + if (!s->is_sse200) { + goto bad_offset; + } + r =3D s->initsvtor1; + break; case A_CPUWAIT: r =3D s->cpuwait; break; - case A_BUSWAIT: - /* In IoTKit BUSWAIT is reserved, R/O, zero */ - r =3D 0; + case A_NMI_ENABLE: + /* In IoTKit this is named BUSWAIT but is marked reserved, R/O, ze= ro */ + if (!s->is_sse200) { + r =3D 0; + break; + } + r =3D s->nmi_enable; break; case A_WICCTRL: r =3D s->wicctrl; break; + case A_EWCTRL: + if (!s->is_sse200) { + goto bad_offset; + } + r =3D s->ewctrl; + break; + case A_PDCM_PD_SYS_SENSE: + if (!s->is_sse200) { + goto bad_offset; + } + r =3D s->pdcm_pd_sys_sense; + break; + case A_PDCM_PD_SRAM0_SENSE: + if (!s->is_sse200) { + goto bad_offset; + } + r =3D s->pdcm_pd_sram0_sense; + break; + case A_PDCM_PD_SRAM1_SENSE: + if (!s->is_sse200) { + goto bad_offset; + } + r =3D s->pdcm_pd_sram1_sense; + break; + case A_PDCM_PD_SRAM2_SENSE: + if (!s->is_sse200) { + goto bad_offset; + } + r =3D s->pdcm_pd_sram2_sense; + break; + case A_PDCM_PD_SRAM3_SENSE: + if (!s->is_sse200) { + goto bad_offset; + } + r =3D s->pdcm_pd_sram3_sense; + break; case A_PID4 ... A_CID3: r =3D sysctl_id[(offset - A_PID4) / 4]; break; @@ -101,6 +183,7 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr= offset, r =3D 0; break; default: + bad_offset: qemu_log_mask(LOG_GUEST_ERROR, "IoTKit SysCtl read: bad offset %x\n", (int)offset); r =3D 0; @@ -172,14 +255,105 @@ static void iotkit_sysctl_write(void *opaque, hwaddr= offset, qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); } break; - case A_BUSWAIT: /* In IoTKit BUSWAIT is reserved, R/O, zero */ + case A_SCSECCTRL: + if (!s->is_sse200) { + goto bad_offset; + } + qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SCSECCTRL unimplemented\n"= ); + s->scsecctrl =3D value; + break; + case A_FCLK_DIV: + if (!s->is_sse200) { + goto bad_offset; + } + qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl FCLK_DIV unimplemented\n"); + s->fclk_div =3D value; + break; + case A_SYSCLK_DIV: + if (!s->is_sse200) { + goto bad_offset; + } + qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SYSCLK_DIV unimplemented\n= "); + s->sysclk_div =3D value; + break; + case A_CLOCK_FORCE: + if (!s->is_sse200) { + goto bad_offset; + } + qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CLOCK_FORCE unimplemented\= n"); + s->clock_force =3D value; + break; + case A_INITSVTOR1: + if (!s->is_sse200) { + goto bad_offset; + } + qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVTOR1 unimplemented\n= "); + s->initsvtor1 =3D value; + break; + case A_EWCTRL: + if (!s->is_sse200) { + goto bad_offset; + } + qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl EWCTRL unimplemented\n"); + s->ewctrl =3D value; + break; + case A_PDCM_PD_SYS_SENSE: + if (!s->is_sse200) { + goto bad_offset; + } + qemu_log_mask(LOG_UNIMP, + "IoTKit SysCtl PDCM_PD_SYS_SENSE unimplemented\n"); + s->pdcm_pd_sys_sense =3D value; + break; + case A_PDCM_PD_SRAM0_SENSE: + if (!s->is_sse200) { + goto bad_offset; + } + qemu_log_mask(LOG_UNIMP, + "IoTKit SysCtl PDCM_PD_SRAM0_SENSE unimplemented\n"); + s->pdcm_pd_sram0_sense =3D value; + break; + case A_PDCM_PD_SRAM1_SENSE: + if (!s->is_sse200) { + goto bad_offset; + } + qemu_log_mask(LOG_UNIMP, + "IoTKit SysCtl PDCM_PD_SRAM1_SENSE unimplemented\n"); + s->pdcm_pd_sram1_sense =3D value; + break; + case A_PDCM_PD_SRAM2_SENSE: + if (!s->is_sse200) { + goto bad_offset; + } + qemu_log_mask(LOG_UNIMP, + "IoTKit SysCtl PDCM_PD_SRAM2_SENSE unimplemented\n"); + s->pdcm_pd_sram2_sense =3D value; + break; + case A_PDCM_PD_SRAM3_SENSE: + if (!s->is_sse200) { + goto bad_offset; + } + qemu_log_mask(LOG_UNIMP, + "IoTKit SysCtl PDCM_PD_SRAM3_SENSE unimplemented\n"); + s->pdcm_pd_sram3_sense =3D value; + break; + case A_NMI_ENABLE: + /* In IoTKit this is BUSWAIT: reserved, R/O, zero */ + if (!s->is_sse200) { + goto ro_offset; + } + qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl NMI_ENABLE unimplemented\n= "); + s->nmi_enable =3D value; + break; case A_SECDBGSTAT: case A_PID4 ... A_CID3: + ro_offset: qemu_log_mask(LOG_GUEST_ERROR, "IoTKit SysCtl write: write of RO offset %x\n", (int)offset); break; default: + bad_offset: qemu_log_mask(LOG_GUEST_ERROR, "IoTKit SysCtl write: bad offset %x\n", (int)offset); break; @@ -207,8 +381,20 @@ static void iotkit_sysctl_reset(DeviceState *dev) s->reset_mask =3D 0; s->gretreg =3D 0; s->initsvtor0 =3D 0x10000000; + s->initsvtor1 =3D 0x10000000; s->cpuwait =3D 0; s->wicctrl =3D 0; + s->scsecctrl =3D 0; + s->fclk_div =3D 0; + s->sysclk_div =3D 0; + s->clock_force =3D 0; + s->nmi_enable =3D 0; + s->ewctrl =3D 0; + s->pdcm_pd_sys_sense =3D 0x7f; + s->pdcm_pd_sram0_sense =3D 0; + s->pdcm_pd_sram1_sense =3D 0; + s->pdcm_pd_sram2_sense =3D 0; + s->pdcm_pd_sram3_sense =3D 0; } =20 static void iotkit_sysctl_init(Object *obj) @@ -221,6 +407,44 @@ static void iotkit_sysctl_init(Object *obj) sysbus_init_mmio(sbd, &s->iomem); } =20 +static void iotkit_sysctl_realize(DeviceState *dev, Error **errp) +{ + IoTKitSysCtl *s =3D IOTKIT_SYSCTL(dev); + + /* The top 4 bits of the SYS_VERSION register tell us if we're an SSE-= 200 */ + if (extract32(s->sys_version, 28, 4) =3D=3D 2) { + s->is_sse200 =3D true; + } +} + +static bool sse200_needed(void *opaque) +{ + IoTKitSysCtl *s =3D IOTKIT_SYSCTL(opaque); + + return s->is_sse200; +} + +static const VMStateDescription iotkit_sysctl_sse200_vmstate =3D { + .name =3D "iotkit-sysctl/sse-200", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D sse200_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(scsecctrl, IoTKitSysCtl), + VMSTATE_UINT32(fclk_div, IoTKitSysCtl), + VMSTATE_UINT32(sysclk_div, IoTKitSysCtl), + VMSTATE_UINT32(clock_force, IoTKitSysCtl), + VMSTATE_UINT32(initsvtor1, IoTKitSysCtl), + VMSTATE_UINT32(nmi_enable, IoTKitSysCtl), + VMSTATE_UINT32(pdcm_pd_sys_sense, IoTKitSysCtl), + VMSTATE_UINT32(pdcm_pd_sram0_sense, IoTKitSysCtl), + VMSTATE_UINT32(pdcm_pd_sram1_sense, IoTKitSysCtl), + VMSTATE_UINT32(pdcm_pd_sram2_sense, IoTKitSysCtl), + VMSTATE_UINT32(pdcm_pd_sram3_sense, IoTKitSysCtl), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription iotkit_sysctl_vmstate =3D { .name =3D "iotkit-sysctl", .version_id =3D 1, @@ -234,15 +458,26 @@ static const VMStateDescription iotkit_sysctl_vmstate= =3D { VMSTATE_UINT32(cpuwait, IoTKitSysCtl), VMSTATE_UINT32(wicctrl, IoTKitSysCtl), VMSTATE_END_OF_LIST() + }, + .subsections =3D (const VMStateDescription*[]) { + &iotkit_sysctl_sse200_vmstate, + NULL } }; =20 +static Property iotkit_sysctl_props[] =3D { + DEFINE_PROP_UINT32("SYS_VERSION", IoTKitSysCtl, sys_version, 0), + DEFINE_PROP_END_OF_LIST() +}; + static void iotkit_sysctl_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->vmsd =3D &iotkit_sysctl_vmstate; dc->reset =3D iotkit_sysctl_reset; + dc->props =3D iotkit_sysctl_props; + dc->realize =3D iotkit_sysctl_realize; } =20 static const TypeInfo iotkit_sysctl_info =3D { --=20 2.20.1 From nobody Fri May 3 12:59:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1550581542102459.5665253808978; Tue, 19 Feb 2019 05:05:42 -0800 (PST) Received: from localhost ([127.0.0.1]:48004 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gw55a-0007Jp-KR for importer@patchew.org; Tue, 19 Feb 2019 08:05:34 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53328) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gw4yy-00024D-6F for qemu-devel@nongnu.org; Tue, 19 Feb 2019 07:58:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gw4yw-0002yq-Uc for qemu-devel@nongnu.org; Tue, 19 Feb 2019 07:58:43 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:41482) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gw4yp-0002rS-Dh for qemu-devel@nongnu.org; Tue, 19 Feb 2019 07:58:38 -0500 Received: by mail-wr1-x42b.google.com with SMTP id n2so9701400wrw.8 for ; Tue, 19 Feb 2019 04:58:21 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id e75sm5226113wmg.32.2019.02.19.04.58.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Feb 2019 04:58:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=h7p/j2bF8mRYbAEayArl2bX6oWoA1v9jlyX/daxOJvc=; b=PpNqtpeGj5dalW1H3GxIQJB9JGiU/qnLn4PA3sE1sNUmypvkQfbxLw4LRUOFBrHI5A BRImZNFFUk+3kUXO1LhH2iSFkBr3jwIyNVypFMJU5OM2Iuw9095sjRTUiMjxmOEBDBFO ZpB8EcQuqdQBACwumD2yXS4sSR9jBhZnw5EZq47dQMC9laORTtbhAKy+wQc8LHCXfU+J ptjOVqwcmROFYYA6hLty6nupnss92CNBemxw1P1zlnEdpOE2EuimwlybpaVOBLl3suwE L8onE1y3tnmNymXGic9+8FNFDW348q+/2998hjkLycXAP9JtRmpo3nMxD8kQ4Lk3ziMs 1lMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=h7p/j2bF8mRYbAEayArl2bX6oWoA1v9jlyX/daxOJvc=; b=YC1kA72ah6CUpZZHvqgNvv5UAF2igiLgQ7W3MjJ4QwFEWmHouG5QdjIakelHOGA4L4 ISn5ZdBluGOTD/eSek7/M38zKlU54mkA7x+d9bkF6N7giBzoJX37aVRlMoyGOa7J+aI1 c2QUEBGXtJerLR/U0j6mJ1Fndjb5pN9IS3Ar4E4RwUxUUDk9P1EFrimLqpta7jc5g+OR arGFZ73R1XWbqsqE20Dte8x0ylIUB80xTICtj/lbVd9AbHmNcFpHRZfxFSEpIHiS2FXF PRegwJSujlcsxwi6SIJqwMQkdJVmYfCMXsC4MAZSDXISuLXerAZf2ZhMkMtw4Najk1mC tA2A== X-Gm-Message-State: AHQUAuZzPkAU3S9HtKQHevmfZJfdnJlMcdCfCh+LNV4m9lrz0RCrNrAN NmNWsKkRnGqW4Q7tgJYwFXfhHroiBxpQYQ== X-Google-Smtp-Source: AHgI3IaCxkq9FiyT6YwNGynv/gb04ItksS4MYAB9baGciuz6nwHQOiwbBNch0Fu0xYEcFrZOd20N2g== X-Received: by 2002:a5d:4841:: with SMTP id n1mr19444389wrs.85.1550581100559; Tue, 19 Feb 2019 04:58:20 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 19 Feb 2019 12:58:07 +0000 Message-Id: <20190219125808.25174-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190219125808.25174-1-peter.maydell@linaro.org> References: <20190219125808.25174-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42b Subject: [Qemu-devel] [PATCH 7/8] hw/arm/iotkit-sysctl: Implement CPUWAIT and INITSVTOR* X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The CPUWAIT register acts as a sort of power-control: if a bit in it is 1 then the CPU will have been forced into waiting when the system was reset (which in QEMU we model as the CPU starting powered off). Writing a 0 to the register will allow the CPU to boot (for QEMU, we model this as powering it on). Note that writing 0 to the register does not power off a CPU. For this to work correctly we need to also honour the INITSVTOR* registers, which let the guest control where the CPU will load its SP and PC from when it comes out of reset. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/misc/iotkit-sysctl.c | 41 +++++++++++++++++++++++++++++++++++++---- 1 file changed, 37 insertions(+), 4 deletions(-) diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c index 05606017fc2..e333c8169a3 100644 --- a/hw/misc/iotkit-sysctl.c +++ b/hw/misc/iotkit-sysctl.c @@ -25,6 +25,8 @@ #include "hw/sysbus.h" #include "hw/registerfields.h" #include "hw/misc/iotkit-sysctl.h" +#include "target/arm/arm-powerctl.h" +#include "target/arm/cpu.h" =20 REG32(SECDBGSTAT, 0x0) REG32(SECDBGSET, 0x4) @@ -69,6 +71,21 @@ static const int sysctl_id[] =3D { 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ }; =20 +/* + * Set the initial secure vector table offset address for the core. + * This will take effect when the CPU next resets. + */ +static void set_init_vtor(uint64_t cpuid, uint32_t vtor) +{ + Object *cpuobj =3D OBJECT(arm_get_cpu_by_id(cpuid)); + + if (cpuobj) { + if (object_property_find(cpuobj, "init-svtor", NULL)) { + object_property_set_uint(cpuobj, vtor, "init-svtor", &error_ab= ort); + } + } +} + static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset, unsigned size) { @@ -229,11 +246,18 @@ static void iotkit_sysctl_write(void *opaque, hwaddr = offset, s->gretreg =3D value; break; case A_INITSVTOR0: - qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVTOR0 unimplemented\n= "); s->initsvtor0 =3D value; + set_init_vtor(0, s->initsvtor0); break; case A_CPUWAIT: - qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CPUWAIT unimplemented\n"); + if ((s->cpuwait & 1) && !(value & 1)) { + /* Powering up CPU 0 */ + arm_set_cpu_on_and_reset(0); + } + if ((s->cpuwait & 2) && !(value & 2)) { + /* Powering up CPU 1 */ + arm_set_cpu_on_and_reset(1); + } s->cpuwait =3D value; break; case A_WICCTRL: @@ -287,8 +311,8 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, if (!s->is_sse200) { goto bad_offset; } - qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVTOR1 unimplemented\n= "); s->initsvtor1 =3D value; + set_init_vtor(1, s->initsvtor1); break; case A_EWCTRL: if (!s->is_sse200) { @@ -382,7 +406,16 @@ static void iotkit_sysctl_reset(DeviceState *dev) s->gretreg =3D 0; s->initsvtor0 =3D 0x10000000; s->initsvtor1 =3D 0x10000000; - s->cpuwait =3D 0; + if (s->is_sse200) { + /* + * CPU 0 starts on, CPU 1 starts off. In real hardware this is + * configurable by the SoC integrator as a verilog parameter. + */ + s->cpuwait =3D 2; + } else { + /* CPU 0 starts on */ + s->cpuwait =3D 0; + } s->wicctrl =3D 0; s->scsecctrl =3D 0; s->fclk_div =3D 0; --=20 2.20.1 From nobody Fri May 3 12:59:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1550582162876809.9976285263391; Tue, 19 Feb 2019 05:16:02 -0800 (PST) Received: from localhost ([127.0.0.1]:48308 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gw5Fe-0007Hc-My for importer@patchew.org; Tue, 19 Feb 2019 08:15:58 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53307) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gw4yw-00023O-UJ for qemu-devel@nongnu.org; Tue, 19 Feb 2019 07:58:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gw4yn-0002vn-Hr for qemu-devel@nongnu.org; Tue, 19 Feb 2019 07:58:38 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:56128) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gw4yj-0002rz-Ss for qemu-devel@nongnu.org; Tue, 19 Feb 2019 07:58:31 -0500 Received: by mail-wm1-x341.google.com with SMTP id q187so2719269wme.5 for ; Tue, 19 Feb 2019 04:58:22 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id e75sm5226113wmg.32.2019.02.19.04.58.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Feb 2019 04:58:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4O/2DIPuo1vUPn3lTda3Uyrx1AZplqtTL94xX4XAy9k=; b=JgAFmEGHR8ERiE50kYgODUXYJVCSSR4xPCVxYhb5g1nPGo+Uz7cRitrMNizf0GjeFt GSqtmp6ulPvWjyNW6s1Ps08v4xO1yCE8vejAnnL8OJnLX2+CDz0sM1wr9I1HqGTF9l8N NaT4i8ICaVlAoTlZGbC6YeaBIl/l9uKTmX3yv5jpI2easM9s0f1mi63Y5uEy8qM7LZuW w07df+5EKq2R/tu87bjsoIhaYeifiLy8hwIIe6YY0Vx/E6ItTEqyfDc2XpdaEVuIhFI0 ugj/M1C0GaNRDQIjU/bYe1JMTodTZrgR9vz5K8b44MGr709FvQfiLtRu9YE29MjgH4oG c/fA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4O/2DIPuo1vUPn3lTda3Uyrx1AZplqtTL94xX4XAy9k=; b=Zb+oWA06wUL62KPHZAOouBg9drYFj1tN8UsW9rjWHVVfaDOQehK4s0Wk2++6vZXkUg 6eMpZjc/u2+lWzQO9lz1+Z7D8OQEzovfnZWYTgEdu7K2mcLypNiZg3ij2224261XwBze 99jkAhNCmanJK4kPvnu/7TK9zPpieBA95vzZrs64sIWGjb9U+JwttUOIYnwjJzwxNk/4 8qIBukcuQYhGOzs3rkpPfWLWZpO9yvlEujPeu8JaeU3LPBm+1MnO9IVo27KQjtpGswaX bE/VMMUbsLqBg9lMBhCafsb4PVkiEKigrmzhXcoA8xsBZfMshvJ/JinUyvErvHoz26Mt Ghhg== X-Gm-Message-State: AHQUAuYGdk7AtW6sqf8yL5jTtKoRxPACtEEUYnC3axgZEs/9PeQ5O1fA cG6lwE5EEfkcsoi+o7FmXdJhJQ== X-Google-Smtp-Source: AHgI3IbmmtwcAnAc69fHRDIeUME2gKxzjNAwSHyr8l01Bm8iurPW+k6/xDPmK/Npu9ffrgV7lEHlLw== X-Received: by 2002:a1c:a941:: with SMTP id s62mr2861801wme.16.1550581101846; Tue, 19 Feb 2019 04:58:21 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 19 Feb 2019 12:58:08 +0000 Message-Id: <20190219125808.25174-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190219125808.25174-1-peter.maydell@linaro.org> References: <20190219125808.25174-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH 8/8] hw/arm/armsse: Unify init-svtor and cpuwait handling X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" At the moment the handling of init-svtor and cpuwait initial values is split between armsse.c and iotkit-sysctl.c: the code in armsse.c sets the initial state of the CPU object by setting the init-svtor and start-powered-off properties, but the iotkit-sysctl.c code has its own code setting the reset values of its registers (which are then used when updating the CPU when the guest makes runtime changes). Clean this up by making the armsse.c code set properties on the iotkit-sysctl object to define the initial values of the registers, so they always match the initial CPU state, and update the comments in armsse.c accordingly. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/misc/iotkit-sysctl.h | 3 ++ hw/arm/armsse.c | 49 +++++++++++++++++++++------------ hw/misc/iotkit-sysctl.c | 20 ++++++-------- 3 files changed, 42 insertions(+), 30 deletions(-) diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysct= l.h index 9c2f23ecd28..601c8ecc0d0 100644 --- a/include/hw/misc/iotkit-sysctl.h +++ b/include/hw/misc/iotkit-sysctl.h @@ -62,6 +62,9 @@ typedef struct IoTKitSysCtl { =20 /* Properties */ uint32_t sys_version; + uint32_t cpuwait_rst; + uint32_t initsvtor0_rst; + uint32_t initsvtor1_rst; =20 bool is_sse200; } IoTKitSysCtl; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 7c946564ebc..027e113f2ee 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -11,6 +11,7 @@ =20 #include "qemu/osdep.h" #include "qemu/log.h" +#include "qemu/bitops.h" #include "qapi/error.h" #include "trace.h" #include "hw/sysbus.h" @@ -29,6 +30,7 @@ struct ARMSSEInfo { int sram_banks; int num_cpus; uint32_t sys_version; + uint32_t cpuwait_rst; SysConfigFormat sys_config_format; bool has_mhus; bool has_ppus; @@ -43,6 +45,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .sram_banks =3D 1, .num_cpus =3D 1, .sys_version =3D 0x41743, + .cpuwait_rst =3D 0, .sys_config_format =3D IoTKitFormat, .has_mhus =3D false, .has_ppus =3D false, @@ -55,6 +58,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .sram_banks =3D 4, .num_cpus =3D 2, .sys_version =3D 0x22041743, + .cpuwait_rst =3D 2, .sys_config_format =3D SSE200Format, .has_mhus =3D true, .has_ppus =3D true, @@ -495,30 +499,33 @@ static void armsse_realize(DeviceState *dev, Error **= errp) =20 qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + 32); /* - * In real hardware the initial Secure VTOR is set from the INITSV= TOR0 - * register in the IoT Kit System Control Register block, and the - * initial value of that is in turn specifiable by the FPGA that - * instantiates the IoT Kit. In QEMU we don't implement this wrink= le, - * and simply set the CPU's init-svtor to the IoT Kit default valu= e. - * In SSE-200 the situation is similar, except that the default va= lue - * is a reset-time signal input. Typically a board using the SSE-2= 00 - * will have a system control processor whose boot firmware initia= lizes - * the INITSVTOR* registers before powering up the CPUs in any cas= e, - * so the hardware's default value doesn't matter. QEMU doesn't em= ulate + * In real hardware the initial Secure VTOR is set from the INITSV= TOR* + * registers in the IoT Kit System Control Register block. In QEMU + * we set the initial value here, and also the reset value of the + * sysctl register, from this object's QOM init-svtor property. + * If the guest changes the INITSVTOR* registers at runtime then t= he + * code in iotkit-sysctl.c will update the CPU init-svtor property + * (which will then take effect on the next CPU warm-reset). + * + * Note that typically a board using the SSE-200 will have a system + * control processor whose boot firmware initializes the INITSVTOR* + * registers before powering up the CPUs. QEMU doesn't emulate * the control processor, so instead we behave in the way that the - * firmware does. The initial value is configurable by the board c= ode - * to match whatever its firmware does. + * firmware does: the initial value should be set by the board code + * (using the init-svtor property on the ARMSSE object) to match + * whatever its firmware does. */ qdev_prop_set_uint32(cpudev, "init-svtor", s->init_svtor); /* - * Start all CPUs except CPU0 powered down. In real hardware it is - * a configurable property of the SSE-200 which CPUs start powered= up - * (via the CPUWAIT0_RST and CPUWAIT1_RST parameters), but since a= ll - * the boards we care about start CPU0 and leave CPU1 powered off, - * we hard-code that for now. We can add QOM properties for this + * CPUs start powered down if the corresponding bit in the CPUWAIT + * register is 1. In real hardware the CPUWAIT register reset valu= e is + * a configurable property of the SSE-200 (via the CPUWAIT0_RST and + * CPUWAIT1_RST parameters), but since all the boards we care about + * start CPU0 and leave CPU1 powered off, we hard-code that in + * info->cpuwait_rst for now. We can add QOM properties for this * later if necessary. */ - if (i > 0) { + if (extract32(info->cpuwait_rst, i, 1)) { object_property_set_bool(cpuobj, true, "start-powered-off", &e= rr); if (err) { error_propagate(errp, err); @@ -999,6 +1006,12 @@ static void armsse_realize(DeviceState *dev, Error **= errp) /* System control registers */ object_property_set_int(OBJECT(&s->sysctl), info->sys_version, "SYS_VERSION", &err); + object_property_set_int(OBJECT(&s->sysctl), info->cpuwait_rst, + "CPUWAIT_RST", &err); + object_property_set_int(OBJECT(&s->sysctl), s->init_svtor, + "INITSVTOR0_RST", &err); + object_property_set_int(OBJECT(&s->sysctl), s->init_svtor, + "INITSVTOR1_RST", &err); object_property_set_bool(OBJECT(&s->sysctl), true, "realized", &err); if (err) { error_propagate(errp, err); diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c index e333c8169a3..54064a31ef0 100644 --- a/hw/misc/iotkit-sysctl.c +++ b/hw/misc/iotkit-sysctl.c @@ -404,18 +404,9 @@ static void iotkit_sysctl_reset(DeviceState *dev) s->reset_syndrome =3D 1; s->reset_mask =3D 0; s->gretreg =3D 0; - s->initsvtor0 =3D 0x10000000; - s->initsvtor1 =3D 0x10000000; - if (s->is_sse200) { - /* - * CPU 0 starts on, CPU 1 starts off. In real hardware this is - * configurable by the SoC integrator as a verilog parameter. - */ - s->cpuwait =3D 2; - } else { - /* CPU 0 starts on */ - s->cpuwait =3D 0; - } + s->initsvtor0 =3D s->initsvtor0_rst; + s->initsvtor1 =3D s->initsvtor1_rst; + s->cpuwait =3D s->cpuwait_rst; s->wicctrl =3D 0; s->scsecctrl =3D 0; s->fclk_div =3D 0; @@ -500,6 +491,11 @@ static const VMStateDescription iotkit_sysctl_vmstate = =3D { =20 static Property iotkit_sysctl_props[] =3D { DEFINE_PROP_UINT32("SYS_VERSION", IoTKitSysCtl, sys_version, 0), + DEFINE_PROP_UINT32("CPUWAIT_RST", IoTKitSysCtl, cpuwait_rst, 0), + DEFINE_PROP_UINT32("INITSVTOR0_RST", IoTKitSysCtl, initsvtor0_rst, + 0x10000000), + DEFINE_PROP_UINT32("INITSVTOR1_RST", IoTKitSysCtl, initsvtor1_rst, + 0x10000000), DEFINE_PROP_END_OF_LIST() }; =20 --=20 2.20.1