From nobody Sun Oct 6 10:18:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1550501185130314.9438014999315; Mon, 18 Feb 2019 06:46:25 -0800 (PST) Received: from localhost ([127.0.0.1]:59773 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gvkBZ-0001Lv-4b for importer@patchew.org; Mon, 18 Feb 2019 09:46:21 -0500 Received: from eggs.gnu.org ([209.51.188.92]:38641) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gvjws-0005XC-5W for qemu-devel@nongnu.org; Mon, 18 Feb 2019 09:31:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gvjwl-0002ap-2k for qemu-devel@nongnu.org; Mon, 18 Feb 2019 09:31:09 -0500 Received: from ozlabs.org ([203.11.71.1]:54069) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gvjwj-0002WK-JW; Mon, 18 Feb 2019 09:31:02 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 4435rc69Xxz9sPc; Tue, 19 Feb 2019 01:30:56 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1550500256; bh=yCpvtMtOy2sg4LROwvXiCB6Az/0gCld5AU7a4tsq5q8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=T6ed77lN6b8XrIOhD3uI4y2odMk9RdYFAk4mPstM2vz5b2FLw02QDV4XyGrVciEJc J1zguxT/Aedf6BoCWustYplafYpHUaJF32WLUArCHtWMndDmsOu0Xe3jGQ3EDqH/uA FIfXjs+nwZn1jlxEX4d6X2WF545Gye2OqvzlN6wo= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 19 Feb 2019 01:30:10 +1100 Message-Id: <20190218143049.17142-5-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190218143049.17142-1-david@gibson.dropbear.id.au> References: <20190218143049.17142-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 04/43] target/ppc: Fix msync to do what hardware does X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: BALATON Zoltan According to BookE docs, invalid bits (while undefined behaviour) should not raise exception but be ignored. This seems to be implementation dependent though and QEMU currently does what e500 CPUs do and raise exception for invalid bits. Unfortunately some versions of libstdc++ (and so all programs compiled with it) have lwsync on PPC440 which is invalid but on real hardware it's just executed as msync ignoring the invalid bits (maybe that's why it got undetected) but they fail on QEMU. This patch changes invalid mask of msync to allow these programs to run but keep generating exception on e500 cores to follow what hardware does. Signed-off-by: BALATON Zoltan Signed-off-by: David Gibson --- target/ppc/translate.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index e169c43643..5429ceb1ab 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6476,7 +6476,12 @@ static void gen_mbar(DisasContext *ctx) /* msync replaces sync on 440 */ static void gen_msync_4xx(DisasContext *ctx) { - /* interpreted as no-op */ + /* Only e500 seems to treat reserved bits as invalid */ + if ((ctx->insns_flags2 & PPC2_BOOKE206) && + (ctx->opcode & 0x03FFF801)) { + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); + } + /* otherwise interpreted as no-op */ } =20 /* icbt */ @@ -7054,11 +7059,11 @@ GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, P= PC_WRTEE), GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, PPC_BOOKE, PPC2_BOOKE206), -GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), +GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE, PPC2_BOOKE206), GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, - PPC_440_SPEC), + PPC_440_SPEC), GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), --=20 2.20.1