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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y5sm2503360wmg.31.2019.02.15.10.05.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 15 Feb 2019 10:05:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=7jDC0BbGafD6lfyjfl1Pi9GQ9ZpZGO7Lekb8UiW3pSg=; b=UTkofiREe1jO4ezUSPyUoxRbS47OGuj9WRlYASTelRnEHKbUD4AiBCfTZiiEheNWjT Qi1WUg/Qq7wm4CgrBn4uDQq4/aEpCkxsWjWawTqgvYDmMshSYd2urdxwudUGZP6xP664 qwQyAlJhYQcxWyh8dgyJ27BH6tLOmxqRT4FzZoQlpvb9o3t2p+io1o+mjsJZY2UREykr TMqMEkpmLRjkAv84be1GlI7/YDydlaAvOenjXB7yGx6wnlyJx0Jw5xwhRlUZmRsVuY/0 Fh518T8Mexw8S3qqok8M5oT4FIf07l4AmyYDiBzhSAZ4NR68OTkNbnXmIqdJnjrPXRJX 5IHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=7jDC0BbGafD6lfyjfl1Pi9GQ9ZpZGO7Lekb8UiW3pSg=; b=hH9WKcy1HUh4IpuZKVAWYg6M9CQ0XlqKrdXli58rRH4ejzlqYvuhhpJZRZt6wMjv/o zWsU+crBqyScdKdF5y+ZfO/l4hB5JCIoGpmPvrRT76BveZqHK6oz5TvbFMCBpMXzq5Z8 I/Re0AzeXkKn2wVIA27T/lbvu/sbMVU8b8PxxCPBjnQyzR3OBWyNw3MzVFBF+blVrjH6 Gdl4DJ1wEtEgLr0HOd9G2bxL4QZmNFaU+AcB8S/1qpsYIw+HLxHG+adUs4z/C2zx1kPq h1upWJiSzhobB7avQSvulG/7IegrboiPCMI1Q/rzPFpfQxz83nFLfrpVyOgY7xGOwg34 TMGw== X-Gm-Message-State: AHQUAuZ3VVIqDpQKYMhd8JJtfRMYyhGur9hwiR1mAvU7dy5qwATDmMaP gVFoHyJPMZK/EjogoRXAV5GkFg== X-Google-Smtp-Source: AHgI3Iag9jYk8ugiP040q767djGXgoKZqjZymkgraBbhlTHCTzEYcyy2aEbCj4TKv4Htx+kuFCIGQg== X-Received: by 2002:a5d:6810:: with SMTP id w16mr7721000wru.62.1550253903150; Fri, 15 Feb 2019 10:05:03 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Fri, 15 Feb 2019 18:05:00 +0000 Message-Id: <20190215180500.6906-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH] hw/arm/armsse: Make 0x5... alias region work for per-CPU devices X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The region 0x40010000 .. 0x4001ffff and its secure-only alias at 0x50010000... are for per-CPU devices. We implement this by giving each CPU its own container memory region, where the per-CPU devices live. Unfortunately, the alias region which makes devices mapped at 0x4... addresses also appear at 0x5... is only implemented in the overall "all CPUs" container. The effect of this bug is that the CPU_IDENTITY register block appears only at 0x4001f000, but not at the 0x5001f000 alias where it should also appear. Guests (like very recent Arm Trusted Firmware-M) which try to access it at 0x5001f000 will crash. Fix this by moving the handling for this alias from the "all CPUs" container to the per-CPU container. (We leave the aliases for 0x1... and 0x3... in the overall container, because there are no per-CPU devices there.) Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e --- include/hw/arm/armsse.h | 2 +- hw/arm/armsse.c | 26 ++++++++++++++++---------- 2 files changed, 17 insertions(+), 11 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index f800bafb14a..5a845b3478d 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -182,7 +182,7 @@ typedef struct ARMSSE { MemoryRegion cpu_container[SSE_MAX_CPUS]; MemoryRegion alias1; MemoryRegion alias2; - MemoryRegion alias3; + MemoryRegion alias3[SSE_MAX_CPUS]; MemoryRegion sram[MAX_SRAM_BANKS]; =20 qemu_irq *exp_irqs[SSE_MAX_CPUS]; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index d0207dbabc7..ee1357312f1 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -110,15 +110,16 @@ static bool irq_is_common[32] =3D { /* 30, 31: reserved */ }; =20 -/* Create an alias region of @size bytes starting at @base +/* + * Create an alias region in @container of @size bytes starting at @base * which mirrors the memory starting at @orig. */ -static void make_alias(ARMSSE *s, MemoryRegion *mr, const char *name, - hwaddr base, hwaddr size, hwaddr orig) +static void make_alias(ARMSSE *s, MemoryRegion *mr, MemoryRegion *containe= r, + const char *name, hwaddr base, hwaddr size, hwaddr = orig) { - memory_region_init_alias(mr, NULL, name, &s->container, orig, size); + memory_region_init_alias(mr, NULL, name, container, orig, size); /* The alias is even lower priority than unimplemented_device regions = */ - memory_region_add_subregion_overlap(&s->container, base, mr, -1500); + memory_region_add_subregion_overlap(container, base, mr, -1500); } =20 static void irq_status_forwarder(void *opaque, int n, int level) @@ -608,16 +609,21 @@ static void armsse_realize(DeviceState *dev, Error **= errp) } =20 /* Set up the big aliases first */ - make_alias(s, &s->alias1, "alias 1", 0x10000000, 0x10000000, 0x0000000= 0); - make_alias(s, &s->alias2, "alias 2", 0x30000000, 0x10000000, 0x2000000= 0); + make_alias(s, &s->alias1, &s->container, "alias 1", + 0x10000000, 0x10000000, 0x00000000); + make_alias(s, &s->alias2, &s->container, + "alias 2", 0x30000000, 0x10000000, 0x20000000); /* The 0x50000000..0x5fffffff region is not a pure alias: it has * a few extra devices that only appear there (generally the * control interfaces for the protection controllers). * We implement this by mapping those devices over the top of this - * alias MR at a higher priority. + * alias MR at a higher priority. Some of the devices in this range + * are per-CPU, so we must put this alias in the per-cpu containers. */ - make_alias(s, &s->alias3, "alias 3", 0x50000000, 0x10000000, 0x4000000= 0); - + for (i =3D 0; i < info->num_cpus; i++) { + make_alias(s, &s->alias3[i], &s->cpu_container[i], + "alias 3", 0x50000000, 0x10000000, 0x40000000); + } =20 /* Security controller */ object_property_set_bool(OBJECT(&s->secctl), true, "realized", &err); --=20 2.20.1