From nobody Mon Feb 9 22:39:17 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1550247975018614.6176210864959; Fri, 15 Feb 2019 08:26:15 -0800 (PST) Received: from localhost ([127.0.0.1]:42490 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gugJX-00012g-2c for importer@patchew.org; Fri, 15 Feb 2019 11:26:11 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52057) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gugAh-00034q-SR for qemu-devel@nongnu.org; Fri, 15 Feb 2019 11:17:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gugAf-0005fi-2K for qemu-devel@nongnu.org; Fri, 15 Feb 2019 11:17:03 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:36896 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gugAe-0005dr-Pn for qemu-devel@nongnu.org; Fri, 15 Feb 2019 11:17:00 -0500 Received: from pps.filterd (m0098417.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x1FGBcCm108967 for ; Fri, 15 Feb 2019 11:17:00 -0500 Received: from e06smtp04.uk.ibm.com (e06smtp04.uk.ibm.com [195.75.94.100]) by mx0a-001b2d01.pphosted.com with ESMTP id 2qp0ga1pg2-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 15 Feb 2019 11:16:58 -0500 Received: from localhost by e06smtp04.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 15 Feb 2019 16:16:52 -0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x1FGGp2139583936 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 15 Feb 2019 16:16:51 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6697B11C058; Fri, 15 Feb 2019 16:16:51 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4B54A11C052; Fri, 15 Feb 2019 16:16:51 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 15 Feb 2019 16:16:51 +0000 (GMT) Received: from zorba.lab.toulouse-stg.fr.ibm.com (zorba.lab.toulouse-stg.fr.ibm.com [9.101.4.32]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id 154E72203AC; Fri, 15 Feb 2019 17:16:51 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Fri, 15 Feb 2019 17:16:47 +0100 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190215161648.9600-1-clg@kaod.org> References: <20190215161648.9600-1-clg@kaod.org> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19021516-0016-0000-0000-00000256EEC1 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19021516-0017-0000-0000-000032B12561 Message-Id: <20190215161648.9600-10-clg@kaod.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-02-15_12:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1902150111 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by mx0a-001b2d01.pphosted.com id x1FGBcCm108967 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH 09/10] target/ppc: Add POWER9 external interrupt model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Benjamin Herrenschmidt Adds support for the Hypervisor directed interrupts in addition to the OS ones. Signed-off-by: Benjamin Herrenschmidt [clg: - modified the icp_realize() and xive_tctx_realize() to take into account explicitely the POWER9 interrupt model - introduced a specific power9_set_irq for POWER9 ] Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/ppc.h | 2 ++ target/ppc/cpu-qom.h | 2 ++ target/ppc/cpu.h | 7 ++++++ hw/intc/xics.c | 3 +++ hw/intc/xive.c | 3 +++ hw/ppc/ppc.c | 42 +++++++++++++++++++++++++++++++++ target/ppc/translate_init.inc.c | 4 ++-- 7 files changed, 61 insertions(+), 2 deletions(-) diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h index 298ec354a8a8..746170f635c6 100644 --- a/include/hw/ppc/ppc.h +++ b/include/hw/ppc/ppc.h @@ -73,6 +73,7 @@ static inline void ppc40x_irq_init(PowerPCCPU *cpu) {} static inline void ppc6xx_irq_init(PowerPCCPU *cpu) {} static inline void ppc970_irq_init(PowerPCCPU *cpu) {} static inline void ppcPOWER7_irq_init(PowerPCCPU *cpu) {} +static inline void ppcPOWER9_irq_init(PowerPCCPU *cpu) {} static inline void ppce500_irq_init(PowerPCCPU *cpu) {} #else void ppc40x_irq_init(PowerPCCPU *cpu); @@ -80,6 +81,7 @@ void ppce500_irq_init(PowerPCCPU *cpu); void ppc6xx_irq_init(PowerPCCPU *cpu); void ppc970_irq_init(PowerPCCPU *cpu); void ppcPOWER7_irq_init(PowerPCCPU *cpu); +void ppcPOWER9_irq_init(PowerPCCPU *cpu); #endif =20 /* PPC machines for OpenBIOS */ diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 904ee694ac40..ae51fe754ecd 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -142,6 +142,8 @@ enum powerpc_input_t { PPC_FLAGS_INPUT_970, /* PowerPC POWER7 bus */ PPC_FLAGS_INPUT_POWER7, + /* PowerPC POWER9 bus */ + PPC_FLAGS_INPUT_POWER9, /* PowerPC 401 bus */ PPC_FLAGS_INPUT_401, /* Freescale RCPU bus */ diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index ce55aa209770..42cad1ee06f6 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2327,6 +2327,13 @@ enum { * them */ POWER7_INPUT_NB, }; + +enum { + /* POWER9 input pins */ + POWER9_INPUT_INT =3D 0, + POWER9_INPUT_HINT =3D 1, + POWER9_INPUT_NB, +}; #endif =20 /* Hardware exceptions definitions */ diff --git a/hw/intc/xics.c b/hw/intc/xics.c index 16e8ffa2aaf7..643f1dfcece8 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -344,6 +344,9 @@ static void icp_realize(DeviceState *dev, Error **errp) case PPC_FLAGS_INPUT_POWER7: icp->output =3D env->irq_inputs[POWER7_INPUT_INT]; break; + case PPC_FLAGS_INPUT_POWER9: /* For SPAPR xics emulation */ + icp->output =3D env->irq_inputs[POWER9_INPUT_INT]; + break; =20 case PPC_FLAGS_INPUT_970: icp->output =3D env->irq_inputs[PPC970_INPUT_INT]; diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 2e9b8efd4342..425aa97ef9f6 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -484,6 +484,9 @@ static void xive_tctx_realize(DeviceState *dev, Error *= *errp) case PPC_FLAGS_INPUT_POWER7: tctx->output =3D env->irq_inputs[POWER7_INPUT_INT]; break; + case PPC_FLAGS_INPUT_POWER9: + tctx->output =3D env->irq_inputs[POWER9_INPUT_INT]; + break; =20 default: error_setg(errp, "XIVE interrupt controller does not support " diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index 12439dbe5d43..d1e3d4cd207e 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -306,6 +306,48 @@ void ppcPOWER7_irq_init(PowerPCCPU *cpu) env->irq_inputs =3D (void **)qemu_allocate_irqs(&power7_set_irq, cpu, POWER7_INPUT_NB); } + +/* POWER9 internal IRQ controller */ +static void power9_set_irq(void *opaque, int pin, int level) +{ + PowerPCCPU *cpu =3D opaque; + CPUPPCState *env =3D &cpu->env; + + LOG_IRQ("%s: env %p pin %d level %d\n", __func__, + env, pin, level); + + switch (pin) { + case POWER9_INPUT_INT: + /* Level sensitive - active high */ + LOG_IRQ("%s: set the external IRQ state to %d\n", + __func__, level); + ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); + break; + case POWER9_INPUT_HINT: + /* Level sensitive - active high */ + LOG_IRQ("%s: set the external IRQ state to %d\n", + __func__, level); + ppc_set_irq(cpu, PPC_INTERRUPT_HVIRT, level); + break; + default: + /* Unknown pin - do nothing */ + LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); + return; + } + if (level) { + env->irq_input_state |=3D 1 << pin; + } else { + env->irq_input_state &=3D ~(1 << pin); + } +} + +void ppcPOWER9_irq_init(PowerPCCPU *cpu) +{ + CPUPPCState *env =3D &cpu->env; + + env->irq_inputs =3D (void **)qemu_allocate_irqs(&power9_set_irq, cpu, + POWER9_INPUT_NB); +} #endif /* defined(TARGET_PPC64) */ =20 void ppc40x_core_reset(PowerPCCPU *cpu) diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.in= c.c index ae88e004faef..befa1a95cd77 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -8793,7 +8793,7 @@ static void init_proc_POWER9(CPUPPCState *env) =20 /* Allocate hardware IRQ controller */ init_excp_POWER9(env); - ppcPOWER7_irq_init(ppc_env_get_cpu(env)); + ppcPOWER9_irq_init(ppc_env_get_cpu(env)); } =20 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr) @@ -8920,7 +8920,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) pcc->radix_page_info =3D &POWER9_radix_page_info; #endif pcc->excp_model =3D POWERPC_EXCP_POWER9; - pcc->bus_model =3D PPC_FLAGS_INPUT_POWER7; + pcc->bus_model =3D PPC_FLAGS_INPUT_POWER9; pcc->bfd_mach =3D bfd_mach_ppc64; pcc->flags =3D POWERPC_FLAG_VRE | POWERPC_FLAG_SE | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | --=20 2.20.1