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(localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 4F1FE1FF82; Fri, 15 Feb 2019 14:31:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fa5n8QN3ki2CfZFIch/iiZRZse7EswI3t2HkK/o+qvM=; b=k1aIK+uitKQo/vfBUAjdIDuwgHFOni8thvqP1leD/7CqY5Io+w19eAYVMvDsCpvvL0 7PDJDDwNg3WJoxdAJERalaqJdpXk3wcYx4SGKSqfMe1iE/hmtCwVLsEqKxQFW4nVc5UT pW81IEZEo16rgVG13TyfJ9A6PsVAoGt5LH6GYrvPy9nB45rbmXFrjrpcqHB7mVShCE6Q ubScp3LCRxaCMGsZVsYMXXLfsuoMMZFsIVg6QDNuXdqeMFFq3lz/2DULWI/Ebv8bvSrE 3MOYF2bhYFoKEuSW2O3BcTt3PXt/G4otTT3FFc1DE6ZBt8G78ZXKeEqEoAj/SN6yVoBh d5Aw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fa5n8QN3ki2CfZFIch/iiZRZse7EswI3t2HkK/o+qvM=; b=JlCHYMITBfUvGE829jUXJYvzf/aNBW9fPheyiA2xR69QYR+XK6iZB8z1VGmGoptqx8 eNXtks7XYxSw9MrpIRNHXQQ3zlKyEuo7e/6pvhEuZ9mPq0EDEiZ2xXMcK5LdFF/snmZC PVrCiahJKYyTt9E221McUPfQmujrZqkaOKqpied8Vh9ZjSkoyCMEM51zU80hteViCo+D YPAdKwv7fxdzb21iGskdM4BdKs6zKP5V/WyYIEFcp7zmBR1Vi1NcPt4CgKWPRC1pY9Eg dZZ93P0uO4dnVOWF6g3YOMkez5HZhUNQraHi78nH+RLJfdeWjsNAZ8z7jEHJTyxqqZC9 pr3g== X-Gm-Message-State: AHQUAuadFsOGPDKdvSj/5SHCh5i/2J5SMZa/68ny+d7SkrTy+ITvBi/B Y8wgHNw6TJxLK1JCL0dLiOGNTA== X-Google-Smtp-Source: AHgI3IZCNmwvu/mjlOO601j6HQfRMmlHkqjXVtHbAv+uHqIy6CKrcdXncEk4n/i55YDKS5XUOnZXSw== X-Received: by 2002:a1c:2985:: with SMTP id p127mr6493944wmp.63.1550241076940; Fri, 15 Feb 2019 06:31:16 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Fri, 15 Feb 2019 14:31:13 +0000 Message-Id: <20190215143115.28777-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190215143115.28777-1-alex.bennee@linaro.org> References: <20190215143115.28777-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::336 Subject: [Qemu-devel] [PATCH v3 1/3] accel/tcg: demacro cputlb X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , cota@braap.org, mark.cave-ayland@ilande.co.uk Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Instead of expanding a series of macros to generate the load/store helpers we move stuff into common functions and rely on the compiler to eliminate the dead code for each variant. Signed-off-by: Alex Benn=C3=A9e --- v3 - rebase, apply tlb_fill fixes from 20190209162745.12668-3-cota@braap.org - ensure load_helper honours code/read in the victim_tlb access - convert comments to proper block style --- accel/tcg/cputlb.c | 483 ++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 457 insertions(+), 26 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 88cc8389e9..351f579fed 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1167,26 +1167,426 @@ static void *atomic_mmu_lookup(CPUArchState *env, = target_ulong addr, } =20 #ifdef TARGET_WORDS_BIGENDIAN -# define TGT_BE(X) (X) -# define TGT_LE(X) BSWAP(X) +#define NEED_BE_BSWAP 0 +#define NEED_LE_BSWAP 1 #else -# define TGT_BE(X) BSWAP(X) -# define TGT_LE(X) (X) +#define NEED_BE_BSWAP 1 +#define NEED_LE_BSWAP 0 #endif =20 -#define MMUSUFFIX _mmu +/* + * Byte Swap Helper + * + * This should all dead code away depending on the build host and + * access type. + */ =20 -#define DATA_SIZE 1 -#include "softmmu_template.h" +static inline uint64_t handle_bswap(uint64_t val, int size, bool big_endia= n) +{ + if ((big_endian && NEED_BE_BSWAP) || (!big_endian && NEED_LE_BSWAP)) { + switch (size) { + case 1: return val; + case 2: return bswap16(val); + case 4: return bswap32(val); + case 8: return bswap64(val); + default: + g_assert_not_reached(); + } + } else { + return val; + } +} =20 -#define DATA_SIZE 2 -#include "softmmu_template.h" +/* + * Load Helpers + * + * We support two different access types. SOFTMMU_CODE_ACCESS is + * specifically for reading instructions from system memory. It is + * called by the translation loop and in some helpers where the code + * is disassembled. It shouldn't be called directly by guest code. + */ =20 -#define DATA_SIZE 4 -#include "softmmu_template.h" +static tcg_target_ulong load_helper(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr, + size_t size, bool big_endian, + bool code_read) +{ + uintptr_t mmu_idx =3D get_mmuidx(oi); + uintptr_t index =3D tlb_index(env, mmu_idx, addr); + CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); + target_ulong tlb_addr =3D code_read ? entry->addr_code : entry->addr_r= ead; + const size_t tlb_off =3D code_read ? + offsetof(CPUTLBEntry, addr_code) : offsetof(CPUTLBEntry, addr_read= ); + unsigned a_bits =3D get_alignment_bits(get_memop(oi)); + uintptr_t haddr; + tcg_target_ulong res; + + /* Handle CPU specific unaligned behaviour */ + if (addr & ((1 << a_bits) - 1)) { + cpu_unaligned_access(ENV_GET_CPU(env), addr, + code_read ? MMU_INST_FETCH : MMU_DATA_LOAD, + mmu_idx, retaddr); + } =20 -#define DATA_SIZE 8 -#include "softmmu_template.h" + /* If the TLB entry is for a different page, reload and try again. */ + if (!tlb_hit(tlb_addr, addr)) { + if (!victim_tlb_hit(env, mmu_idx, index, tlb_off, + addr & TARGET_PAGE_MASK)) { + tlb_fill(ENV_GET_CPU(env), addr, size, + code_read ? MMU_INST_FETCH : MMU_DATA_LOAD, + mmu_idx, retaddr); + index =3D tlb_index(env, mmu_idx, addr); + entry =3D tlb_entry(env, mmu_idx, addr); + } + tlb_addr =3D code_read ? entry->addr_code : entry->addr_read; + } + + /* Handle an IO access. */ + if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { + CPUIOTLBEntry *iotlbentry =3D &env->iotlb[mmu_idx][index]; + uint64_t tmp; + + if ((addr & (size - 1)) !=3D 0) { + goto do_unaligned_access; + } + + tmp =3D io_readx(env, iotlbentry, mmu_idx, addr, retaddr, + addr & tlb_addr & TLB_RECHECK, + code_read ? MMU_INST_FETCH : MMU_DATA_LOAD, size); + return handle_bswap(tmp, size, big_endian); + } + + /* Handle slow unaligned access (it spans two pages or IO). */ + if (size > 1 + && unlikely((addr & ~TARGET_PAGE_MASK) + size - 1 + >=3D TARGET_PAGE_SIZE)) { + target_ulong addr1, addr2; + tcg_target_ulong r1, r2; + unsigned shift; + do_unaligned_access: + addr1 =3D addr & ~(size - 1); + addr2 =3D addr1 + size; + r1 =3D load_helper(env, addr1, oi, retaddr, size, big_endian, code= _read); + r2 =3D load_helper(env, addr2, oi, retaddr, size, big_endian, code= _read); + shift =3D (addr & (size - 1)) * 8; + + if (big_endian) { + /* Big-endian combine. */ + res =3D (r1 << shift) | (r2 >> ((size * 8) - shift)); + } else { + /* Little-endian combine. */ + res =3D (r1 >> shift) | (r2 << ((size * 8) - shift)); + } + return res; + } + + haddr =3D addr + entry->addend; + + switch (size) { + case 1: + res =3D ldub_p((uint8_t *)haddr); + break; + case 2: + if (big_endian) { + res =3D lduw_be_p((uint8_t *)haddr); + } else { + res =3D lduw_le_p((uint8_t *)haddr); + } + break; + case 4: + if (big_endian) { + res =3D ldl_be_p((uint8_t *)haddr); + } else { + res =3D ldl_le_p((uint8_t *)haddr); + } + break; + case 8: + if (big_endian) { + res =3D ldq_be_p((uint8_t *)haddr); + } else { + res =3D ldq_le_p((uint8_t *)haddr); + } + break; + default: + g_assert_not_reached(); + break; + } + + return res; +} + +/* + * For the benefit of TCG generated code, we want to avoid the + * complication of ABI-specific return type promotion and always + * return a value extended to the register size of the host. This is + * tcg_target_long, except in the case of a 32-bit host and 64-bit + * data, and for that we always have uint64_t. + * + * We don't bother with this widened value for SOFTMMU_CODE_ACCESS. + */ + +tcg_target_ulong __attribute__((flatten)) +helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 1, false, false); +} + +tcg_target_ulong __attribute__((flatten)) +helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 2, false, false); +} + +tcg_target_ulong __attribute__((flatten)) +helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 2, true, false); +} + +tcg_target_ulong __attribute__((flatten)) +helper_le_ldul_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 4, false, false); +} + +tcg_target_ulong __attribute__((flatten)) +helper_be_ldul_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 4, true, false); +} + +uint64_t __attribute__((flatten)) +helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 8, false, false); +} + +uint64_t __attribute__((flatten)) +helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 8, true, false); +} + +/* + * Provide signed versions of the load routines as well. We can of course + * avoid this for 64-bit data, or for 32-bit data on 32-bit host. + */ + + +tcg_target_ulong __attribute__((flatten)) +helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return (int8_t)helper_ret_ldub_mmu(env, addr, oi, retaddr); +} + +tcg_target_ulong __attribute__((flatten)) +helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return (int16_t)helper_le_lduw_mmu(env, addr, oi, retaddr); +} + +tcg_target_ulong __attribute__((flatten)) +helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return (int16_t)helper_be_lduw_mmu(env, addr, oi, retaddr); +} + +tcg_target_ulong +helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return (int32_t)helper_le_lduw_mmu(env, addr, oi, retaddr); +} + +tcg_target_ulong +helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return (int32_t)helper_be_lduw_mmu(env, addr, oi, retaddr); +} + +/* + * Store Helpers + */ + +static void store_helper(CPUArchState *env, target_ulong addr, uint64_t va= l, + TCGMemOpIdx oi, uintptr_t retaddr, size_t size, + bool big_endian) +{ + uintptr_t mmu_idx =3D get_mmuidx(oi); + uintptr_t index =3D tlb_index(env, mmu_idx, addr); + CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); + target_ulong tlb_addr =3D tlb_addr_write(entry); + unsigned a_bits =3D get_alignment_bits(get_memop(oi)); + uintptr_t haddr; + + /* Handle CPU specific unaligned behaviour */ + if (addr & ((1 << a_bits) - 1)) { + cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE, + mmu_idx, retaddr); + } + + /* If the TLB entry is for a different page, reload and try again. */ + if (!tlb_hit(tlb_addr, addr)) { + if (!VICTIM_TLB_HIT(addr_write, addr)) { + tlb_fill(ENV_GET_CPU(env), addr, size, MMU_DATA_STORE, + mmu_idx, retaddr); + index =3D tlb_index(env, mmu_idx, addr); + entry =3D tlb_entry(env, mmu_idx, addr); + } + tlb_addr =3D tlb_addr_write(entry) & ~TLB_INVALID_MASK; + } + + /* Handle an IO access. */ + if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { + CPUIOTLBEntry *iotlbentry =3D &env->iotlb[mmu_idx][index]; + + if ((addr & (size - 1)) !=3D 0) { + goto do_unaligned_access; + } + + io_writex(env, iotlbentry, mmu_idx, + handle_bswap(val, size, big_endian), + addr, retaddr, tlb_addr & TLB_RECHECK, size); + return; + } + + /* Handle slow unaligned access (it spans two pages or IO). */ + if (size > 1 + && unlikely((addr & ~TARGET_PAGE_MASK) + size - 1 + >=3D TARGET_PAGE_SIZE)) { + int i; + uintptr_t index2; + CPUTLBEntry *entry2; + target_ulong page2, tlb_addr2; + do_unaligned_access: + /* + * Ensure the second page is in the TLB. Note that the first page + * is already guaranteed to be filled, and that the second page + * cannot evict the first. + */ + page2 =3D (addr + size) & TARGET_PAGE_MASK; + index2 =3D tlb_index(env, mmu_idx, page2); + entry2 =3D tlb_entry(env, mmu_idx, index2); + tlb_addr2 =3D tlb_addr_write(entry2); + if (!tlb_hit_page(tlb_addr2, page2) + && !VICTIM_TLB_HIT(addr_write, page2)) { + tlb_fill(ENV_GET_CPU(env), page2, size, MMU_DATA_STORE, + mmu_idx, retaddr); + index2 =3D tlb_index(env, mmu_idx, page2); + entry2 =3D tlb_entry(env, mmu_idx, index2); + } + + /* + * XXX: not efficient, but simple. + * This loop must go in the forward direction to avoid issues + * with self-modifying code in Windows 64-bit. + */ + for (i =3D 0; i < size; ++i) { + uint8_t val8; + if (big_endian) { + /* Big-endian extract. */ + val8 =3D val >> (((size - 1) * 8) - (i * 8)); + } else { + /* Little-endian extract. */ + val8 =3D val >> (i * 8); + } + store_helper(env, addr + i, val8, oi, retaddr, 1, big_endian); + } + return; + } + + haddr =3D addr + entry->addend; + + switch (size) { + case 1: + stb_p((uint8_t *)haddr, val); + break; + case 2: + if (big_endian) { + stw_be_p((uint8_t *)haddr, val); + } else { + stw_le_p((uint8_t *)haddr, val); + } + break; + case 4: + if (big_endian) { + stl_be_p((uint8_t *)haddr, val); + } else { + stl_le_p((uint8_t *)haddr, val); + } + break; + case 8: + if (big_endian) { + stq_be_p((uint8_t *)haddr, val); + } else { + stq_le_p((uint8_t *)haddr, val); + } + break; + default: + g_assert_not_reached(); + break; + } +} + +void __attribute__((flatten)) +helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + store_helper(env, addr, val, oi, retaddr, 1, false); +} + +void __attribute__((flatten)) +helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + store_helper(env, addr, val, oi, retaddr, 2, false); +} + +void __attribute__((flatten)) +helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + store_helper(env, addr, val, oi, retaddr, 2, true); +} + +void __attribute__((flatten)) +helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + store_helper(env, addr, val, oi, retaddr, 4, false); +} + +void __attribute__((flatten)) +helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + store_helper(env, addr, val, oi, retaddr, 4, true); +} + +void __attribute__((flatten)) +helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + store_helper(env, addr, val, oi, retaddr, 8, false); +} + +void __attribute__((flatten)) +helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + store_helper(env, addr, val, oi, retaddr, 8, true); +} =20 /* First set of helpers allows passing in of OI and RETADDR. This makes them callable from other helpers. */ @@ -1247,20 +1647,51 @@ static void *atomic_mmu_lookup(CPUArchState *env, t= arget_ulong addr, =20 /* Code access functions. */ =20 -#undef MMUSUFFIX -#define MMUSUFFIX _cmmu -#undef GETPC -#define GETPC() ((uintptr_t)0) -#define SOFTMMU_CODE_ACCESS +uint8_t __attribute__((flatten)) +helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 1, false, true); +} =20 -#define DATA_SIZE 1 -#include "softmmu_template.h" +uint16_t __attribute__((flatten)) +helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 2, false, true); +} =20 -#define DATA_SIZE 2 -#include "softmmu_template.h" +uint16_t __attribute__((flatten)) +helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 2, true, true); +} =20 -#define DATA_SIZE 4 -#include "softmmu_template.h" +uint32_t __attribute__((flatten)) +helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 4, false, true); +} =20 -#define DATA_SIZE 8 -#include "softmmu_template.h" +uint32_t __attribute__((flatten)) +helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 4, true, true); +} + +uint64_t __attribute__((flatten)) +helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 8, false, true); +} + +uint64_t __attribute__((flatten)) +helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, oi, retaddr, 8, true, true); +} --=20 2.20.1 From nobody Wed May 1 14:10:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1550241218408962.8905040887314; Fri, 15 Feb 2019 06:33:38 -0800 (PST) Received: from localhost ([127.0.0.1]:40847 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gueYZ-0000Zq-6q for importer@patchew.org; Fri, 15 Feb 2019 09:33:35 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59182) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gueWQ-0007qK-Rq for qemu-devel@nongnu.org; Fri, 15 Feb 2019 09:31:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gueWN-0000C8-Rj for qemu-devel@nongnu.org; Fri, 15 Feb 2019 09:31:22 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:52736) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gueWN-0000Ay-6i for qemu-devel@nongnu.org; Fri, 15 Feb 2019 09:31:19 -0500 Received: by mail-wm1-x32a.google.com with SMTP id m1so10165129wml.2 for ; Fri, 15 Feb 2019 06:31:19 -0800 (PST) Received: from zen.linaroharston ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id t18sm5502094wmt.35.2019.02.15.06.31.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 15 Feb 2019 06:31:15 -0800 (PST) Received: from zen.linaroharston. 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X-Received-From: 2a00:1450:4864:20::32a Subject: [Qemu-devel] [PATCH v3 2/3] accel/tcg: remove softmmu_template.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , cota@braap.org, mark.cave-ayland@ilande.co.uk Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Signed-off-by: Alex Benn=C3=A9e --- accel/tcg/softmmu_template.h | 454 ----------------------------------- 1 file changed, 454 deletions(-) delete mode 100644 accel/tcg/softmmu_template.h diff --git a/accel/tcg/softmmu_template.h b/accel/tcg/softmmu_template.h deleted file mode 100644 index e970a8b378..0000000000 --- a/accel/tcg/softmmu_template.h +++ /dev/null @@ -1,454 +0,0 @@ -/* - * Software MMU support - * - * Generate helpers used by TCG for qemu_ld/st ops and code load - * functions. - * - * Included from target op helpers and exec.c. - * - * Copyright (c) 2003 Fabrice Bellard - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ -#if DATA_SIZE =3D=3D 8 -#define SUFFIX q -#define LSUFFIX q -#define SDATA_TYPE int64_t -#define DATA_TYPE uint64_t -#elif DATA_SIZE =3D=3D 4 -#define SUFFIX l -#define LSUFFIX l -#define SDATA_TYPE int32_t -#define DATA_TYPE uint32_t -#elif DATA_SIZE =3D=3D 2 -#define SUFFIX w -#define LSUFFIX uw -#define SDATA_TYPE int16_t -#define DATA_TYPE uint16_t -#elif DATA_SIZE =3D=3D 1 -#define SUFFIX b -#define LSUFFIX ub -#define SDATA_TYPE int8_t -#define DATA_TYPE uint8_t -#else -#error unsupported data size -#endif - - -/* For the benefit of TCG generated code, we want to avoid the complication - of ABI-specific return type promotion and always return a value extended - to the register size of the host. This is tcg_target_long, except in t= he - case of a 32-bit host and 64-bit data, and for that we always have - uint64_t. Don't bother with this widened value for SOFTMMU_CODE_ACCESS= . */ -#if defined(SOFTMMU_CODE_ACCESS) || DATA_SIZE =3D=3D 8 -# define WORD_TYPE DATA_TYPE -# define USUFFIX SUFFIX -#else -# define WORD_TYPE tcg_target_ulong -# define USUFFIX glue(u, SUFFIX) -# define SSUFFIX glue(s, SUFFIX) -#endif - -#ifdef SOFTMMU_CODE_ACCESS -#define READ_ACCESS_TYPE MMU_INST_FETCH -#define ADDR_READ addr_code -#else -#define READ_ACCESS_TYPE MMU_DATA_LOAD -#define ADDR_READ addr_read -#endif - -#if DATA_SIZE =3D=3D 8 -# define BSWAP(X) bswap64(X) -#elif DATA_SIZE =3D=3D 4 -# define BSWAP(X) bswap32(X) -#elif DATA_SIZE =3D=3D 2 -# define BSWAP(X) bswap16(X) -#else -# define BSWAP(X) (X) -#endif - -#if DATA_SIZE =3D=3D 1 -# define helper_le_ld_name glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX) -# define helper_be_ld_name helper_le_ld_name -# define helper_le_lds_name glue(glue(helper_ret_ld, SSUFFIX), MMUSUFFIX) -# define helper_be_lds_name helper_le_lds_name -# define helper_le_st_name glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX) -# define helper_be_st_name helper_le_st_name -#else -# define helper_le_ld_name glue(glue(helper_le_ld, USUFFIX), MMUSUFFIX) -# define helper_be_ld_name glue(glue(helper_be_ld, USUFFIX), MMUSUFFIX) -# define helper_le_lds_name glue(glue(helper_le_ld, SSUFFIX), MMUSUFFIX) -# define helper_be_lds_name glue(glue(helper_be_ld, SSUFFIX), MMUSUFFIX) -# define helper_le_st_name glue(glue(helper_le_st, SUFFIX), MMUSUFFIX) -# define helper_be_st_name glue(glue(helper_be_st, SUFFIX), MMUSUFFIX) -#endif - -#ifndef SOFTMMU_CODE_ACCESS -static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env, - size_t mmu_idx, size_t index, - target_ulong addr, - uintptr_t retaddr, - bool recheck, - MMUAccessType access_type) -{ - CPUIOTLBEntry *iotlbentry =3D &env->iotlb[mmu_idx][index]; - return io_readx(env, iotlbentry, mmu_idx, addr, retaddr, recheck, - access_type, DATA_SIZE); -} -#endif - -WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) -{ - uintptr_t mmu_idx =3D get_mmuidx(oi); - uintptr_t index =3D tlb_index(env, mmu_idx, addr); - CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); - target_ulong tlb_addr =3D entry->ADDR_READ; - unsigned a_bits =3D get_alignment_bits(get_memop(oi)); - uintptr_t haddr; - DATA_TYPE res; - - if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE, - mmu_idx, retaddr); - } - - /* If the TLB entry is for a different page, reload and try again. */ - if (!tlb_hit(tlb_addr, addr)) { - if (!VICTIM_TLB_HIT(ADDR_READ, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, READ_ACCESS_TYPE, - mmu_idx, retaddr); - index =3D tlb_index(env, mmu_idx, addr); - entry =3D tlb_entry(env, mmu_idx, addr); - } - tlb_addr =3D entry->ADDR_READ; - } - - /* Handle an IO access. */ - if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - if ((addr & (DATA_SIZE - 1)) !=3D 0) { - goto do_unaligned_access; - } - - /* ??? Note that the io helpers always read data in the target - byte ordering. We should push the LE/BE request down into io. = */ - res =3D glue(io_read, SUFFIX)(env, mmu_idx, index, addr, retaddr, - tlb_addr & TLB_RECHECK, - READ_ACCESS_TYPE); - res =3D TGT_LE(res); - return res; - } - - /* Handle slow unaligned access (it spans two pages or IO). */ - if (DATA_SIZE > 1 - && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1 - >=3D TARGET_PAGE_SIZE)) { - target_ulong addr1, addr2; - DATA_TYPE res1, res2; - unsigned shift; - do_unaligned_access: - addr1 =3D addr & ~(DATA_SIZE - 1); - addr2 =3D addr1 + DATA_SIZE; - res1 =3D helper_le_ld_name(env, addr1, oi, retaddr); - res2 =3D helper_le_ld_name(env, addr2, oi, retaddr); - shift =3D (addr & (DATA_SIZE - 1)) * 8; - - /* Little-endian combine. */ - res =3D (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift)); - return res; - } - - haddr =3D addr + entry->addend; -#if DATA_SIZE =3D=3D 1 - res =3D glue(glue(ld, LSUFFIX), _p)((uint8_t *)haddr); -#else - res =3D glue(glue(ld, LSUFFIX), _le_p)((uint8_t *)haddr); -#endif - return res; -} - -#if DATA_SIZE > 1 -WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) -{ - uintptr_t mmu_idx =3D get_mmuidx(oi); - uintptr_t index =3D tlb_index(env, mmu_idx, addr); - CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); - target_ulong tlb_addr =3D entry->ADDR_READ; - unsigned a_bits =3D get_alignment_bits(get_memop(oi)); - uintptr_t haddr; - DATA_TYPE res; - - if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE, - mmu_idx, retaddr); - } - - /* If the TLB entry is for a different page, reload and try again. */ - if (!tlb_hit(tlb_addr, addr)) { - if (!VICTIM_TLB_HIT(ADDR_READ, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, READ_ACCESS_TYPE, - mmu_idx, retaddr); - index =3D tlb_index(env, mmu_idx, addr); - entry =3D tlb_entry(env, mmu_idx, addr); - } - tlb_addr =3D entry->ADDR_READ; - } - - /* Handle an IO access. */ - if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - if ((addr & (DATA_SIZE - 1)) !=3D 0) { - goto do_unaligned_access; - } - - /* ??? Note that the io helpers always read data in the target - byte ordering. We should push the LE/BE request down into io. = */ - res =3D glue(io_read, SUFFIX)(env, mmu_idx, index, addr, retaddr, - tlb_addr & TLB_RECHECK, - READ_ACCESS_TYPE); - res =3D TGT_BE(res); - return res; - } - - /* Handle slow unaligned access (it spans two pages or IO). */ - if (DATA_SIZE > 1 - && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1 - >=3D TARGET_PAGE_SIZE)) { - target_ulong addr1, addr2; - DATA_TYPE res1, res2; - unsigned shift; - do_unaligned_access: - addr1 =3D addr & ~(DATA_SIZE - 1); - addr2 =3D addr1 + DATA_SIZE; - res1 =3D helper_be_ld_name(env, addr1, oi, retaddr); - res2 =3D helper_be_ld_name(env, addr2, oi, retaddr); - shift =3D (addr & (DATA_SIZE - 1)) * 8; - - /* Big-endian combine. */ - res =3D (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift)); - return res; - } - - haddr =3D addr + entry->addend; - res =3D glue(glue(ld, LSUFFIX), _be_p)((uint8_t *)haddr); - return res; -} -#endif /* DATA_SIZE > 1 */ - -#ifndef SOFTMMU_CODE_ACCESS - -/* Provide signed versions of the load routines as well. We can of course - avoid this for 64-bit data, or for 32-bit data on 32-bit host. */ -#if DATA_SIZE * 8 < TCG_TARGET_REG_BITS -WORD_TYPE helper_le_lds_name(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) -{ - return (SDATA_TYPE)helper_le_ld_name(env, addr, oi, retaddr); -} - -# if DATA_SIZE > 1 -WORD_TYPE helper_be_lds_name(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) -{ - return (SDATA_TYPE)helper_be_ld_name(env, addr, oi, retaddr); -} -# endif -#endif - -static inline void glue(io_write, SUFFIX)(CPUArchState *env, - size_t mmu_idx, size_t index, - DATA_TYPE val, - target_ulong addr, - uintptr_t retaddr, - bool recheck) -{ - CPUIOTLBEntry *iotlbentry =3D &env->iotlb[mmu_idx][index]; - return io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr, - recheck, DATA_SIZE); -} - -void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, - TCGMemOpIdx oi, uintptr_t retaddr) -{ - uintptr_t mmu_idx =3D get_mmuidx(oi); - uintptr_t index =3D tlb_index(env, mmu_idx, addr); - CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); - target_ulong tlb_addr =3D tlb_addr_write(entry); - unsigned a_bits =3D get_alignment_bits(get_memop(oi)); - uintptr_t haddr; - - if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE, - mmu_idx, retaddr); - } - - /* If the TLB entry is for a different page, reload and try again. */ - if (!tlb_hit(tlb_addr, addr)) { - if (!VICTIM_TLB_HIT(addr_write, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, MMU_DATA_STORE, - mmu_idx, retaddr); - index =3D tlb_index(env, mmu_idx, addr); - entry =3D tlb_entry(env, mmu_idx, addr); - } - tlb_addr =3D tlb_addr_write(entry) & ~TLB_INVALID_MASK; - } - - /* Handle an IO access. */ - if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - if ((addr & (DATA_SIZE - 1)) !=3D 0) { - goto do_unaligned_access; - } - - /* ??? Note that the io helpers always read data in the target - byte ordering. We should push the LE/BE request down into io. = */ - val =3D TGT_LE(val); - glue(io_write, SUFFIX)(env, mmu_idx, index, val, addr, - retaddr, tlb_addr & TLB_RECHECK); - return; - } - - /* Handle slow unaligned access (it spans two pages or IO). */ - if (DATA_SIZE > 1 - && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1 - >=3D TARGET_PAGE_SIZE)) { - int i; - target_ulong page2; - CPUTLBEntry *entry2; - do_unaligned_access: - /* Ensure the second page is in the TLB. Note that the first page - is already guaranteed to be filled, and that the second page - cannot evict the first. */ - page2 =3D (addr + DATA_SIZE) & TARGET_PAGE_MASK; - entry2 =3D tlb_entry(env, mmu_idx, page2); - if (!tlb_hit_page(tlb_addr_write(entry2), page2) - && !VICTIM_TLB_HIT(addr_write, page2)) { - tlb_fill(ENV_GET_CPU(env), page2, DATA_SIZE, MMU_DATA_STORE, - mmu_idx, retaddr); - } - - /* XXX: not efficient, but simple. */ - /* This loop must go in the forward direction to avoid issues - with self-modifying code in Windows 64-bit. */ - for (i =3D 0; i < DATA_SIZE; ++i) { - /* Little-endian extract. */ - uint8_t val8 =3D val >> (i * 8); - glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8, - oi, retaddr); - } - return; - } - - haddr =3D addr + entry->addend; -#if DATA_SIZE =3D=3D 1 - glue(glue(st, SUFFIX), _p)((uint8_t *)haddr, val); -#else - glue(glue(st, SUFFIX), _le_p)((uint8_t *)haddr, val); -#endif -} - -#if DATA_SIZE > 1 -void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, - TCGMemOpIdx oi, uintptr_t retaddr) -{ - uintptr_t mmu_idx =3D get_mmuidx(oi); - uintptr_t index =3D tlb_index(env, mmu_idx, addr); - CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); - target_ulong tlb_addr =3D tlb_addr_write(entry); - unsigned a_bits =3D get_alignment_bits(get_memop(oi)); - uintptr_t haddr; - - if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE, - mmu_idx, retaddr); - } - - /* If the TLB entry is for a different page, reload and try again. */ - if (!tlb_hit(tlb_addr, addr)) { - if (!VICTIM_TLB_HIT(addr_write, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, MMU_DATA_STORE, - mmu_idx, retaddr); - index =3D tlb_index(env, mmu_idx, addr); - entry =3D tlb_entry(env, mmu_idx, addr); - } - tlb_addr =3D tlb_addr_write(entry) & ~TLB_INVALID_MASK; - } - - /* Handle an IO access. */ - if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - if ((addr & (DATA_SIZE - 1)) !=3D 0) { - goto do_unaligned_access; - } - - /* ??? Note that the io helpers always read data in the target - byte ordering. We should push the LE/BE request down into io. = */ - val =3D TGT_BE(val); - glue(io_write, SUFFIX)(env, mmu_idx, index, val, addr, retaddr, - tlb_addr & TLB_RECHECK); - return; - } - - /* Handle slow unaligned access (it spans two pages or IO). */ - if (DATA_SIZE > 1 - && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1 - >=3D TARGET_PAGE_SIZE)) { - int i; - target_ulong page2; - CPUTLBEntry *entry2; - do_unaligned_access: - /* Ensure the second page is in the TLB. Note that the first page - is already guaranteed to be filled, and that the second page - cannot evict the first. */ - page2 =3D (addr + DATA_SIZE) & TARGET_PAGE_MASK; - entry2 =3D tlb_entry(env, mmu_idx, page2); - if (!tlb_hit_page(tlb_addr_write(entry2), page2) - && !VICTIM_TLB_HIT(addr_write, page2)) { - tlb_fill(ENV_GET_CPU(env), page2, DATA_SIZE, MMU_DATA_STORE, - mmu_idx, retaddr); - } - - /* XXX: not efficient, but simple */ - /* This loop must go in the forward direction to avoid issues - with self-modifying code. */ - for (i =3D 0; i < DATA_SIZE; ++i) { - /* Big-endian extract. */ - uint8_t val8 =3D val >> (((DATA_SIZE - 1) * 8) - (i * 8)); - glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8, - oi, retaddr); - } - return; - } - - haddr =3D addr + entry->addend; - glue(glue(st, SUFFIX), _be_p)((uint8_t *)haddr, val); -} -#endif /* DATA_SIZE > 1 */ -#endif /* !defined(SOFTMMU_CODE_ACCESS) */ - -#undef READ_ACCESS_TYPE -#undef DATA_TYPE -#undef SUFFIX -#undef LSUFFIX -#undef DATA_SIZE -#undef ADDR_READ -#undef WORD_TYPE -#undef SDATA_TYPE -#undef USUFFIX -#undef SSUFFIX -#undef BSWAP -#undef helper_le_ld_name -#undef helper_be_ld_name -#undef helper_le_lds_name -#undef helper_be_lds_name -#undef helper_le_st_name -#undef helper_be_st_name --=20 2.20.1 From nobody Wed May 1 14:10:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1550241353760752.4086344776939; Fri, 15 Feb 2019 06:35:53 -0800 (PST) Received: from localhost ([127.0.0.1]:40886 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gueak-0002Gt-MK for importer@patchew.org; Fri, 15 Feb 2019 09:35:50 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59185) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gueWQ-0007qM-SQ for qemu-devel@nongnu.org; Fri, 15 Feb 2019 09:31:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gueWO-0000DR-JP for qemu-devel@nongnu.org; Fri, 15 Feb 2019 09:31:22 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:55252) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gueWN-0000Bh-Up for qemu-devel@nongnu.org; Fri, 15 Feb 2019 09:31:20 -0500 Received: by mail-wm1-x32a.google.com with SMTP id a62so10153186wmh.4 for ; Fri, 15 Feb 2019 06:31:19 -0800 (PST) Received: from zen.linaroharston ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id i192sm5902333wmg.7.2019.02.15.06.31.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 15 Feb 2019 06:31:17 -0800 (PST) Received: from zen.linaroharston. (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 6AA4A1FF86; Fri, 15 Feb 2019 14:31:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=h/QwSNZ4mgsPBoS8x2aW8GpKqB5WxTyDH3cEEHn5ZJw=; b=XrlXTb7BTrQe2+jISxgSwnRd8kwTMxa8fDvcVE1bhJ2CTA4jQS6M/m+pJBvRD3/QLr tC2OGEJaDn97k+HKC+/gKJ3JulO4fWIB2wYeUYxNVdaYH1emLIdbak9XolRfKmswkQkl pCmf2uxrP3bH+lL2r/WjRaI4I4xrBQzkdyvhwFJ69UYCQuohqUF+ZUyba4/ME1WFHgvW i2Hz5WvUKFDU+mfTFodfdlZj4iK1xdnLEdesmcBrcxOB8Zj9Qz4FBSZKAvRRfY/QE4CR NgKd65fi2UYoR3ITnoBGhCozfaP3x19ITNO74a++w/Ezm2hR4ohd/XW+J6tMwrNAKmIN yTRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=h/QwSNZ4mgsPBoS8x2aW8GpKqB5WxTyDH3cEEHn5ZJw=; b=NhFP2NJofS9sJB1HMaBgUXd4FthS08nn9KFFVUBaG+RSiccvvPlE8wysYz2/XQwBkP 6W/2trunFoPIl24OBq1UsyMmP7Y9fZq/dq2ovJqsVTr9Bd13xkqXW+44TLClwR5+wjNE Yf2ExuyUroeA7iG2J7ZX0TXuN9YgjyD7zWFU0VooEs6pIU1Ap65cseo4odiAeNJKDL/D PLHVum/EgFYVi3Rp587Vok6yTdhrRCPPwalU0T4NXxFTP1orG5jVesK/4BjjXW8gVxAA x1MajnmxQSMGifaCaYYSDsRyjEHmhERjgFEJFAfNVwfkrLCBUmyDABvU/fCrGD2VtIfz tBGA== X-Gm-Message-State: AHQUAuZzH8Ug2BlIKTkV+xD9SaNmCzuv9udyr3/cQtHASkKy6dOpyD67 KXih9xkyINlDjj/e5tlL8j17zA== X-Google-Smtp-Source: AHgI3IaczALj/183IXVQ33XHrnyG6hbIZTCJutHogIODboEVZztmMuuMDz3H9XcY8ADd5X2leCNAMA== X-Received: by 2002:a1c:be04:: with SMTP id o4mr6533773wmf.19.1550241078771; Fri, 15 Feb 2019 06:31:18 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Fri, 15 Feb 2019 14:31:15 +0000 Message-Id: <20190215143115.28777-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190215143115.28777-1-alex.bennee@linaro.org> References: <20190215143115.28777-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32a Subject: [Qemu-devel] [PATCH v3 3/3] accel/tcg: move unaligned helpers out of core helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , cota@braap.org, mark.cave-ayland@ilande.co.uk Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Using __flatten__ ends up with fairly large functions. Attempt to ameliorate this by moving the unaligned handling out of the main helper. We can now use __always_inline__ instead of __flatten__ and keep the main functions relatively small. Signed-off-by: Alex Benn=C3=A9e --- v3 - take care to mask high bits in unaligned_load_helper --- accel/tcg/cputlb.c | 200 ++++++++++++++++++++++++--------------------- 1 file changed, 109 insertions(+), 91 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 351f579fed..5f225e3623 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1206,10 +1206,47 @@ static inline uint64_t handle_bswap(uint64_t val, i= nt size, bool big_endian) * is disassembled. It shouldn't be called directly by guest code. */ =20 -static tcg_target_ulong load_helper(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr, - size_t size, bool big_endian, - bool code_read) +static inline __attribute__((__always_inline__)) +tcg_target_ulong load_helper(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr, + size_t size, bool big_endian, + bool code_read); + +static tcg_target_ulong unaligned_load_helper(CPUArchState *env, target_ul= ong addr, + TCGMemOpIdx oi, uintptr_t re= taddr, + size_t size, bool big_endian, + bool code_read) +{ + target_ulong addr1, addr2; + tcg_target_ulong res, r1, r2; + const tcg_target_ulong size_mask =3D MAKE_64BIT_MASK(0, size * 8); + unsigned shift; + + addr1 =3D addr & ~(size - 1); + addr2 =3D addr1 + size; + + r1 =3D load_helper(env, addr1, oi, retaddr, size, big_endian, code_rea= d); + r2 =3D load_helper(env, addr2, oi, retaddr, size, big_endian, code_rea= d); + shift =3D (addr & (size - 1)) * 8; + + if (big_endian) { + /* Big-endian combine. */ + r2 &=3D size_mask; + res =3D (r1 << shift) | (r2 >> ((size * 8) - shift)); + } else { + /* Little-endian combine. */ + r1 &=3D size_mask; + res =3D (r1 >> shift) | (r2 << ((size * 8) - shift)); + } + return res; +} + + +static inline __attribute__((__always_inline__)) +tcg_target_ulong load_helper(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr, + size_t size, bool big_endian, + bool code_read) { uintptr_t mmu_idx =3D get_mmuidx(oi); uintptr_t index =3D tlb_index(env, mmu_idx, addr); @@ -1247,7 +1284,8 @@ static tcg_target_ulong load_helper(CPUArchState *env= , target_ulong addr, uint64_t tmp; =20 if ((addr & (size - 1)) !=3D 0) { - goto do_unaligned_access; + return unaligned_load_helper(env, addr, oi, retaddr, + size, big_endian, code_read); } =20 tmp =3D io_readx(env, iotlbentry, mmu_idx, addr, retaddr, @@ -1260,24 +1298,9 @@ static tcg_target_ulong load_helper(CPUArchState *en= v, target_ulong addr, if (size > 1 && unlikely((addr & ~TARGET_PAGE_MASK) + size - 1 >=3D TARGET_PAGE_SIZE)) { - target_ulong addr1, addr2; - tcg_target_ulong r1, r2; - unsigned shift; - do_unaligned_access: - addr1 =3D addr & ~(size - 1); - addr2 =3D addr1 + size; - r1 =3D load_helper(env, addr1, oi, retaddr, size, big_endian, code= _read); - r2 =3D load_helper(env, addr2, oi, retaddr, size, big_endian, code= _read); - shift =3D (addr & (size - 1)) * 8; =20 - if (big_endian) { - /* Big-endian combine. */ - res =3D (r1 << shift) | (r2 >> ((size * 8) - shift)); - } else { - /* Little-endian combine. */ - res =3D (r1 >> shift) | (r2 << ((size * 8) - shift)); - } - return res; + return unaligned_load_helper(env, addr, oi, retaddr, + size, big_endian, code_read); } =20 haddr =3D addr + entry->addend; @@ -1325,50 +1348,49 @@ static tcg_target_ulong load_helper(CPUArchState *e= nv, target_ulong addr, * We don't bother with this widened value for SOFTMMU_CODE_ACCESS. */ =20 -tcg_target_ulong __attribute__((flatten)) +tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 1, false, false); } =20 -tcg_target_ulong __attribute__((flatten)) +tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 2, false, false); } =20 -tcg_target_ulong __attribute__((flatten)) +tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 2, true, false); } =20 -tcg_target_ulong __attribute__((flatten)) +tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 4, false, false); } =20 -tcg_target_ulong __attribute__((flatten)) +tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 4, true, false); } =20 -uint64_t __attribute__((flatten)) -helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, + +uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, TCGMemOpI= dx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 8, false, false); } =20 -uint64_t __attribute__((flatten)) -helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, +uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, TCGMemOpI= dx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 8, true, false); @@ -1379,22 +1401,21 @@ helper_be_ldq_mmu(CPUArchState *env, target_ulong a= ddr, TCGMemOpIdx oi, * avoid this for 64-bit data, or for 32-bit data on 32-bit host. */ =20 - -tcg_target_ulong __attribute__((flatten)) +tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { return (int8_t)helper_ret_ldub_mmu(env, addr, oi, retaddr); } =20 -tcg_target_ulong __attribute__((flatten)) +tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { return (int16_t)helper_le_lduw_mmu(env, addr, oi, retaddr); } =20 -tcg_target_ulong __attribute__((flatten)) +tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { @@ -1418,10 +1439,43 @@ helper_be_ldsl_mmu(CPUArchState *env, target_ulong = addr, TCGMemOpIdx oi, /* * Store Helpers */ +static inline __attribute__((__always_inline__)) +void store_helper(CPUArchState *env, target_ulong addr, uint64_t val, + TCGMemOpIdx oi, uintptr_t retaddr, size_t size, + bool big_endian); =20 -static void store_helper(CPUArchState *env, target_ulong addr, uint64_t va= l, - TCGMemOpIdx oi, uintptr_t retaddr, size_t size, - bool big_endian) + +static void +unaligned_store_helper(CPUArchState *env, target_ulong addr, uint64_t val, + TCGMemOpIdx oi, uintptr_t retaddr, size_t size, + bool big_endian) +{ + int i; + + /* + * This is inefficient but simple and hopefully on the slow path + * anyway. The loop must go in the forward direction to avoid + * issues with self-modifying code in Windows 64-bit. + */ + for (i =3D 0; i < size; ++i) { + uint8_t val8; + if (big_endian) { + /* Big-endian extract. */ + val8 =3D val >> (((size - 1) * 8) - (i * 8)); + } else { + /* Little-endian extract. */ + val8 =3D val >> (i * 8); + } + store_helper(env, addr + i, val8, oi, retaddr, 1, big_endian); + } + return; +} + + +static inline __attribute__((__always_inline__)) +void store_helper(CPUArchState *env, target_ulong addr, uint64_t val, + TCGMemOpIdx oi, uintptr_t retaddr, size_t size, + bool big_endian) { uintptr_t mmu_idx =3D get_mmuidx(oi); uintptr_t index =3D tlb_index(env, mmu_idx, addr); @@ -1452,7 +1506,8 @@ static void store_helper(CPUArchState *env, target_ul= ong addr, uint64_t val, CPUIOTLBEntry *iotlbentry =3D &env->iotlb[mmu_idx][index]; =20 if ((addr & (size - 1)) !=3D 0) { - goto do_unaligned_access; + unaligned_store_helper(env, addr, val, oi, retaddr, size, big_= endian); + return; } =20 io_writex(env, iotlbentry, mmu_idx, @@ -1465,44 +1520,7 @@ static void store_helper(CPUArchState *env, target_u= long addr, uint64_t val, if (size > 1 && unlikely((addr & ~TARGET_PAGE_MASK) + size - 1 >=3D TARGET_PAGE_SIZE)) { - int i; - uintptr_t index2; - CPUTLBEntry *entry2; - target_ulong page2, tlb_addr2; - do_unaligned_access: - /* - * Ensure the second page is in the TLB. Note that the first page - * is already guaranteed to be filled, and that the second page - * cannot evict the first. - */ - page2 =3D (addr + size) & TARGET_PAGE_MASK; - index2 =3D tlb_index(env, mmu_idx, page2); - entry2 =3D tlb_entry(env, mmu_idx, index2); - tlb_addr2 =3D tlb_addr_write(entry2); - if (!tlb_hit_page(tlb_addr2, page2) - && !VICTIM_TLB_HIT(addr_write, page2)) { - tlb_fill(ENV_GET_CPU(env), page2, size, MMU_DATA_STORE, - mmu_idx, retaddr); - index2 =3D tlb_index(env, mmu_idx, page2); - entry2 =3D tlb_entry(env, mmu_idx, index2); - } - - /* - * XXX: not efficient, but simple. - * This loop must go in the forward direction to avoid issues - * with self-modifying code in Windows 64-bit. - */ - for (i =3D 0; i < size; ++i) { - uint8_t val8; - if (big_endian) { - /* Big-endian extract. */ - val8 =3D val >> (((size - 1) * 8) - (i * 8)); - } else { - /* Little-endian extract. */ - val8 =3D val >> (i * 8); - } - store_helper(env, addr + i, val8, oi, retaddr, 1, big_endian); - } + unaligned_store_helper(env, addr, val, oi, retaddr, size, big_endi= an); return; } =20 @@ -1539,49 +1557,49 @@ static void store_helper(CPUArchState *env, target_= ulong addr, uint64_t val, } } =20 -void __attribute__((flatten)) +void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, TCGMemOpIdx oi, uintptr_t retaddr) { store_helper(env, addr, val, oi, retaddr, 1, false); } =20 -void __attribute__((flatten)) +void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, TCGMemOpIdx oi, uintptr_t retaddr) { store_helper(env, addr, val, oi, retaddr, 2, false); } =20 -void __attribute__((flatten)) +void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, TCGMemOpIdx oi, uintptr_t retaddr) { store_helper(env, addr, val, oi, retaddr, 2, true); } =20 -void __attribute__((flatten)) +void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, TCGMemOpIdx oi, uintptr_t retaddr) { store_helper(env, addr, val, oi, retaddr, 4, false); } =20 -void __attribute__((flatten)) +void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, TCGMemOpIdx oi, uintptr_t retaddr) { store_helper(env, addr, val, oi, retaddr, 4, true); } =20 -void __attribute__((flatten)) +void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, TCGMemOpIdx oi, uintptr_t retaddr) { store_helper(env, addr, val, oi, retaddr, 8, false); } =20 -void __attribute__((flatten)) +void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, TCGMemOpIdx oi, uintptr_t retaddr) { @@ -1647,49 +1665,49 @@ helper_be_stq_mmu(CPUArchState *env, target_ulong a= ddr, uint64_t val, =20 /* Code access functions. */ =20 -uint8_t __attribute__((flatten)) +uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 1, false, true); } =20 -uint16_t __attribute__((flatten)) +uint16_t helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 2, false, true); } =20 -uint16_t __attribute__((flatten)) +uint16_t helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 2, true, true); } =20 -uint32_t __attribute__((flatten)) +uint32_t helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 4, false, true); } =20 -uint32_t __attribute__((flatten)) +uint32_t helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 4, true, true); } =20 -uint64_t __attribute__((flatten)) +uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { return load_helper(env, addr, oi, retaddr, 8, false, true); } =20 -uint64_t __attribute__((flatten)) +uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { --=20 2.20.1