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v2: drop a couple of RTH's patches that he wants to rework. The following changes since commit 0266c739abbed804deabb4ccde2aa449466ac3b4: Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-feb-14-2019' into staging (2019-02-14 18:33:00 +0000) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190215 for you to fetch changes up to 0f8b09b22234460cb5b8766a25066cf6b5f06842: gdbstub: Send a reply to the vKill packet. (2019-02-15 09:56:41 +0000) ---------------------------------------------------------------- target-arm queue: * gdbstub: Send a reply to the vKill packet * Improve codegen for neon min/max and saturating arithmetic * Fix a bug in clearing FPSCR exception status bits * hw/arm/armsse: Fix miswiring of expansion IRQs * hw/intc/armv7m_nvic: Allow byte accesses to SHPR1 * MAINTAINERS: Remove Peter Crosthwaite from various entries * arm: Allow system registers for KVM guests to be changed by QEMU code * linux-user: support HWCAP_CPUID which exposes ID registers to user code * Fix bug in 128-bit cmpxchg for BE Arm guests * Implement (no-op) HACR_EL2 * Fix CRn to be 14 for PMEVTYPER/PMEVCNTR ---------------------------------------------------------------- Aaron Lindsay OS (1): target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR Alex Bennée (5): target/arm: relax permission checks for HWCAP_CPUID registers target/arm: expose CPUID registers to userspace target/arm: expose MPIDR_EL1 to userspace target/arm: expose remaining CPUID registers as RAZ linux-user/elfload: enable HWCAP_CPUID for AArch64 Catherine Ho (1): target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be Peter Maydell (5): target/arm: Implement HACR_EL2 arm: Allow system registers for KVM guests to be changed by QEMU code MAINTAINERS: Remove Peter Crosthwaite from various entries hw/intc/armv7m_nvic: Allow byte accesses to SHPR1 hw/arm/armsse: Fix miswiring of expansion IRQs Richard Henderson (12): target/arm: Rely on optimization within tcg_gen_gvec_or target/arm: Use vector minmax expanders for aarch64 target/arm: Use vector minmax expanders for aarch32 target/arm: Use tcg integer min/max primitives for neon target/arm: Remove neon min/max helpers target/arm: Fix vfp_gdb_get/set_reg vs FPSCR target/arm: Fix arm_cpu_dump_state vs FPSCR target/arm: Split out flags setting from vfp compares target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR] target/arm: Split out FPSCR.QC to a vector field target/arm: Use vector operations for saturation target/arm: Add missing clear_tail calls Sandra Loosemore (1): gdbstub: Send a reply to the vKill packet. target/arm/cpu.h | 50 +++++++++- target/arm/helper.h | 45 ++++++--- target/arm/translate.h | 4 + gdbstub.c | 1 + hw/arm/armsse.c | 2 +- hw/intc/armv7m_nvic.c | 4 +- linux-user/elfload.c | 1 + target/arm/helper-a64.c | 4 +- target/arm/helper.c | 228 ++++++++++++++++++++++++++++++++++++--------- target/arm/kvm32.c | 20 +--- target/arm/kvm64.c | 2 + target/arm/machine.c | 2 +- target/arm/neon_helper.c | 14 +-- target/arm/translate-a64.c | 77 ++++++--------- target/arm/translate-sve.c | 6 +- target/arm/translate.c | 219 ++++++++++++++++++++++++++++++++++--------- target/arm/vec_helper.c | 134 +++++++++++++++++++++++++- MAINTAINERS | 4 - 18 files changed, 622 insertions(+), 195 deletions(-)
v3->v4: Windows headers define an INT type which clashed with an enum value name in arm_gicv3_its.c... The following changes since commit eae587e8e3694b1aceab23239493fb4c7e1a80f5: Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-09-13' into staging (2021-09-13 11:00:30 +0100) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210913-3 for you to fetch changes up to 28e987a7e7edaa3ca7feeac65edca26145df8814: hw/arm/mps2.c: Mark internal-only I2C buses as 'full' (2021-09-13 21:01:08 +0100) ---------------------------------------------------------------- target-arm queue: * mark MPS2/MPS3 board-internal i2c buses as 'full' so that command line user-created devices are not plugged into them * Take an exception if PSTATE.IL is set * Support an emulated ITS in the virt board * Add support for kudo-bmc board * Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM * cadence_uart: Fix clock handling issues that prevented u-boot from running ---------------------------------------------------------------- Bin Meng (6): hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phase hw/char: cadence_uart: Disable transmit when input clock is disabled hw/char: cadence_uart: Move clock/reset check to uart_can_receive() hw/char: cadence_uart: Convert to memop_with_attrs() ops hw/char: cadence_uart: Ignore access when unclocked or in reset for uart_{read, write}() hw/char: cadence_uart: Log a guest error when device is unclocked or in reset Chris Rauer (1): hw/arm: Add support for kudo-bmc board. Marc Zyngier (1): hw/arm/virt: KVM: Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM Peter Maydell (5): target/arm: Take an exception if PSTATE.IL is set qdev: Support marking individual buses as 'full' hw/arm/mps2-tz.c: Add extra data parameter to MakeDevFn hw/arm/mps2-tz.c: Mark internal-only I2C buses as 'full' hw/arm/mps2.c: Mark internal-only I2C buses as 'full' Richard Henderson (1): target/arm: Merge disas_a64_insn into aarch64_tr_translate_insn Shashi Mallela (9): hw/intc: GICv3 ITS initial framework hw/intc: GICv3 ITS register definitions added hw/intc: GICv3 ITS command queue framework hw/intc: GICv3 ITS Command processing hw/intc: GICv3 ITS Feature enablement hw/intc: GICv3 redistributor ITS processing tests/data/acpi/virt: Add IORT files for ITS hw/arm/virt: add ITS support in virt GIC tests/data/acpi/virt: Update IORT files for ITS docs/system/arm/nuvoton.rst | 1 + hw/intc/gicv3_internal.h | 188 ++++- include/hw/arm/virt.h | 2 + include/hw/intc/arm_gicv3_common.h | 13 + include/hw/intc/arm_gicv3_its_common.h | 32 +- include/hw/qdev-core.h | 24 + target/arm/cpu.h | 1 + target/arm/kvm_arm.h | 4 +- target/arm/syndrome.h | 5 + target/arm/translate.h | 2 + hw/arm/mps2-tz.c | 92 ++- hw/arm/mps2.c | 12 +- hw/arm/npcm7xx_boards.c | 34 + hw/arm/virt.c | 29 +- hw/char/cadence_uart.c | 61 +- hw/intc/arm_gicv3.c | 14 + hw/intc/arm_gicv3_common.c | 13 + hw/intc/arm_gicv3_cpuif.c | 7 +- hw/intc/arm_gicv3_dist.c | 5 +- hw/intc/arm_gicv3_its.c | 1322 ++++++++++++++++++++++++++++++++ hw/intc/arm_gicv3_its_common.c | 7 +- hw/intc/arm_gicv3_its_kvm.c | 2 +- hw/intc/arm_gicv3_redist.c | 153 +++- hw/misc/zynq_slcr.c | 31 +- softmmu/qdev-monitor.c | 7 +- target/arm/helper-a64.c | 1 + target/arm/helper.c | 8 + target/arm/kvm.c | 7 +- target/arm/translate-a64.c | 255 +++--- target/arm/translate.c | 21 + hw/intc/meson.build | 1 + tests/data/acpi/virt/IORT | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.memhp | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.numamem | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.pxb | Bin 0 -> 124 bytes 35 files changed, 2144 insertions(+), 210 deletions(-) create mode 100644 hw/intc/arm_gicv3_its.c create mode 100644 tests/data/acpi/virt/IORT create mode 100644 tests/data/acpi/virt/IORT.memhp create mode 100644 tests/data/acpi/virt/IORT.numamem create mode 100644 tests/data/acpi/virt/IORT.pxb