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[2001:470:27:1fa::2]) by smtp.gmail.com with ESMTPSA id h123sm172384lfh.26.2019.02.14.15.01.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Feb 2019 15:01:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rzvpWlHArW/bEyQbhniakJouRLXjPEcmRViiSqQt5ag=; b=SG0z+qO9j77nJzUpDXazIAEiGdCm5yKhybIsYinjwmtB8zb87Ha1E4h+i6Z5dxdhaZ KsfqaspCcyR4gcKUzGoCORjIGa5b3W5+84AkHBOqD57UVkrXGzmPc6qDwbHLiq6Bgzsh SU4S8TCQdZNP5yqrnYpE0QcK1h4DbXf1dZk6VeZIoyzP+HGAgzdBFVXCxzk1bUun5hXm QZSdM9kLUrLiVeaG/rfaPtG04fbZ8GUv5z+OG8An7dQjzl+eQdAkH39TTqXyRTimRT05 yL7Ekbw6ItiutBw2JhPCrA2tmpLXfisg9CidiO/cPkFCRPqIKE73Jp8IGdyVa1MZlT0P H96Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rzvpWlHArW/bEyQbhniakJouRLXjPEcmRViiSqQt5ag=; b=JevnKumCpOBz7C1MyFWEkhXcHX0fmLcrNsnNIQvxnUyeYha0IXM/hMR0n8VY2WzEma JI0oTDGAARQ9MMjr3CasEwqPB0R4xTx9gs5mIWT1YEIAdz6FAyIfO1zajlwErhRNQAAo Hj6jT93ZstFrF+SsikO6rffvB1sxUHN0VY6t4ZU1NfxynuTCO8B0BzNeRGBLaxXWqH7/ xgI1V7RY/Qwob+Rr9o/yVZLb7CJdPWBULU01XoZesspvDxGPWy5yVW0bTVZ5ObsRPlKe 91xh7krL5R/EslPQ68nWyz+zBtnOPEUIUdd7gtrDfTelII4e6nwTOkoK7QtqTQlroULI zllA== X-Gm-Message-State: AHQUAubu8gaqmc0XyRuikjpaMsMKOt4cHpbOEQwHE954d22H0ZpU1Xlc Vg4WHR/dXh5PcXvSFA8doV6Va5ApK90= X-Google-Smtp-Source: AHgI3IYAc4VXZR4iOGcanjtwWFvlMI72PTBqpfehV1kaO+P1U7LQCBZ+PMS2P6T3oEbeirdhCxJ6fA== X-Received: by 2002:ac2:43c6:: with SMTP id u6mr3871759lfl.102.1550185265527; Thu, 14 Feb 2019 15:01:05 -0800 (PST) From: Max Filippov To: qemu-devel@nongnu.org Date: Thu, 14 Feb 2019 14:59:58 -0800 Message-Id: <20190214230000.24894-12-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190214230000.24894-1-jcmvbkbc@gmail.com> References: <20190214230000.24894-1-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::143 Subject: [Qemu-devel] [PATCH 11/13] target/xtensa: reorganize access to boolean registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" libisa represents boolean registers b0..b16 as a BR register file and as BR4 and BR8 register groups. Add these register files and use OpcodeArg::{in,out} parameters to access boolean registers in translators. Signed-off-by: Max Filippov --- target/xtensa/translate.c | 50 +++++++++++++++++++++++++++++++++++++++----= ---- 1 file changed, 42 insertions(+), 8 deletions(-) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 065e3d01427b..276b435ce81e 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -80,6 +80,9 @@ static TCGv_i32 cpu_pc; static TCGv_i32 cpu_R[16]; static TCGv_i32 cpu_FR[16]; static TCGv_i32 cpu_MR[4]; +static TCGv_i32 cpu_BR[16]; +static TCGv_i32 cpu_BR4[4]; +static TCGv_i32 cpu_BR8[2]; static TCGv_i32 cpu_SR[256]; static TCGv_i32 cpu_UR[256]; static TCGv_i32 cpu_windowbase_next; @@ -227,6 +230,12 @@ void xtensa_translate_init(void) static const char * const mregnames[] =3D { "m0", "m1", "m2", "m3", }; + static const char * const bregnames[] =3D { + "b0", "b1", "b2", "b3", + "b4", "b5", "b6", "b7", + "b8", "b9", "b10", "b11", + "b12", "b13", "b14", "b15", + }; int i; =20 cpu_pc =3D tcg_global_mem_new_i32(cpu_env, @@ -252,6 +261,25 @@ void xtensa_translate_init(void) mregnames[i]); } =20 + for (i =3D 0; i < 16; i++) { + cpu_BR[i] =3D tcg_global_mem_new_i32(cpu_env, + offsetof(CPUXtensaState, + sregs[BR]), + bregnames[i]); + if (i % 4 =3D=3D 0) { + cpu_BR4[i / 4] =3D tcg_global_mem_new_i32(cpu_env, + offsetof(CPUXtensaStat= e, + sregs[BR]), + bregnames[i]); + } + if (i % 8 =3D=3D 0) { + cpu_BR8[i / 8] =3D tcg_global_mem_new_i32(cpu_env, + offsetof(CPUXtensaStat= e, + sregs[BR]), + bregnames[i]); + } + } + for (i =3D 0; i < 256; ++i) { if (sregnames[i].name) { cpu_SR[i] =3D tcg_global_mem_new_i32(cpu_env, @@ -284,6 +312,12 @@ void **xtensa_get_regfile_by_name(const char *name) (void *)"MR", (void *)cpu_MR); g_hash_table_insert(xtensa_regfile_table, (void *)"FR", (void *)cpu_FR); + g_hash_table_insert(xtensa_regfile_table, + (void *)"BR", (void *)cpu_BR); + g_hash_table_insert(xtensa_regfile_table, + (void *)"BR4", (void *)cpu_BR4); + g_hash_table_insert(xtensa_regfile_table, + (void *)"BR8", (void *)cpu_BR8); } return (void **)g_hash_table_lookup(xtensa_regfile_table, (void *)name= ); } @@ -1583,14 +1617,14 @@ static void translate_all(DisasContext *dc, const O= pcodeArg arg[], TCGv_i32 mask =3D tcg_const_i32(((1 << shift) - 1) << arg[1].imm); TCGv_i32 tmp =3D tcg_temp_new_i32(); =20 - tcg_gen_and_i32(tmp, cpu_SR[BR], mask); + tcg_gen_and_i32(tmp, arg[1].in, mask); if (par[0]) { tcg_gen_addi_i32(tmp, tmp, 1 << arg[1].imm); } else { tcg_gen_add_i32(tmp, tmp, mask); } tcg_gen_shri_i32(tmp, tmp, arg[1].imm + shift); - tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], + tcg_gen_deposit_i32(arg[0].out, arg[0].out, tmp, arg[0].imm, 1); tcg_temp_free(mask); tcg_temp_free(tmp); @@ -1694,10 +1728,10 @@ static void translate_boolean(DisasContext *dc, con= st OpcodeArg arg[], TCGv_i32 tmp1 =3D tcg_temp_new_i32(); TCGv_i32 tmp2 =3D tcg_temp_new_i32(); =20 - tcg_gen_shri_i32(tmp1, cpu_SR[BR], arg[1].imm); - tcg_gen_shri_i32(tmp2, cpu_SR[BR], arg[2].imm); + tcg_gen_shri_i32(tmp1, arg[1].in, arg[1].imm); + tcg_gen_shri_i32(tmp2, arg[2].in, arg[2].imm); op[par[0]](tmp1, tmp1, tmp2); - tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, arg[0].imm, 1); + tcg_gen_deposit_i32(arg[0].out, arg[0].out, tmp1, arg[0].imm, 1); tcg_temp_free(tmp1); tcg_temp_free(tmp2); } @@ -1707,7 +1741,7 @@ static void translate_bp(DisasContext *dc, const Opco= deArg arg[], { TCGv_i32 tmp =3D tcg_temp_new_i32(); =20 - tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[0].imm); + tcg_gen_andi_i32(tmp, arg[0].in, 1 << arg[0].imm); gen_brcondi(dc, par[0], tmp, 0, arg[1].imm); tcg_temp_free(tmp); } @@ -2074,7 +2108,7 @@ static void translate_movp(DisasContext *dc, const Op= codeArg arg[], TCGv_i32 zero =3D tcg_const_i32(0); TCGv_i32 tmp =3D tcg_temp_new_i32(); =20 - tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[2].imm); + tcg_gen_andi_i32(tmp, arg[2].in, 1 << arg[2].imm); tcg_gen_movcond_i32(par[0], arg[0].out, tmp, zero, arg[1].in, arg[0].in); @@ -5296,7 +5330,7 @@ static void translate_movp_s(DisasContext *dc, const = OpcodeArg arg[], TCGv_i32 zero =3D tcg_const_i32(0); TCGv_i32 tmp =3D tcg_temp_new_i32(); =20 - tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[2].imm); + tcg_gen_andi_i32(tmp, arg[2].in, 1 << arg[2].imm); tcg_gen_movcond_i32(par[0], arg[0].out, tmp, zero, arg[1].in, arg[0].in); --=20 2.11.0