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X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v3 3/3] target/arm: Implement ARMv8.3-JSConv X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- v2: Return 0 for NaN v3: Return aa32 flags in FPSCR.NZCV. --- target/arm/cpu.h | 10 +++++ target/arm/helper.h | 3 ++ target/arm/cpu.c | 1 + target/arm/cpu64.c | 2 + target/arm/translate-a64.c | 26 +++++++++++ target/arm/translate.c | 10 +++++ target/arm/vfp_helper.c | 88 ++++++++++++++++++++++++++++++++++++++ 7 files changed, 140 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b96463e8f1..dbed7a74b4 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3230,6 +3230,11 @@ static inline bool isar_feature_aa32_vcma(const ARMI= SARegisters *id) return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) !=3D 0; } =20 +static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) !=3D 0; +} + static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) { return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) !=3D 0; @@ -3308,6 +3313,11 @@ static inline bool isar_feature_aa64_dp(const ARMISA= Registers *id) return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) !=3D 0; } =20 +static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) !=3D 0; +} + static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) !=3D 0; diff --git a/target/arm/helper.h b/target/arm/helper.h index 923e8e1525..747cb64d29 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -218,6 +218,9 @@ DEF_HELPER_FLAGS_2(rintd_exact, TCG_CALL_NO_RWG, f64, f= 64, ptr) DEF_HELPER_FLAGS_2(rints, TCG_CALL_NO_RWG, f32, f32, ptr) DEF_HELPER_FLAGS_2(rintd, TCG_CALL_NO_RWG, f64, f64, ptr) =20 +DEF_HELPER_FLAGS_2(vjcvt, TCG_CALL_NO_RWG, i32, f64, env) +DEF_HELPER_FLAGS_2(fjcvtzs, TCG_CALL_NO_RWG, i64, f64, ptr) + /* neon_helper.c */ DEF_HELPER_FLAGS_3(neon_qadd_u8, TCG_CALL_NO_RWG, i32, env, i32, i32) DEF_HELPER_FLAGS_3(neon_qadd_s8, TCG_CALL_NO_RWG, i32, env, i32, i32) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index edf6e0e1f1..8ea6569088 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2001,6 +2001,7 @@ static void arm_max_initfn(Object *obj) cpu->isar.id_isar5 =3D t; =20 t =3D cpu->isar.id_isar6; + t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); cpu->isar.id_isar6 =3D t; =20 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index eff0f164dd..69e4134f79 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -311,6 +311,7 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_aa64isar0 =3D t; =20 t =3D cpu->isar.id_aa64isar1; + t =3D FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); t =3D FIELD_DP64(t, ID_AA64ISAR1, APA, 1); /* PAuth, architected o= nly */ t =3D FIELD_DP64(t, ID_AA64ISAR1, API, 0); @@ -344,6 +345,7 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_isar5 =3D u; =20 u =3D cpu->isar.id_isar6; + u =3D FIELD_DP32(u, ID_ISAR6, JSCVT, 1); u =3D FIELD_DP32(u, ID_ISAR6, DP, 1); cpu->isar.id_isar6 =3D u; =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index dbce24fe32..c56e878787 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -6526,6 +6526,24 @@ static void handle_fmov(DisasContext *s, int rd, int= rn, int type, bool itof) } } =20 +static void handle_fjcvtzs(DisasContext *s, int rd, int rn) +{ + TCGv_i64 t =3D read_fp_dreg(s, rn); + TCGv_ptr fpstatus =3D get_fpstatus_ptr(false); + + gen_helper_fjcvtzs(t, t, fpstatus); + + tcg_temp_free_ptr(fpstatus); + + tcg_gen_ext32u_i64(cpu_reg(s, rd), t); + tcg_gen_extrh_i64_i32(cpu_ZF, t); + tcg_gen_movi_i32(cpu_CF, 0); + tcg_gen_movi_i32(cpu_NF, 0); + tcg_gen_movi_i32(cpu_VF, 0); + + tcg_temp_free_i64(t); +} + /* Floating point <-> integer conversions * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4= 0 * +----+---+---+-----------+------+---+-------+-----+-------------+----+-= ---+ @@ -6601,6 +6619,14 @@ static void disas_fp_int_conv(DisasContext *s, uint3= 2_t insn) handle_fmov(s, rd, rn, type, itof); break; =20 + case 0b00111110: /* FJCVTZS */ + if (!dc_isar_feature(aa64_jscvt, s)) { + goto do_unallocated; + } else if (fp_access_check(s)) { + handle_fjcvtzs(s, rd, rn); + } + break; + default: do_unallocated: unallocated_encoding(s); diff --git a/target/arm/translate.c b/target/arm/translate.c index 64c5fe0df3..c1175798ac 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3718,6 +3718,13 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) rm_is_dp =3D false; break; =20 + case 0x13: /* vjcvt */ + if (!dp || !dc_isar_feature(aa32_jscvt, s)) { + return 1; + } + rd_is_dp =3D false; + break; + default: return 1; } @@ -4088,6 +4095,9 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) case 17: /* fsito */ gen_vfp_sito(dp, 0); break; + case 19: /* vjcvt */ + gen_helper_vjcvt(cpu_F0s, cpu_F0d, cpu_env); + break; case 20: /* fshto */ gen_vfp_shto(dp, 16 - rm, 0); break; diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 74d3030c47..f19c0606c2 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -1086,3 +1086,91 @@ int arm_rmode_to_sf(int rmode) } return rmode; } + +/* + * Implement float64 to int32_t conversion without saturation; + * the result is supplied modulo 2^32. + */ +uint64_t HELPER(fjcvtzs)(float64 value, void *vstatus) +{ + float_status *status =3D vstatus; + uint32_t exp, sign; + uint64_t frac; + uint32_t inexact =3D 1; /* !Z */ + + sign =3D extract64(value, 63, 1); + exp =3D extract64(value, 52, 11); + frac =3D extract64(value, 0, 52); + + if (exp =3D=3D 0) { + /* While not inexact for IEEE FP, -0.0 is inexact for JavaScript. = */ + inexact =3D sign; + if (frac !=3D 0) { + if (status->flush_inputs_to_zero) { + float_raise(float_flag_input_denormal, status); + } else { + float_raise(float_flag_inexact, status); + inexact =3D 1; + } + } + frac =3D 0; + } else if (exp =3D=3D 0x7ff) { + /* This operation raises Invalid for both NaN and overflow (Inf). = */ + float_raise(float_flag_invalid, status); + frac =3D 0; + } else { + int true_exp =3D exp - 1023; + int shift =3D true_exp - 52; + + /* Restore implicit bit. */ + frac |=3D 1ull << 52; + + /* Shift the fraction into place. */ + if (shift >=3D 0) { + /* The number is so large we must shift the fraction left. */ + if (shift >=3D 64) { + /* The the fraction is shifted out entirely. */ + frac =3D 0; + } else { + frac <<=3D shift; + } + } else if (shift > -64) { + /* Normal case -- shift right and notice if bits shift out. */ + inexact =3D (frac << (64 + shift)) !=3D 0; + frac >>=3D -shift; + } else { + /* The fraction is shifted out entirely. */ + frac =3D 0; + } + + /* Notice overflow or inexact exceptions. */ + if (true_exp > 31 || frac > (sign ? 0x80000000ull : 0x7fffffff)) { + /* Overflow, for which this operation raises invalid. */ + float_raise(float_flag_invalid, status); + inexact =3D 1; + } else if (inexact) { + float_raise(float_flag_inexact, status); + } + + /* Honor the sign. */ + if (sign) { + frac =3D -frac; + } + } + + /* Pack the result and the env->ZF representation of Z together. */ + return deposit64(frac, 32, 32, inexact); +} + +uint32_t HELPER(vjcvt)(float64 value, CPUARMState *env) +{ + uint64_t pair =3D HELPER(fjcvtzs)(value, &env->vfp.fp_status); + uint32_t result =3D pair; + uint32_t z =3D (pair >> 32) =3D=3D 0; + + /* Store Z, clear NCV, in FPSCR.NZCF. */ + env->vfp.xregs[ARM_VFP_FPSCR] + =3D (env->vfp.xregs[ARM_VFP_FPSCR] & ~CPSR_NZCV) | (z * CPSR_Z); + + return result; +} --=20 2.17.2