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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n184sm7798471wmf.5.2019.02.14.11.06.12 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Feb 2019 11:06:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=lZfKwSdGUuGpFg4aTqYEBeTE57fpYvGiIwxpL69KCVo=; b=Xvb+dDkAyEQcN/ykxas4RYWBAou+Ozx2EhttNb2fLHsLPulKbdC62cqj4acyNb8PEk V2PGzwKnT+WbI8p2E02KMxPIsRDLeAtW2+IH5xLK9KIF95j8n9y4ki101Orxe5SACeaV nLFVOMxUzV6J4/a5/ZnhEmGq14WIYNFsrYmyDISFJOBsy0jEY0zUr4mazhxzpxa2K18p tgXN8+F4r40cE05IEuG73MF8b0iTeE2AWVBRNuYJiG5Dnebb5X/CvUfVEkeFQ15dIaQG Gl05pj+KB3VodK59ocjv3dNRlKfsNoNU+N3sOAzeFqsv4fOKJMSKHLyBYJr2afJTEboI mBxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lZfKwSdGUuGpFg4aTqYEBeTE57fpYvGiIwxpL69KCVo=; b=IoBYDf1z4ao/7kr71Qo3zEFiuYFiLiVvsYkOtzXqV/rLzqG21lkpHvP6wQU2okKffe Sdnrded4h7E4psOC1MDjioPFzdY9O5DHEsm4eKRSLfF81eW62xTsPNbr3grhUWQiMfGE Ec6qj6dht4fluZza9S5yK34Q+84zYd4BUmmX2kJl968cMh6K+OaTTUmGo9Qkn+hbglld 67c2pBJ6XPPAOOL/C8JiCKuRIk8xWff7Q3U+JN/MUjLvZCh43Xj7J4UxX55FDIMUOapT JWqRSEhFoAioN851V4AhzLB+/ue+OQwW8IHFz9m/YAdRd4HP4maZR2o9fT+Ut/u9CIc5 UbgQ== X-Gm-Message-State: AHQUAuZPgvkDAXqNaLoooy1hM3MMDmHr03hj99QfxhcuU8hf2YOSjviP h+pKw1zfnH6EI8K/3lImdrlt4WMqfzKTUg== X-Google-Smtp-Source: AHgI3IbCPrejLhqIUkqN2LliPZRP+TCYpEgk0FsCO2kTzKAcaQkPWoM8fcn2ffQVEi1Fx36BuD/WSw== X-Received: by 2002:adf:d845:: with SMTP id k5mr4039014wrl.145.1550171173673; Thu, 14 Feb 2019 11:06:13 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Feb 2019 19:05:43 +0000 Message-Id: <20190214190603.25030-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190214190603.25030-1-peter.maydell@linaro.org> References: <20190214190603.25030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PULL 07/27] target/arm: expose CPUID registers to userspace X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Alex Benn=C3=A9e A number of CPUID registers are exposed to userspace by modern Linux kernels thanks to the "ARM64 CPU Feature Registers" ABI. For QEMU's user-mode emulation we don't need to emulate the kernels trap but just return the value the trap would have done. To avoid too much #ifdef hackery we process ARMCPRegInfo with a new helper (modify_arm_cp_regs) before defining the registers. The modify routine is driven by a simple data structure which describes which bits are exported and which are fixed. Signed-off-by: Alex Benn=C3=A9e Message-id: 20190205190224.2198-3-alex.bennee@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 21 ++++++++++++++++ target/arm/helper.c | 59 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 80 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c92c097b449..7c31e5a2d10 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2464,6 +2464,27 @@ static inline void define_one_arm_cp_reg(ARMCPU *cpu= , const ARMCPRegInfo *regs) } const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encode= d_cp); =20 +/* + * Definition of an ARM co-processor register as viewed from + * userspace. This is used for presenting sanitised versions of + * registers to userspace when emulating the Linux AArch64 CPU + * ID/feature ABI (advertised as HWCAP_CPUID). + */ +typedef struct ARMCPRegUserSpaceInfo { + /* Name of register */ + const char *name; + + /* Only some bits are exported to user space */ + uint64_t exported_bits; + + /* Fixed bits are applied after the mask */ + uint64_t fixed_bits; +} ARMCPRegUserSpaceInfo; + +#define REGUSERINFO_SENTINEL { .name =3D NULL } + +void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *m= ods); + /* CPWriteFn that can be used to implement writes-ignored behaviour */ void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value); diff --git a/target/arm/helper.c b/target/arm/helper.c index 88cf4976039..b2abaf5b225 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6109,6 +6109,30 @@ void register_cp_regs_for_features(ARMCPU *cpu) .resetvalue =3D cpu->pmceid1 }, REGINFO_SENTINEL }; +#ifdef CONFIG_USER_ONLY + ARMCPRegUserSpaceInfo v8_user_idregs[] =3D { + { .name =3D "ID_AA64PFR0_EL1", + .exported_bits =3D 0x000f000f00ff0000, + .fixed_bits =3D 0x0000000000000011 }, + { .name =3D "ID_AA64PFR1_EL1", + .exported_bits =3D 0x00000000000000f0 }, + { .name =3D "ID_AA64ZFR0_EL1" }, + { .name =3D "ID_AA64MMFR0_EL1", + .fixed_bits =3D 0x00000000ff000000 }, + { .name =3D "ID_AA64MMFR1_EL1" }, + { .name =3D "ID_AA64DFR0_EL1", + .fixed_bits =3D 0x0000000000000006 }, + { .name =3D "ID_AA64DFR1_EL1" }, + { .name =3D "ID_AA64AFR0_EL1" }, + { .name =3D "ID_AA64AFR1_EL1" }, + { .name =3D "ID_AA64ISAR0_EL1", + .exported_bits =3D 0x00fffffff0fffff0 }, + { .name =3D "ID_AA64ISAR1_EL1", + .exported_bits =3D 0x000000f0ffffffff }, + REGUSERINFO_SENTINEL + }; + modify_arm_cp_regs(v8_idregs, v8_user_idregs); +#endif /* RVBAR_EL1 is only implemented if EL1 is the highest EL */ if (!arm_feature(env, ARM_FEATURE_EL3) && !arm_feature(env, ARM_FEATURE_EL2)) { @@ -6385,6 +6409,15 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_W, .type =3D ARM_CP_NOP | ARM_CP_OVERRIDE }; +#ifdef CONFIG_USER_ONLY + ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] =3D { + { .name =3D "MIDR_EL1", + .exported_bits =3D 0x00000000ffffffff }, + { .name =3D "REVIDR_EL1" }, + REGUSERINFO_SENTINEL + }; + modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_regin= fo); +#endif if (arm_feature(env, ARM_FEATURE_OMAPCP) || arm_feature(env, ARM_FEATURE_STRONGARM)) { ARMCPRegInfo *r; @@ -6966,6 +6999,32 @@ void define_arm_cp_regs_with_opaque(ARMCPU *cpu, } } =20 +/* + * Modify ARMCPRegInfo for access from userspace. + * + * This is a data driven modification directed by + * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as + * user-space cannot alter any values and dynamic values pertaining to + * execution state are hidden from user space view anyway. + */ +void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *m= ods) +{ + const ARMCPRegUserSpaceInfo *m; + ARMCPRegInfo *r; + + for (m =3D mods; m->name; m++) { + for (r =3D regs; r->type !=3D ARM_CP_SENTINEL; r++) { + if (strcmp(r->name, m->name) =3D=3D 0) { + r->type =3D ARM_CP_CONST; + r->access =3D PL0U_R; + r->resetvalue &=3D m->exported_bits; + r->resetvalue |=3D m->fixed_bits; + break; + } + } + } +} + const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encode= d_cp) { return g_hash_table_lookup(cpregs, &encoded_cp); --=20 2.20.1