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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n184sm7798471wmf.5.2019.02.14.11.06.11 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Feb 2019 11:06:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=MLWTlAGA+UoWxGz/xEJXz3ZE6B8T7D9aiFqsuj678Eg=; b=KggvhIUBhRhDEP+voeu3ylp1GtlJMYsK2QxxO0rD8AaRYtNSMGiQFqJk2VzxXA52Fl U8DoXZYje0KeOzeDMXLwcvIUahiLUPYD3zeIgsXJ2wybvUBc9HeZ+snracmXNgJr1kBF IQCzABYAnnep87h4NZlD0y4D9oxen3O0Dd0a7j8nZ3z88+4OgcG+aZws4Fv7+ly4XpWZ f+QDIekp1bd3q1SLJ4c5ANkLOVh8rf8vE9qQs1qAwxUd/TBJNu++r7WXbTj5WJ8+mP6c nBeAyamJJSuLaL+TSmzLzhL0nJOfSNi84XUUtKSIni7HKKKfojIrmWVj6NZpwcAVJGXp ho2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MLWTlAGA+UoWxGz/xEJXz3ZE6B8T7D9aiFqsuj678Eg=; b=iVZY0wCRcfyBwFNlJTrW8qVBDcGLhFZDAAXska6EkAM0QJL0Ub+G6eUva2xHBwQrUh eH2ISc0mUi4xfj3bQoBZ69Ko32u8Ax9rG7bzbpyImG8AeBxtbMf9fP1bmygGBOMmPBRF z1LCiGRLzaZTSMrnA7zfdJpWX1+zLNqO5K8RLiHDNmAT4ZlFpqIxIuSr74fxrPgC4j+O KXFYUJg4BGvUugICDb7NwdWcP64p0q/qa9RHbjjGLgBJRv3qeICk1CieXH9bW7+I2a8z eHTKGIKQ3vlGINME6qI937cc7KtfHooOk/X4nvi1P1DW7NKHQ1CTtRj1gWo1PGeYdpTe mXNQ== X-Gm-Message-State: AHQUAuZGSfd9xR6bhP/F/b9wNHY7CUwhZXAgMoLrr1amJB3pIiZtEnLX p0fOn0xYidLwYuRisVE0A6mS4BKYIDfJww== X-Google-Smtp-Source: AHgI3IZGGk7YNv/MEWifjp7smoss3QzqXAPRo5QcBmDplgUQF00bytw58GJAFKgedDagGKtEeRZstQ== X-Received: by 2002:a5d:620d:: with SMTP id y13mr3993996wru.119.1550171172537; Thu, 14 Feb 2019 11:06:12 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Feb 2019 19:05:42 +0000 Message-Id: <20190214190603.25030-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190214190603.25030-1-peter.maydell@linaro.org> References: <20190214190603.25030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PULL 06/27] target/arm: relax permission checks for HWCAP_CPUID registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Alex Benn=C3=A9e Although technically not visible to userspace the kernel does make them visible via a trap and emulate ABI. We provide a new permission mask (PL0U_R) which maps to PL0_R for CONFIG_USER builds and adjust the minimum permission check accordingly. Signed-off-by: Alex Benn=C3=A9e Message-id: 20190205190224.2198-2-alex.bennee@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 12 ++++++++++++ target/arm/helper.c | 6 +++++- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 47238e42458..c92c097b449 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2226,6 +2226,18 @@ static inline bool cptype_valid(int cptype) #define PL0_R (0x02 | PL1_R) #define PL0_W (0x01 | PL1_W) =20 +/* + * For user-mode some registers are accessible to EL0 via a kernel + * trap-and-emulate ABI. In this case we define the read permissions + * as actually being PL0_R. However some bits of any given register + * may still be masked. + */ +#ifdef CONFIG_USER_ONLY +#define PL0U_R PL0_R +#else +#define PL0U_R PL1_R +#endif + #define PL3_RW (PL3_R | PL3_W) #define PL2_RW (PL2_R | PL2_W) #define PL1_RW (PL1_R | PL1_W) diff --git a/target/arm/helper.c b/target/arm/helper.c index e1ef2f35237..88cf4976039 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6857,7 +6857,11 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, if (r->state !=3D ARM_CP_STATE_AA32) { int mask =3D 0; switch (r->opc1) { - case 0: case 1: case 2: + case 0: + /* min_EL EL1, but some accessible to EL0 via kernel ABI */ + mask =3D PL0U_R | PL1_RW; + break; + case 1: case 2: /* min_EL EL1 */ mask =3D PL1_RW; break; --=20 2.20.1