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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n184sm7798471wmf.5.2019.02.14.11.06.14 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Feb 2019 11:06:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=5j4rXGjVgvY3s9QkcEZduEdu+tbGw8yHEbDdy7Si5QE=; b=pfnAb1nRpZVYeHZYxxF8h+EJrYGjJzW9Hntp9m21lY/aT89TlnbyMkDdRfgpNGu0q9 rfkLvmuTVxaFRNiiD7rKOK/T+ZN7a7KMZSizcePgRPCB/0LZhCfjumWcwBeOSzDOtQzo IHqIY9Q7j83uD4beyrq8iBsiwRemUQmyJucxLQnlai0NXiWks6BzHdl2Y6tLVlhQ47Sl 4yrvJ+klzF8hra4UKahTILyI/24IIYKIJUdYzjKbxcQ/bFLMUjPUQp5OJyokPs5fMJ6N 2IHMpBkVpfXqsMlroVgoOpmYGTywb/0M5SknIAqbLet8cmwDNAXRRcEuQUXJq3hQOO9j HIIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5j4rXGjVgvY3s9QkcEZduEdu+tbGw8yHEbDdy7Si5QE=; b=KFX9Lc/cxN3nLr82pgaNOPznTeMrO8MOod0B8ACV5KVkikzJw98v6IVza6lV//mrI4 sKYAZ4kpiATlIlrfZDfB2kMcomDOImzlz+QrFszIYxmgmPHt17YYIPmDmwVIoGJp17Gi BMbowkbhSVsUZrUD62r2wKE7SyJqNqNV9mlv4uJRPGUSidb5C5rFfZ+zuZnvst9tFZzJ pc6g458mN2XvHhjMayBfk1y6z+CzhBG25oO00pQ53tcZ0XIISKiVWe6zsA/8HITP7Cv+ ueHRfdEV52QEQtBGkdNd/4CmQT4apG7YDEngiPISGY/TGLp78VB45lZ60mjjPumbH6aA dyIw== X-Gm-Message-State: AHQUAuafN3BTmJlZY1vhAbPLf7MZlbrq04xK49VSnG57z+8eGY5JeOgl HdKSo6efxeBrDdZXoLC3m4cN02RI7RdS3Q== X-Google-Smtp-Source: AHgI3IZYf5MfnScLy87ur0rISnH2LVIEcqq1x+qW2UzpRXb0yBRX9NeBXoWWWmNi3SCKKatD8ma5Gg== X-Received: by 2002:a1c:1d15:: with SMTP id d21mr3570101wmd.132.1550171175897; Thu, 14 Feb 2019 11:06:15 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Feb 2019 19:05:45 +0000 Message-Id: <20190214190603.25030-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190214190603.25030-1-peter.maydell@linaro.org> References: <20190214190603.25030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PULL 09/27] target/arm: expose remaining CPUID registers as RAZ X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Alex Benn=C3=A9e There are a whole bunch more registers in the CPUID space which are currently not used but are exposed as RAZ. To avoid too much duplication we expand ARMCPRegUserSpaceInfo to understand glob patterns so we only need one entry to tweak whole ranges of registers. Signed-off-by: Alex Benn=C3=A9e Message-id: 20190205190224.2198-5-alex.bennee@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 3 +++ target/arm/helper.c | 26 +++++++++++++++++++++++--- 2 files changed, 26 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7c31e5a2d10..f0334413ece 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2474,6 +2474,9 @@ typedef struct ARMCPRegUserSpaceInfo { /* Name of register */ const char *name; =20 + /* Is the name actually a glob pattern */ + bool is_glob; + /* Only some bits are exported to user space */ uint64_t exported_bits; =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 77c73056948..5ac335f598c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6109,19 +6109,27 @@ void register_cp_regs_for_features(ARMCPU *cpu) .fixed_bits =3D 0x0000000000000011 }, { .name =3D "ID_AA64PFR1_EL1", .exported_bits =3D 0x00000000000000f0 }, + { .name =3D "ID_AA64PFR*_EL1_RESERVED", + .is_glob =3D true }, { .name =3D "ID_AA64ZFR0_EL1" }, { .name =3D "ID_AA64MMFR0_EL1", .fixed_bits =3D 0x00000000ff000000 }, { .name =3D "ID_AA64MMFR1_EL1" }, + { .name =3D "ID_AA64MMFR*_EL1_RESERVED", + .is_glob =3D true }, { .name =3D "ID_AA64DFR0_EL1", .fixed_bits =3D 0x0000000000000006 }, { .name =3D "ID_AA64DFR1_EL1" }, - { .name =3D "ID_AA64AFR0_EL1" }, - { .name =3D "ID_AA64AFR1_EL1" }, + { .name =3D "ID_AA64DFR*_EL1_RESERVED", + .is_glob =3D true }, + { .name =3D "ID_AA64AFR*", + .is_glob =3D true }, { .name =3D "ID_AA64ISAR0_EL1", .exported_bits =3D 0x00fffffff0fffff0 }, { .name =3D "ID_AA64ISAR1_EL1", .exported_bits =3D 0x000000f0ffffffff }, + { .name =3D "ID_AA64ISAR*_EL1_RESERVED", + .is_glob =3D true }, REGUSERINFO_SENTINEL }; modify_arm_cp_regs(v8_idregs, v8_user_idregs); @@ -7020,8 +7028,17 @@ void modify_arm_cp_regs(ARMCPRegInfo *regs, const AR= MCPRegUserSpaceInfo *mods) ARMCPRegInfo *r; =20 for (m =3D mods; m->name; m++) { + GPatternSpec *pat =3D NULL; + if (m->is_glob) { + pat =3D g_pattern_spec_new(m->name); + } for (r =3D regs; r->type !=3D ARM_CP_SENTINEL; r++) { - if (strcmp(r->name, m->name) =3D=3D 0) { + if (pat && g_pattern_match_string(pat, r->name)) { + r->type =3D ARM_CP_CONST; + r->access =3D PL0U_R; + r->resetvalue =3D 0; + /* continue */ + } else if (strcmp(r->name, m->name) =3D=3D 0) { r->type =3D ARM_CP_CONST; r->access =3D PL0U_R; r->resetvalue &=3D m->exported_bits; @@ -7029,6 +7046,9 @@ void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARM= CPRegUserSpaceInfo *mods) break; } } + if (pat) { + g_pattern_spec_free(pat); + } } } =20 --=20 2.20.1