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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j3sm1488073wmb.39.2019.02.14.04.51.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Feb 2019 04:51:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ebn64XdcAcwAG7W2yYJLFh5oyBBZkjhw+yyDNY3aVQc=; b=nRh++iUG3stPiTw+pdpr5Sjc6NRsdcS/YRYk0cjIkqq4Zfi7Tal2abID+yOVEzYdgH iNbYbGfRHCR5TTx3rijF8pt9ppO6nI/FLuSCYr4peXGqYtozwQUssbzabDd41yrNJkhu ZRJSDanM7B0aKLxOpO3HLGEhC77JzU0VopJ2XmXY07xmjYosGiFtQuWtrA+xfNTP74JT aStUzcmODFLCFoYquJt80HI9Ts7GCs3z82+HIVevByLPKwU50YKcrQW8Jx9Rf7nTOdzC blfuOekfCQjAaNxGxZrpPmh6Mgukw0vGVYSG4os9nBiLiXbLGdXlD7eE9k8NRb/WmduM KpCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ebn64XdcAcwAG7W2yYJLFh5oyBBZkjhw+yyDNY3aVQc=; b=izLHN41Q0D0mEiIwONsQSWe88Fcw8f/ZvW81IYK30H6yIsuGg6fLk+mZyeRKc6Qa6b 9KW97EwTnqg5laeSws4X08P0jkHVZxtHmDvonkmNr9UeI13gXY3GNx3tExSFf58p83vH vwfZSHbj4gjdnUcyfM0JG/ROt9qKXiLFgolNz47fw8Y54SWuWnJkLOyJlnjjFl6RA+dZ lgmu8c3f7/qBFo3pg0bKkzIyyzrO0muRIbHyBQCtaFOaeZkmt+smIiLuBvsmArwUvJ4M 2ly3O4T8tD91lUHivTSxeJlm3mAS+bhzTZ5uT3RaEh4qfDMWVcqeLnyQAzSWBc2rYbLQ wXBg== X-Gm-Message-State: AHQUAuYH0SF14Xkm8zkoLRN9uuo0o5aSx9YrGhNj3KhbhpYdc9Trvo45 LpXPRQHVlix4CPSnWIL+mSLP03Hr5AgnCQ== X-Google-Smtp-Source: AHgI3IbqfH2MkwEDS4ptCvGH4MLbR4fgJYO1gwMqGr0F1+hzKKmyc/TZyi8kzv9UlidNiigNA9AiBQ== X-Received: by 2002:a1c:e1c4:: with SMTP id y187mr2755729wmg.50.1550148678630; Thu, 14 Feb 2019 04:51:18 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 14 Feb 2019 12:51:01 +0000 Message-Id: <20190214125107.22178-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190214125107.22178-1-peter.maydell@linaro.org> References: <20190214125107.22178-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32c Subject: [Qemu-devel] [PATCH 08/14] hw/arm/armsse: Document SRAM_ADDR_WIDTH property in header comment X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" In commit 4b635cf7a95e501211 we added a QOM property to the ARMSSE object, but forgot to add it to the documentation comment in the header. Correct the omission. Fixes: 4b635cf7a95e501211 ("hw/arm/armsse: Make SRAM bank size configurable= ") Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/arm/armsse.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index f800bafb14a..444605b44dc 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -46,6 +46,8 @@ * being the same for both, to avoid having to have separate Property * lists for different variants. This restriction can be relaxed later * if necessary.) + * + QOM property "SRAM_ADDR_WIDTH" sets the number of bits used for the + * address of each SRAM bank (and thus the total amount of internal SRA= M) * + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CP= U 0, * which are wired to its NVIC lines 32 .. n+32 * + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts f= or --=20 2.20.1