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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j3sm1488073wmb.39.2019.02.14.04.51.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Feb 2019 04:51:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9GhcdoHkWYFQUs/bSK2K6WRQDH8DkevPHImfn8kPArY=; b=n26sLxq5Oi6VHS4zA4McrNiLy47MxTPtsjbf46p8iXp7IXVvPwXCyxaRNXouvi754D R4CMIulgR6cmE2PfuwwOy5FLa8pw2zUrEK6q2+gN+OCBVIOyC0qafM0DV6ScK16Rt6xN QOTIFAuWnAL/OQnY3iHj+m9GrlaUH86QgGfV1NGRWJvHQ4YRC7KtkK2RmBDjz7+ujyJw Q94sHUBR3iz427T5z8v9cUhP5RBe2wcf1jQQBbxSrVFQ2L+GHq2cgabPauFKJ8t1omx5 kpes/M1ERnw5FmnhpupeaErVzbGvxfdM3yhJSemVEUKa03VmoyPchiVFM/kp1u2/MNNg 4RZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9GhcdoHkWYFQUs/bSK2K6WRQDH8DkevPHImfn8kPArY=; b=gUEfmqmTeXJmhzAI6WY6nEaWj8odsb5Ju2rGnmk+XKwhQmrLbTQ/bigH5x/LsCzeQh Srh9RFdfuB6ciC+UJ4YY8oVFo32I5mFulVvwAyrzSNEkqYdRfnEQNA9iXhrydNJef+g+ pV8ZUPGxp/lyAFm9hL1z7mcvOJ/AXQuwK2bFqlnkrnBST/Fti8jeAEnzv2hE7Q9zpgej O8/2obimHb7UviZe+DdaRi5ewgzJdCrQiUkf9dGFh8BlrFyOidJfXbZ8/kcnBXDB16BI XdCZ6I6Tpv4BmM7eOnrY6wyvndqPGrhx1TMXeiDYKeOtBzAjDjcoUi5xuAzTEkujtpxv I+WA== X-Gm-Message-State: AHQUAub172aWeAQ63VwA5GA2JprDfeDaK0BMI8B+4XoTciqLynYi00BL qdoeyfj8Q2qtGjjcPnn6VxSZLA== X-Google-Smtp-Source: AHgI3IbGy/ZoEJGfKMG/A027h0ltYIan8BPnL8mJo7dGG5cMFhJc5+Enf8BjDGhXe+t/5O5iTJnZGw== X-Received: by 2002:a1c:1b4e:: with SMTP id b75mr2788355wmb.88.1550148676391; Thu, 14 Feb 2019 04:51:16 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 14 Feb 2019 12:50:59 +0000 Message-Id: <20190214125107.22178-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190214125107.22178-1-peter.maydell@linaro.org> References: <20190214125107.22178-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH 06/14] hw/char/pl011: Support all interrupt lines X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The PL011 UART has six interrupt lines: * RX (receive data) * TX (transmit data) * RT (receive timeout) * MS (modem status) * E (errors) * combined (logical OR of all the above) So far we have only emulated the combined interrupt line; add support for the others, so that boards that wire them up to different interrupt controller inputs can do so. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/char/pl011.h | 2 +- hw/char/pl011.c | 46 +++++++++++++++++++++++++++++++++++++++-- 2 files changed, 45 insertions(+), 3 deletions(-) diff --git a/include/hw/char/pl011.h b/include/hw/char/pl011.h index 1b52bfd5c90..dad3cf29121 100644 --- a/include/hw/char/pl011.h +++ b/include/hw/char/pl011.h @@ -45,7 +45,7 @@ typedef struct PL011State { int read_count; int read_trigger; CharBackend chr; - qemu_irq irq; + qemu_irq irq[6]; const unsigned char *id; } PL011State; =20 diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 0c4711e4027..29f4e5eb224 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -7,6 +7,17 @@ * This code is licensed under the GPL. */ =20 +/* + * QEMU interface: + * + sysbus MMIO region 0: device registers + * + sysbus IRQ 0: UARTINTR (combined interrupt line) + * + sysbus IRQ 1: UARTRXINTR (receive FIFO interrupt line) + * + sysbus IRQ 2: UARTTXINTR (transmit FIFO interrupt line) + * + sysbus IRQ 3: UARTRTINTR (receive timeout interrupt line) + * + sysbus IRQ 4: UARTMSINTR (momem status interrupt line) + * + sysbus IRQ 5: UARTEINTR (error interrupt line) + */ + #include "qemu/osdep.h" #include "hw/char/pl011.h" #include "hw/sysbus.h" @@ -22,18 +33,46 @@ #define PL011_FLAG_TXFF 0x20 #define PL011_FLAG_RXFE 0x10 =20 +/* Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC */ +#define INT_OE (1 << 10) +#define INT_BE (1 << 9) +#define INT_PE (1 << 8) +#define INT_FE (1 << 7) +#define INT_RT (1 << 6) +#define INT_TX (1 << 5) +#define INT_RX (1 << 4) +#define INT_DSR (1 << 3) +#define INT_DCD (1 << 2) +#define INT_CTS (1 << 1) +#define INT_RI (1 << 0) +#define INT_E (INT_OE | INT_BE | INT_PE | INT_FE) +#define INT_MS (INT_RI | INT_DSR | INT_DCD | INT_CTS) + static const unsigned char pl011_id_arm[8] =3D { 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; static const unsigned char pl011_id_luminary[8] =3D { 0x11, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 }; =20 +/* Which bits in the interrupt status matter for each outbound IRQ line ? = */ +static const uint32_t irqmask[] =3D { + INT_E | INT_MS | INT_RT | INT_TX | INT_RX, /* combined IRQ */ + INT_RX, + INT_TX, + INT_RT, + INT_MS, + INT_E, +}; + static void pl011_update(PL011State *s) { uint32_t flags; + int i; =20 flags =3D s->int_level & s->int_enabled; trace_pl011_irq_state(flags !=3D 0); - qemu_set_irq(s->irq, flags !=3D 0); + for (i =3D 0; i < ARRAY_SIZE(s->irq); i++) { + qemu_set_irq(s->irq[i], (flags & irqmask[i]) !=3D 0); + } } =20 static uint64_t pl011_read(void *opaque, hwaddr offset, @@ -284,10 +323,13 @@ static void pl011_init(Object *obj) { SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); PL011State *s =3D PL011(obj); + int i; =20 memory_region_init_io(&s->iomem, OBJECT(s), &pl011_ops, s, "pl011", 0x= 1000); sysbus_init_mmio(sbd, &s->iomem); - sysbus_init_irq(sbd, &s->irq); + for (i =3D 0; i < ARRAY_SIZE(s->irq); i++) { + sysbus_init_irq(sbd, &s->irq[i]); + } =20 s->read_trigger =3D 1; s->ifl =3D 0x12; --=20 2.20.1