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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j3sm1488073wmb.39.2019.02.14.04.51.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Feb 2019 04:51:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=i7iefvAvCVRA+KRHNYGYL+qeYUkXaEz5YcRL7tedKZY=; b=RJDEqj7j8XWkG/cMdBPF8DDTmFYF71f6ppHBCIj8blVUT3Id1IvQ9u21UvtfDavnRg Gt8RKUIkzBjMxfRVL3K7MT9sdlzsytUnYN5mXm3fHFCIBCyNw4+B5TKgsuPQDu5qPeca nOukU8K7yVbm7GlLheLXUaS5fuJRlYBWvOGrasCGPOQHUqSq23v6svgWnLe8x0gjORMl tsMRyku9uF89kg4ZBgAfv5kcLJITnnZ1VNuvXiNL4Cf6ukzZOzrB0nHR4dNsrIpfPbwE oFoaCPgJypi3mGrCb2CDJ/0IjYo5ziaNHrhqdpHxFfWney7mkk7pLNB1wPbzwmLXtuHa +kAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=i7iefvAvCVRA+KRHNYGYL+qeYUkXaEz5YcRL7tedKZY=; b=Om86H/dkVN8uHAUZtpT/BzuO40OGF+GtsXHVaC3wzgCaHM9901C2llYRLDmPYNDoeP ZQGRjRa3zSfNIqqxk+ZEA8uE9uwdCEdaW8eBWG/RpGm4OMhhDCqQyCU1SdiQasG9ohSZ jgTjTbCEEWMQ2yBvBRkB/rGtMBg5Q4HDB5iCP7FWzZE4ct+YQ3liAGoIZvZRTtTjOEnh g/T3N+kDTn3PR9mRquKt7ga4EOsUGGzewRhoAdaL7rk+Kvv2rX9FwrVlcvi7mfULxxD2 zzgy1xD1KcQPyS1dJaxcWHY5+cntDdupW3hniaixGIx7GsTUK3ANoVIzIpF0dGUeiMHi BqiA== X-Gm-Message-State: AHQUAubrJt1dQPdxsm4ATsUJc7Z7YPcMRybhRws7z06McT8E9Syb+/b8 IXUZ7pdTgdC34HHh5yha6APatw== X-Google-Smtp-Source: AHgI3IZ+FGrL2VXmlrVdLteBjBJACF4FOWCTEhLe9soyNqkqbHIniMGCTrJvQ633Z92GgMcYDmI2rQ== X-Received: by 2002:a1c:c40c:: with SMTP id u12mr2530542wmf.11.1550148679746; Thu, 14 Feb 2019 04:51:19 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 14 Feb 2019 12:51:02 +0000 Message-Id: <20190214125107.22178-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190214125107.22178-1-peter.maydell@linaro.org> References: <20190214125107.22178-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH 09/14] hw/arm/armsse: Allow boards to specify init-svtor X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The Musca boards have DAPLink firmware that sets the initial secure VTOR value (the location of the vector table) differently depending on the boot mode (from flash, from RAM, etc). Export the init-svtor as a QOM property of the ARMSSE object so that the board can change it. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/arm/armsse.h | 3 +++ hw/arm/armsse.c | 8 ++++---- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 444605b44dc..84879f40dd8 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -48,6 +48,8 @@ * if necessary.) * + QOM property "SRAM_ADDR_WIDTH" sets the number of bits used for the * address of each SRAM bank (and thus the total amount of internal SRA= M) + * + QOM property "init-svtor" sets the initial value of the CPU SVTOR re= gister + * (where it expects to load the PC and SP from the vector table on res= et) * + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CP= U 0, * which are wired to its NVIC lines 32 .. n+32 * + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts f= or @@ -204,6 +206,7 @@ typedef struct ARMSSE { uint32_t exp_numirq; uint32_t mainclk_frq; uint32_t sram_addr_width; + uint32_t init_svtor; } ARMSSE; =20 typedef struct ARMSSEInfo ARMSSEInfo; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 9a8c49547db..3040ea9324e 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -505,11 +505,10 @@ static void armsse_realize(DeviceState *dev, Error **= errp) * the INITSVTOR* registers before powering up the CPUs in any cas= e, * so the hardware's default value doesn't matter. QEMU doesn't em= ulate * the control processor, so instead we behave in the way that the - * firmware does. All boards currently known about have firmware t= hat - * sets the INITSVTOR0 and INITSVTOR1 registers to 0x10000000, lik= e the - * IoTKit default. We can make this more configurable if necessary. + * firmware does. The initial value is configurable by the board c= ode + * to match whatever its firmware does. */ - qdev_prop_set_uint32(cpudev, "init-svtor", 0x10000000); + qdev_prop_set_uint32(cpudev, "init-svtor", s->init_svtor); /* * Start all CPUs except CPU0 powered down. In real hardware it is * a configurable property of the SSE-200 which CPUs start powered= up @@ -1185,6 +1184,7 @@ static Property armsse_properties[] =3D { DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0), DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), + DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), DEFINE_PROP_END_OF_LIST() }; =20 --=20 2.20.1