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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j3sm1488073wmb.39.2019.02.14.04.51.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Feb 2019 04:51:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xO0SmjJi87cMCHBDYE6Aqyprx2bqu1BuqChTWfqFWYg=; b=jODasDd2CprkDE+SMmDJ85XKzxN4RW0kLA7p/4H/kR88P23aVkEW5u39Liy0jXgBfm 67fWPG3UMDqN+EK9ujfMGKZg3fEpDRYmtBkjfy709q8nPFE1sNzCc04I5QbIRcUkDCkT pOlOgUNYvQrH97+f8fomIEqpbkHLUQPj7DtVQ7N1haFuo2pLFkiYAYJteBfqXY3dDCUp iSqOBum1ac9DtwjksTyyRGjxg1DnS4/3K0IKfXPyydLv2kH6+w80P+Co4QfDoXqbIJKU PU8O+zIidJEx0D0qz8mdp4/xoZ2rWPdxdcUlRyDVuQXTkeMZuL8a6dZoR/SlgqIBnOJP 8BPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xO0SmjJi87cMCHBDYE6Aqyprx2bqu1BuqChTWfqFWYg=; b=rUHW4mhHHj65qt5wqOYGRRuWXkwOBSPYcums19nhdkNSZ9cZdJrcAOr9sMCyBZwQDT Kc16XqZ2s+Sf4pH9FlkfH/wdpSoSeHejSMLx8Qo5vbscZSeIFQHFQAhGcLBFKDiOcN1Z OJ9qOlcJVnmjBd2d8q9PL3bIyfH+EOcGa1T+HQXv2VJqry0DV1Z2aacQDO4U6q5XeW/x VZVuIEtvAR12pY9NMbqSg6BupA3jluT2EOdBbdwXJaLbV5/5GuPIVCrJASJhHx6h4C9W uhtZPQgDMpcyptysRBP/zKgRNNoMr2hDR2IKOfM32HT/KKVjzreW+2PgSy9KBY+c7Y3I syMQ== X-Gm-Message-State: AHQUAuZbQeHHfmBK4qvBi1MzQtaScZVv247o3020HRWRz77U+4fgJBo3 dMG5z7KBqdMw3Gu7dM1ZmzVYSQ== X-Google-Smtp-Source: AHgI3IYa4mmdjqp9q4vbOGXMjaOjY+HKEkQC3TyB6sOMiOKX7U21d9XXEvdIvDKlGJvdDRq7O2wQyw== X-Received: by 2002:a1c:6442:: with SMTP id y63mr2469483wmb.143.1550148670479; Thu, 14 Feb 2019 04:51:10 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 14 Feb 2019 12:50:54 +0000 Message-Id: <20190214125107.22178-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190214125107.22178-1-peter.maydell@linaro.org> References: <20190214125107.22178-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH 01/14] hw/arm/armsse: Fix miswiring of expansion IRQs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) In commit 91c1e9fcbd7548db368 where we added dual-CPU support to the ARMSSE, we set up the wiring of the expansion IRQs via nested loops: the outer loop on 'i' loops for each CPU, and the inner loop on 'j' loops for each interrupt. Fix a typo which meant we were wiring every expansion IRQ line to external IRQ 0 on CPU 0 and to external IRQ 1 on CPU 1. Fixes: 91c1e9fcbd7548db368 ("hw/arm/armsse: Support dual-CPU configuration") Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/arm/armsse.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 5d53071a5a0..9a8c49547db 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -565,7 +565,7 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) /* Connect EXP_IRQ/EXP_CPUn_IRQ GPIOs to the NVIC's lines 32 and u= p */ s->exp_irqs[i] =3D g_new(qemu_irq, s->exp_numirq); for (j =3D 0; j < s->exp_numirq; j++) { - s->exp_irqs[i][j] =3D qdev_get_gpio_in(cpudev, i + 32); + s->exp_irqs[i][j] =3D qdev_get_gpio_in(cpudev, j + 32); } if (i =3D=3D 0) { gpioname =3D g_strdup("EXP_IRQ"); --=20 2.20.1 From nobody Sat Nov 8 06:03:08 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1550149886163289.74923997973815; Thu, 14 Feb 2019 05:11:26 -0800 (PST) Received: from localhost ([127.0.0.1]:48390 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1guGnT-0001y5-1x for importer@patchew.org; Thu, 14 Feb 2019 08:11:23 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49935) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1guGeU-00034b-Gp for qemu-devel@nongnu.org; Thu, 14 Feb 2019 08:02:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1guGTx-0006RI-5N for qemu-devel@nongnu.org; Thu, 14 Feb 2019 07:51:14 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:53578) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1guGTw-0006QP-VO for qemu-devel@nongnu.org; Thu, 14 Feb 2019 07:51:13 -0500 Received: by mail-wm1-x343.google.com with SMTP id d15so6168294wmb.3 for ; Thu, 14 Feb 2019 04:51:12 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j3sm1488073wmb.39.2019.02.14.04.51.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Feb 2019 04:51:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vaS39ErdvakXDhjr2AJlzEtf1NZBf73g6lMHeNCY3fs=; b=OlJCJtVB2LvWDyzuPYVS8RradArrRRjjE6HjgcFad8rjTF4UWhmyhuWB4cEW3ZrMHf nY6WCwuH2wpwu2cDv4vU46aBQxcRWKL0w9D5HH4/BKcfeL8WuCF2pUFJu9FsqpEghNgt TVPZVl2hEJrkeabRX64496eRmt3fPNDw/zrIg1x+pAPPVel5jDaz+AZKWoooxWBq+uc1 dl35LdhhAt//9+vR1Ep3O6bdSwQYnWUnEyRe+GzOD20uL7mmG+ZLaIKmvKCPh/CdzPEr 1WfFEsJ4Eh2JkfpqBKbGJDnh0X5Q9jYfEHQ7ixX/XKcC8dinpqI2l85Knd5B6rCha7up B8CQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vaS39ErdvakXDhjr2AJlzEtf1NZBf73g6lMHeNCY3fs=; b=HPTMeR3v4CSWMpO5PO2FddmJDjaiEFHuF8i5g99V+5SWBNvTLD9WSUiqvtYMh7U/kp 6aGkOX7O4wLFEVupliyd5WQoBrq6JZNta6Ri20+Ywcz5sy2JeKfl4wIslSwjOOLIANcJ 18XzEll2vcnpfwbReHCx+K0bO1qRJRyfG2Fl09cDo3Vduvm/IJUArwOHblcM+95tk2da t6KXTmKDeLaAXZtfQorNFUYyw9lsMk/Y6G0w/WbPLKtKWeRzq2crbThlFRfsKpmdcHDV yjIEtoonUKKspSrWydwB69x3Eaif3qJQ8rw5QW9Ox9wnOprSfo1J32WzatK2EqbikxMq gekg== X-Gm-Message-State: AHQUAuZFE1DOd7Pbuk9Msx1FCjBSH4b0IuHPzy2syV06RKHyxP1uOLVk TBfYuQu0rjYiajl4lgTnc+mKbriNQ+Z74w== X-Google-Smtp-Source: AHgI3IZDB8EuCAWDOyL4YwwHVwqYG7PoDo/ZooCurJw8ESV2N3HAmVb6qnb3ddGWgRUxsUHJQDSrLg== X-Received: by 2002:a1c:f901:: with SMTP id x1mr2667013wmh.84.1550148671731; Thu, 14 Feb 2019 04:51:11 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 14 Feb 2019 12:50:55 +0000 Message-Id: <20190214125107.22178-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190214125107.22178-1-peter.maydell@linaro.org> References: <20190214125107.22178-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH 02/14] hw/misc/tz-ppc: Support having unused ports in the middle of the range X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The Peripheral Protection Controller's handling of unused ports is that if there is nothing connected to the port's downstream then it does not create the sysbus MMIO region for the upstream end of the port. This results in odd behaviour when there is an unused port in the middle of the range: since sysbus MMIO regions are implicitly consecutively allocated, any used ports above the unused ones end up with sysbus MMIO region numbers that don't match the port number. Avoid this numbering mismatch by creating dummy MMIO regions for the unused ports. This doesn't change anything for our existing boards, which don't have any gaps in the middle of the port ranges they use; but it will be needed for the Musca board. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/misc/tz-ppc.h | 8 +++++++- hw/misc/tz-ppc.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+), 1 deletion(-) diff --git a/include/hw/misc/tz-ppc.h b/include/hw/misc/tz-ppc.h index fc8b806e4df..080d6e2ec17 100644 --- a/include/hw/misc/tz-ppc.h +++ b/include/hw/misc/tz-ppc.h @@ -38,7 +38,13 @@ * * QEMU interface: * + sysbus MMIO regions 0..15: MemoryRegions defining the upstream end - * of each of the 16 ports of the PPC + * of each of the 16 ports of the PPC. When a port is unused (i.e. no + * downstream MemoryRegion is connected to it) at the end of the 0..15 + * range then no sysbus MMIO region is created for its upstream. When an + * unused port lies in the middle of the range with other used ports at + * higher port numbers, a dummy MMIO region is created to ensure that + * port N's upstream is always sysbus MMIO region N. Dummy regions should + * not be mapped, and will assert if any access is made to them. * + Property "port[0..15]": MemoryRegion defining the downstream device(s) * for each of the 16 ports of the PPC * + Named GPIO inputs "cfg_nonsec[0..15]": set to 1 if the port should be diff --git a/hw/misc/tz-ppc.c b/hw/misc/tz-ppc.c index 3dd045c15f5..2e04837bea9 100644 --- a/hw/misc/tz-ppc.c +++ b/hw/misc/tz-ppc.c @@ -181,6 +181,21 @@ static const MemoryRegionOps tz_ppc_ops =3D { .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 +static bool tz_ppc_dummy_accepts(void *opaque, hwaddr addr, + unsigned size, bool is_write, + MemTxAttrs attrs) +{ + /* + * Board code should never map the upstream end of an unused port, + * so we should never try to make a memory access to it. + */ + g_assert_not_reached(); +} + +static const MemoryRegionOps tz_ppc_dummy_ops =3D { + .valid.accepts =3D tz_ppc_dummy_accepts, +}; + static void tz_ppc_reset(DeviceState *dev) { TZPPC *s =3D TZ_PPC(dev); @@ -210,16 +225,33 @@ static void tz_ppc_realize(DeviceState *dev, Error **= errp) SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); TZPPC *s =3D TZ_PPC(dev); int i; + int max_port =3D 0; =20 /* We can't create the upstream end of the port until realize, * as we don't know the size of the MR used as the downstream until th= en. */ for (i =3D 0; i < TZ_NUM_PORTS; i++) { + if (s->port[i].downstream) { + max_port =3D i; + } + } + + for (i =3D 0; i <=3D max_port; i++) { TZPPCPort *port =3D &s->port[i]; char *name; uint64_t size; =20 if (!port->downstream) { + /* + * Create dummy sysbus MMIO region so the sysbus region + * numbering doesn't get out of sync with the port numbers. + * The size is entirely arbitrary. + */ + name =3D g_strdup_printf("tz-ppc-dummy-port[%d]", i); + memory_region_init_io(&port->upstream, obj, &tz_ppc_dummy_ops, + port, name, 0x10000); + sysbus_init_mmio(sbd, &port->upstream); + g_free(name); continue; } =20 --=20 2.20.1 From nobody Sat Nov 8 06:03:08 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1550149517181352.4187488121305; Thu, 14 Feb 2019 05:05:17 -0800 (PST) Received: from localhost ([127.0.0.1]:48255 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1guGhS-00053S-2u for importer@patchew.org; Thu, 14 Feb 2019 08:05:10 -0500 Received: from eggs.gnu.org ([209.51.188.92]:50008) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1guGeU-00038O-4U for qemu-devel@nongnu.org; Thu, 14 Feb 2019 08:02:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1guGTx-0006Rr-Ux for qemu-devel@nongnu.org; Thu, 14 Feb 2019 07:51:14 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:40011) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1guGTx-0006RS-Oo for qemu-devel@nongnu.org; Thu, 14 Feb 2019 07:51:13 -0500 Received: by mail-wm1-x342.google.com with SMTP id q21so5966731wmc.5 for ; Thu, 14 Feb 2019 04:51:13 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j3sm1488073wmb.39.2019.02.14.04.51.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Feb 2019 04:51:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LPT0GH8RargF2/EI2vjidZ0F87i5Cplwmh30EfoSbEQ=; b=p7hrRiVWsFBlyNxj6IJNQiOC58XJfdUMZuytcUqUUl9xzzLFCYonr60Bcq3gFA7bKr gMStSBHEgLl6NKJt52sDDfb2zZyM1lpuFD+4SuHyR6wRs03CmiS8AYc3YXZhcZseRG/s EVryYxeHebleyGHv8mmW/exv3NFEtLE+/rA2ao62aIIIgLuBUOqVrhwTlfu2M9rJMuu+ JuFCJl/2t3x00/pcMV6lV8hFseJFU/ZM2SaCnwfjp6l59/bN7ALDSDQKwKr9hWfhjN16 PLl84uARj9+2o9J7URb7Zk22S3TRBhn+mvDfnGRs9K+rgE8rqq7HmsPvkPGoX8sz4iBO UNFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LPT0GH8RargF2/EI2vjidZ0F87i5Cplwmh30EfoSbEQ=; b=l1Tcm6KuAyQk7nLJ3xOPP2qvOtcuj9Z+DifQ7QUYuCxPWJjE+HRwZewacWNtfFrpPt KAIQkZa77fX+DQf0zBEjnmppZ+Ug8edDuhRY5aQ6z38Uult9YDopLX2pz5Lfmx3FMahg ae2v4dzypYDgNx8XHlAnRFbW7OF4i7zhur8F5VVJ//8IsqsYV7rNazQdJF3L0wY6fXRL rtmkvB2YvGvQLzx6GQKPmwEdUTBaawhPVz1RVN5dYT9m+f8GMG5TMiSoQ+U67IsienyW +F/ICbCF/zV4SS1daU3yKF3di5rJ2uvMjrj+lZ0kWrXz2FmciVkz4BvXTZhLnLwwr1Zb j0TA== X-Gm-Message-State: AHQUAubaeVptSdASm9CCr23P0dMbsTRcefYvZtIEzv95ILy7NyY+qfft YntWJpHcMi7IQ0QdLt7T3e0decqn4IYv/A== X-Google-Smtp-Source: AHgI3IbylVlcw8zWGKIUVxa/drXqf/HknG0oL/mDLPR7ocK+RIGIdwYFZ0yQUW+WX2d+pnlxvcp7Ig== X-Received: by 2002:a1c:9810:: with SMTP id a16mr2625054wme.37.1550148672786; Thu, 14 Feb 2019 04:51:12 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 14 Feb 2019 12:50:56 +0000 Message-Id: <20190214125107.22178-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190214125107.22178-1-peter.maydell@linaro.org> References: <20190214125107.22178-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH 03/14] hw/timer/pl031: Allow use as an embedded-struct device X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Create a new include file for the pl031's device struct, type macros, etc, so that it can be instantiated using the "embedded struct" coding style. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/timer/pl031.h | 44 ++++++++++++++++++++++++++++++++++++++++ hw/timer/pl031.c | 25 +---------------------- MAINTAINERS | 1 + 3 files changed, 46 insertions(+), 24 deletions(-) create mode 100644 include/hw/timer/pl031.h diff --git a/include/hw/timer/pl031.h b/include/hw/timer/pl031.h new file mode 100644 index 00000000000..99416d8ba52 --- /dev/null +++ b/include/hw/timer/pl031.h @@ -0,0 +1,44 @@ +/* + * ARM AMBA PrimeCell PL031 RTC + * + * Copyright (c) 2007 CodeSourcery + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Contributions after 2012-01-13 are licensed under the terms of the + * GNU GPL, version 2 or (at your option) any later version. + */ + +#ifndef HW_TIMER_PL031 +#define HW_TIMER_PL031 + +#include "hw/sysbus.h" + +#define TYPE_PL031 "pl031" +#define PL031(obj) OBJECT_CHECK(PL031State, (obj), TYPE_PL031) + +typedef struct PL031State { + SysBusDevice parent_obj; + + MemoryRegion iomem; + QEMUTimer *timer; + qemu_irq irq; + + /* + * Needed to preserve the tick_count across migration, even if the + * absolute value of the rtc_clock is different on the source and + * destination. + */ + uint32_t tick_offset_vmstate; + uint32_t tick_offset; + + uint32_t mr; + uint32_t lr; + uint32_t cr; + uint32_t im; + uint32_t is; +} PL031State; + +#endif diff --git a/hw/timer/pl031.c b/hw/timer/pl031.c index d3aacce80da..f774dcd5223 100644 --- a/hw/timer/pl031.c +++ b/hw/timer/pl031.c @@ -12,6 +12,7 @@ */ =20 #include "qemu/osdep.h" +#include "hw/timer/pl031.h" #include "hw/sysbus.h" #include "qemu/timer.h" #include "sysemu/sysemu.h" @@ -36,30 +37,6 @@ do { printf("pl031: " fmt , ## __VA_ARGS__); } while (0) #define RTC_MIS 0x18 /* Masked interrupt status register */ #define RTC_ICR 0x1c /* Interrupt clear register */ =20 -#define TYPE_PL031 "pl031" -#define PL031(obj) OBJECT_CHECK(PL031State, (obj), TYPE_PL031) - -typedef struct PL031State { - SysBusDevice parent_obj; - - MemoryRegion iomem; - QEMUTimer *timer; - qemu_irq irq; - - /* Needed to preserve the tick_count across migration, even if the - * absolute value of the rtc_clock is different on the source and - * destination. - */ - uint32_t tick_offset_vmstate; - uint32_t tick_offset; - - uint32_t mr; - uint32_t lr; - uint32_t cr; - uint32_t im; - uint32_t is; -} PL031State; - static const unsigned char pl031_id[] =3D { 0x31, 0x10, 0x14, 0x00, /* Device ID */ 0x0d, 0xf0, 0x05, 0xb1 /* Cell ID */ diff --git a/MAINTAINERS b/MAINTAINERS index 9a76845581b..85d4b4c9f7c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -493,6 +493,7 @@ F: hw/sd/pl181.c F: hw/ssi/pl022.c F: include/hw/ssi/pl022.h F: hw/timer/pl031.c +F: include/hw/timer/pl031.h F: include/hw/arm/primecell.h F: hw/timer/cmsdk-apb-timer.c F: include/hw/timer/cmsdk-apb-timer.h --=20 2.20.1 From nobody Sat Nov 8 06:03:08 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1550149446282716.6375587170311; Thu, 14 Feb 2019 05:04:06 -0800 (PST) Received: from localhost ([127.0.0.1]:48240 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1guGgP-0004Dc-3i for importer@patchew.org; Thu, 14 Feb 2019 08:04:05 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49781) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1guGe9-0002xd-8n for qemu-devel@nongnu.org; Thu, 14 Feb 2019 08:01:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1guGTz-0006Ta-89 for qemu-devel@nongnu.org; Thu, 14 Feb 2019 07:51:16 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:35875) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1guGTz-0006SZ-18 for qemu-devel@nongnu.org; Thu, 14 Feb 2019 07:51:15 -0500 Received: by mail-wm1-x342.google.com with SMTP id j125so5992681wmj.1 for ; Thu, 14 Feb 2019 04:51:14 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j3sm1488073wmb.39.2019.02.14.04.51.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Feb 2019 04:51:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Lin0GiYvYVCL8oSlzJzB40hq7JY2tVdtIrIszLqF2Dw=; b=hLx2nyUiF8H1HOv9XT4npdod5mk+q9jM6ocePkN15uLeDcj/E1ghPv/MVklrYCPPyy k5oBubbH3BZFEe/R4lZk9b3zlvbm65EMT4raR4fUDdXIhGUXDw810YCAwZXzdNGtZ7PV hQRTCRTJr1BwotR5ioNiWgc6v0tKwd4m9EMsLMN2pjuwhi6n8E0O7gVzPAnhDS3qhGpx 19rKtMX5IEgw5TMsNQZsQEusWD7TWyajq/4u8RU0iGLYmbCYssInDDba52YYsBiPNE0s UQo0SZHRmlCKEbml07UPUIafDH7o3UmBd8DD+iqfAW0Ol0JUcxM17Js2Ls5FgjAlK5bb VLOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Lin0GiYvYVCL8oSlzJzB40hq7JY2tVdtIrIszLqF2Dw=; b=UDlzLkQBRJQXKEIVLzkKHVufTM1fEm0DicIwnJkS27gw9SSNfdOAmntiKHsilk8r8d Ep5hjkr1fSyYHAJt5XzVboMQcYkRWFgTDftvl1LUgBGvSGcQVsWpKE/8uOx4KKdUeAm3 AukCIiRH0/NMiQ2jv/25K0MpaPrMkvNz5jCTJWjEp9BWAsBe1lr6K75fiJzQAOyzfa2b ikLz5D7n4ruUbNLonfBiCOaTdzhL96XvgK2UL7tml89fk4gDCobXNKd2H/nh37/CPSGC iEVZl6Z7cQDoQbuueWhDMTFB5/sKDwYjXGCyrKd3RAN77jSqv1TOaZ5EP8f57uIu7wIz 2cVw== X-Gm-Message-State: AHQUAuYNRHV/42drcWgXT0WTY6RBWZsxk9GNOnOILHZ/gAJO/0Ewd0AY ILdsrNiQ1/LyzUeL/htxhhGAUVouuj9P2g== X-Google-Smtp-Source: AHgI3IYD3t44465u21ZLhxGXLFsJFRQjhiZvKEEPCkifeHVOouEJ+IkXRV5/qVyv8/kwu/VkUJdDSQ== X-Received: by 2002:a1c:9aca:: with SMTP id c193mr2625756wme.2.1550148674017; Thu, 14 Feb 2019 04:51:14 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 14 Feb 2019 12:50:57 +0000 Message-Id: <20190214125107.22178-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190214125107.22178-1-peter.maydell@linaro.org> References: <20190214125107.22178-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH 04/14] hw/timer/pl031: Convert to using trace events X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Convert the debug printing in the PL031 device to use trace events, and augment it to cover the interesting parts of device operation. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/timer/pl031.c | 55 +++++++++++++++++++++++-------------------- hw/timer/trace-events | 6 +++++ 2 files changed, 36 insertions(+), 25 deletions(-) diff --git a/hw/timer/pl031.c b/hw/timer/pl031.c index f774dcd5223..274ad47a33a 100644 --- a/hw/timer/pl031.c +++ b/hw/timer/pl031.c @@ -18,15 +18,7 @@ #include "sysemu/sysemu.h" #include "qemu/cutils.h" #include "qemu/log.h" - -//#define DEBUG_PL031 - -#ifdef DEBUG_PL031 -#define DPRINTF(fmt, ...) \ -do { printf("pl031: " fmt , ## __VA_ARGS__); } while (0) -#else -#define DPRINTF(fmt, ...) do {} while(0) -#endif +#include "trace.h" =20 #define RTC_DR 0x00 /* Data read register */ #define RTC_MR 0x04 /* Match register */ @@ -44,7 +36,10 @@ static const unsigned char pl031_id[] =3D { =20 static void pl031_update(PL031State *s) { - qemu_set_irq(s->irq, s->is & s->im); + uint32_t flags =3D s->is & s->im; + + trace_pl031_irq_state(flags); + qemu_set_irq(s->irq, flags); } =20 static void pl031_interrupt(void * opaque) @@ -52,7 +47,7 @@ static void pl031_interrupt(void * opaque) PL031State *s =3D (PL031State *)opaque; =20 s->is =3D 1; - DPRINTF("Alarm raised\n"); + trace_pl031_alarm_raised(); pl031_update(s); } =20 @@ -69,7 +64,7 @@ static void pl031_set_alarm(PL031State *s) /* The timer wraps around. This subtraction also wraps in the same wa= y, and gives correct results when alarm < now_ticks. */ ticks =3D s->mr - pl031_get_count(s); - DPRINTF("Alarm set in %ud ticks\n", ticks); + trace_pl031_set_alarm(ticks); if (ticks =3D=3D 0) { timer_del(s->timer); pl031_interrupt(s); @@ -83,38 +78,49 @@ static uint64_t pl031_read(void *opaque, hwaddr offset, unsigned size) { PL031State *s =3D (PL031State *)opaque; - - if (offset >=3D 0xfe0 && offset < 0x1000) - return pl031_id[(offset - 0xfe0) >> 2]; + uint64_t r; =20 switch (offset) { case RTC_DR: - return pl031_get_count(s); + r =3D pl031_get_count(s); + break; case RTC_MR: - return s->mr; + r =3D s->mr; + break; case RTC_IMSC: - return s->im; + r =3D s->im; + break; case RTC_RIS: - return s->is; + r =3D s->is; + break; case RTC_LR: - return s->lr; + r =3D s->lr; + break; case RTC_CR: /* RTC is permanently enabled. */ - return 1; + r =3D 1; + break; case RTC_MIS: - return s->is & s->im; + r =3D s->is & s->im; + break; + case 0xfe0 ... 0xfff: + r =3D pl031_id[(offset - 0xfe0) >> 2]; + break; case RTC_ICR: qemu_log_mask(LOG_GUEST_ERROR, "pl031: read of write-only register at offset 0x%x\n= ", (int)offset); + r =3D 0; break; default: qemu_log_mask(LOG_GUEST_ERROR, "pl031_read: Bad offset 0x%x\n", (int)offset); + r =3D 0; break; } =20 - return 0; + trace_pl031_read(offset, r); + return r; } =20 static void pl031_write(void * opaque, hwaddr offset, @@ -122,6 +128,7 @@ static void pl031_write(void * opaque, hwaddr offset, { PL031State *s =3D (PL031State *)opaque; =20 + trace_pl031_write(offset, value); =20 switch (offset) { case RTC_LR: @@ -134,7 +141,6 @@ static void pl031_write(void * opaque, hwaddr offset, break; case RTC_IMSC: s->im =3D value & 1; - DPRINTF("Interrupt mask %d\n", s->im); pl031_update(s); break; case RTC_ICR: @@ -142,7 +148,6 @@ static void pl031_write(void * opaque, hwaddr offset, cleared when bit 0 of the written value is set. However the arm926e documentation (DDI0287B) states that the interrupt is cleared when any value is written. */ - DPRINTF("Interrupt cleared"); s->is =3D 0; pl031_update(s); break; diff --git a/hw/timer/trace-events b/hw/timer/trace-events index 0144a68951c..12eb505fee7 100644 --- a/hw/timer/trace-events +++ b/hw/timer/trace-events @@ -77,3 +77,9 @@ xlnx_zynqmp_rtc_gettime(int year, int month, int day, int= hour, int min, int sec nrf51_timer_read(uint64_t addr, uint32_t value, unsigned size) "read addr = 0x%" PRIx64 " data 0x%" PRIx32 " size %u" nrf51_timer_write(uint64_t addr, uint32_t value, unsigned size) "write add= r 0x%" PRIx64 " data 0x%" PRIx32 " size %u" =20 +# hw/timer/pl031.c +pl031_irq_state(int level) "irq state %d" +pl031_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" +pl031_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" +pl031_alarm_raised(void) "alarm raised" +pl031_set_alarm(uint32_t ticks) "alarm set for %u ticks" --=20 2.20.1 From nobody Sat Nov 8 06:03:08 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1550150095666298.56807266692283; Thu, 14 Feb 2019 05:14:55 -0800 (PST) Received: from localhost ([127.0.0.1]:48426 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1guGqo-0004ZT-JQ for importer@patchew.org; Thu, 14 Feb 2019 08:14:50 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49695) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1guGeS-0002tV-29 for qemu-devel@nongnu.org; Thu, 14 Feb 2019 08:02:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1guGU0-0006Uj-KZ for qemu-devel@nongnu.org; Thu, 14 Feb 2019 07:51:18 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:38286) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1guGU0-0006Tn-Aa for qemu-devel@nongnu.org; Thu, 14 Feb 2019 07:51:16 -0500 Received: by mail-wr1-x444.google.com with SMTP id v13so6343987wrw.5 for ; Thu, 14 Feb 2019 04:51:16 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j3sm1488073wmb.39.2019.02.14.04.51.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Feb 2019 04:51:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1OLWN1Os/7gGDPurXe5cQamlogPhIwB9LbNuZjXBuKI=; b=lJpNLusDpQh2PHjl/4+ywixCD1ZJT8eezUQkNViObLwuuvQBjT/L1xNnqIK8p1aGoa z+7NGf2bU7yJRRWYRlbo8peZ5jboTUY50DEzI9kU88JM24elAwrezjARbH40do8RhJse 6/DUxbhtEDHlTJyr7IQrexHv/2jvpEZqOlSOu/i5esjeFPq344SFFHWNPb8b7Zp5M200 i26uBp0ZhNTEULGWAHCVzPX05ObqhJ3xUN+KKRJm03j/kMmBNkjnziPLhRCdgOaDsPIG +hSXKcxPugQBvVevviu9h/K7kdjtCN3H/qSvdLPEe6f6JAufQsHyTz+nnumfEajcHULj WMpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1OLWN1Os/7gGDPurXe5cQamlogPhIwB9LbNuZjXBuKI=; b=dASPABz2ouDpYnoMY0s6VxXgizBJyUM6k3ur2e7SpAu8OMp1EBpsR9epagQjDS7XYH ZxLbL9yj3o49DWLlXq+1BWwsK2O3f+MvVEBLVY2L1rEfPHN9n2CowY/npJ6z5wHeS0oL gTN0PDUAIzh57u4fgg+cXMhajy6ArmLu3RmJI7JW4EgnJ9xzensHt1fIkarnFeJM1ZZs l3BsBJoW6wSPv76gIm4oOXJcReP8y5sinpERSNotzmsGy6cyfBBD1TJ6e5o9+4QgDykK 9zbeHmZvZOAsjyqn7j1r5YcbopyjOgy9BwylWM7AGAnckXel2mvvlvozUcGuWNO30mTY xhdw== X-Gm-Message-State: AHQUAuYldaGSwB4XjUd/sQDOM0Zwmr2UfWy+haDsG8AX+GWwXJSCviDP VTRxOZXyDt71us8kBS4vbzkzeA== X-Google-Smtp-Source: AHgI3Ian8aZkei2dU7yGnU6bv/Rr2iM818Ac5w+1BY9+4zno94j54x0kqkiGPAzSGFdsl5NpZxWVsQ== X-Received: by 2002:adf:fc87:: with SMTP id g7mr2710183wrr.136.1550148675171; Thu, 14 Feb 2019 04:51:15 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 14 Feb 2019 12:50:58 +0000 Message-Id: <20190214125107.22178-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190214125107.22178-1-peter.maydell@linaro.org> References: <20190214125107.22178-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH 05/14] hw/char/pl011: Allow use as an embedded-struct device X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Create a new include file for the pl011's device struct, type macros, etc, so that it can be instantiated using the "embedded struct" coding style. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/char/pl011.h | 34 ++++++++++++++++++++++++++++++++++ hw/char/pl011.c | 31 ++----------------------------- 2 files changed, 36 insertions(+), 29 deletions(-) diff --git a/include/hw/char/pl011.h b/include/hw/char/pl011.h index 83649324b6a..1b52bfd5c90 100644 --- a/include/hw/char/pl011.h +++ b/include/hw/char/pl011.h @@ -15,6 +15,40 @@ #ifndef HW_PL011_H #define HW_PL011_H =20 +#include "hw/sysbus.h" +#include "chardev/char-fe.h" + +#define TYPE_PL011 "pl011" +#define PL011(obj) OBJECT_CHECK(PL011State, (obj), TYPE_PL011) + +/* This shares the same struct (and cast macro) as the base pl011 device */ +#define TYPE_PL011_LUMINARY "pl011_luminary" + +typedef struct PL011State { + SysBusDevice parent_obj; + + MemoryRegion iomem; + uint32_t readbuff; + uint32_t flags; + uint32_t lcr; + uint32_t rsr; + uint32_t cr; + uint32_t dmacr; + uint32_t int_enabled; + uint32_t int_level; + uint32_t read_fifo[16]; + uint32_t ilpr; + uint32_t ibrd; + uint32_t fbrd; + uint32_t ifl; + int read_pos; + int read_count; + int read_trigger; + CharBackend chr; + qemu_irq irq; + const unsigned char *id; +} PL011State; + static inline DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 2aa277fc4f2..0c4711e4027 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -8,39 +8,12 @@ */ =20 #include "qemu/osdep.h" +#include "hw/char/pl011.h" #include "hw/sysbus.h" #include "chardev/char-fe.h" #include "qemu/log.h" #include "trace.h" =20 -#define TYPE_PL011 "pl011" -#define PL011(obj) OBJECT_CHECK(PL011State, (obj), TYPE_PL011) - -typedef struct PL011State { - SysBusDevice parent_obj; - - MemoryRegion iomem; - uint32_t readbuff; - uint32_t flags; - uint32_t lcr; - uint32_t rsr; - uint32_t cr; - uint32_t dmacr; - uint32_t int_enabled; - uint32_t int_level; - uint32_t read_fifo[16]; - uint32_t ilpr; - uint32_t ibrd; - uint32_t fbrd; - uint32_t ifl; - int read_pos; - int read_count; - int read_trigger; - CharBackend chr; - qemu_irq irq; - const unsigned char *id; -} PL011State; - #define PL011_INT_TX 0x20 #define PL011_INT_RX 0x10 =20 @@ -357,7 +330,7 @@ static void pl011_luminary_init(Object *obj) } =20 static const TypeInfo pl011_luminary_info =3D { - .name =3D "pl011_luminary", + .name =3D TYPE_PL011_LUMINARY, .parent =3D TYPE_PL011, .instance_init =3D pl011_luminary_init, }; --=20 2.20.1 From nobody Sat Nov 8 06:03:08 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1550149986555394.16687038133136; Thu, 14 Feb 2019 05:13:06 -0800 (PST) Received: from localhost ([127.0.0.1]:48410 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1guGp5-0003AR-GH for importer@patchew.org; Thu, 14 Feb 2019 08:13:03 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49891) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1guGeR-00032s-UO for qemu-devel@nongnu.org; Thu, 14 Feb 2019 08:02:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1guGUD-0006nG-8P for qemu-devel@nongnu.org; Thu, 14 Feb 2019 07:51:32 -0500 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:55949) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1guGU2-0006VK-Lk for qemu-devel@nongnu.org; Thu, 14 Feb 2019 07:51:22 -0500 Received: by mail-wm1-x344.google.com with SMTP id r17so6109277wmh.5 for ; Thu, 14 Feb 2019 04:51:17 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j3sm1488073wmb.39.2019.02.14.04.51.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Feb 2019 04:51:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9GhcdoHkWYFQUs/bSK2K6WRQDH8DkevPHImfn8kPArY=; b=n26sLxq5Oi6VHS4zA4McrNiLy47MxTPtsjbf46p8iXp7IXVvPwXCyxaRNXouvi754D R4CMIulgR6cmE2PfuwwOy5FLa8pw2zUrEK6q2+gN+OCBVIOyC0qafM0DV6ScK16Rt6xN QOTIFAuWnAL/OQnY3iHj+m9GrlaUH86QgGfV1NGRWJvHQ4YRC7KtkK2RmBDjz7+ujyJw Q94sHUBR3iz427T5z8v9cUhP5RBe2wcf1jQQBbxSrVFQ2L+GHq2cgabPauFKJ8t1omx5 kpes/M1ERnw5FmnhpupeaErVzbGvxfdM3yhJSemVEUKa03VmoyPchiVFM/kp1u2/MNNg 4RZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9GhcdoHkWYFQUs/bSK2K6WRQDH8DkevPHImfn8kPArY=; b=gUEfmqmTeXJmhzAI6WY6nEaWj8odsb5Ju2rGnmk+XKwhQmrLbTQ/bigH5x/LsCzeQh Srh9RFdfuB6ciC+UJ4YY8oVFo32I5mFulVvwAyrzSNEkqYdRfnEQNA9iXhrydNJef+g+ pV8ZUPGxp/lyAFm9hL1z7mcvOJ/AXQuwK2bFqlnkrnBST/Fti8jeAEnzv2hE7Q9zpgej O8/2obimHb7UviZe+DdaRi5ewgzJdCrQiUkf9dGFh8BlrFyOidJfXbZ8/kcnBXDB16BI XdCZ6I6Tpv4BmM7eOnrY6wyvndqPGrhx1TMXeiDYKeOtBzAjDjcoUi5xuAzTEkujtpxv I+WA== X-Gm-Message-State: AHQUAub172aWeAQ63VwA5GA2JprDfeDaK0BMI8B+4XoTciqLynYi00BL qdoeyfj8Q2qtGjjcPnn6VxSZLA== X-Google-Smtp-Source: AHgI3IbGy/ZoEJGfKMG/A027h0ltYIan8BPnL8mJo7dGG5cMFhJc5+Enf8BjDGhXe+t/5O5iTJnZGw== X-Received: by 2002:a1c:1b4e:: with SMTP id b75mr2788355wmb.88.1550148676391; Thu, 14 Feb 2019 04:51:16 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 14 Feb 2019 12:50:59 +0000 Message-Id: <20190214125107.22178-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190214125107.22178-1-peter.maydell@linaro.org> References: <20190214125107.22178-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH 06/14] hw/char/pl011: Support all interrupt lines X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The PL011 UART has six interrupt lines: * RX (receive data) * TX (transmit data) * RT (receive timeout) * MS (modem status) * E (errors) * combined (logical OR of all the above) So far we have only emulated the combined interrupt line; add support for the others, so that boards that wire them up to different interrupt controller inputs can do so. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/char/pl011.h | 2 +- hw/char/pl011.c | 46 +++++++++++++++++++++++++++++++++++++++-- 2 files changed, 45 insertions(+), 3 deletions(-) diff --git a/include/hw/char/pl011.h b/include/hw/char/pl011.h index 1b52bfd5c90..dad3cf29121 100644 --- a/include/hw/char/pl011.h +++ b/include/hw/char/pl011.h @@ -45,7 +45,7 @@ typedef struct PL011State { int read_count; int read_trigger; CharBackend chr; - qemu_irq irq; + qemu_irq irq[6]; const unsigned char *id; } PL011State; =20 diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 0c4711e4027..29f4e5eb224 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -7,6 +7,17 @@ * This code is licensed under the GPL. */ =20 +/* + * QEMU interface: + * + sysbus MMIO region 0: device registers + * + sysbus IRQ 0: UARTINTR (combined interrupt line) + * + sysbus IRQ 1: UARTRXINTR (receive FIFO interrupt line) + * + sysbus IRQ 2: UARTTXINTR (transmit FIFO interrupt line) + * + sysbus IRQ 3: UARTRTINTR (receive timeout interrupt line) + * + sysbus IRQ 4: UARTMSINTR (momem status interrupt line) + * + sysbus IRQ 5: UARTEINTR (error interrupt line) + */ + #include "qemu/osdep.h" #include "hw/char/pl011.h" #include "hw/sysbus.h" @@ -22,18 +33,46 @@ #define PL011_FLAG_TXFF 0x20 #define PL011_FLAG_RXFE 0x10 =20 +/* Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC */ +#define INT_OE (1 << 10) +#define INT_BE (1 << 9) +#define INT_PE (1 << 8) +#define INT_FE (1 << 7) +#define INT_RT (1 << 6) +#define INT_TX (1 << 5) +#define INT_RX (1 << 4) +#define INT_DSR (1 << 3) +#define INT_DCD (1 << 2) +#define INT_CTS (1 << 1) +#define INT_RI (1 << 0) +#define INT_E (INT_OE | INT_BE | INT_PE | INT_FE) +#define INT_MS (INT_RI | INT_DSR | INT_DCD | INT_CTS) + static const unsigned char pl011_id_arm[8] =3D { 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; static const unsigned char pl011_id_luminary[8] =3D { 0x11, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 }; =20 +/* Which bits in the interrupt status matter for each outbound IRQ line ? = */ +static const uint32_t irqmask[] =3D { + INT_E | INT_MS | INT_RT | INT_TX | INT_RX, /* combined IRQ */ + INT_RX, + INT_TX, + INT_RT, + INT_MS, + INT_E, +}; + static void pl011_update(PL011State *s) { uint32_t flags; + int i; =20 flags =3D s->int_level & s->int_enabled; trace_pl011_irq_state(flags !=3D 0); - qemu_set_irq(s->irq, flags !=3D 0); + for (i =3D 0; i < ARRAY_SIZE(s->irq); i++) { + qemu_set_irq(s->irq[i], (flags & irqmask[i]) !=3D 0); + } } =20 static uint64_t pl011_read(void *opaque, hwaddr offset, @@ -284,10 +323,13 @@ static void pl011_init(Object *obj) { SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); PL011State *s =3D PL011(obj); + int i; =20 memory_region_init_io(&s->iomem, OBJECT(s), &pl011_ops, s, "pl011", 0x= 1000); sysbus_init_mmio(sbd, &s->iomem); - sysbus_init_irq(sbd, &s->irq); + for (i =3D 0; i < ARRAY_SIZE(s->irq); i++) { + sysbus_init_irq(sbd, &s->irq[i]); + } =20 s->read_trigger =3D 1; s->ifl =3D 0x12; --=20 2.20.1 From nobody Sat Nov 8 06:03:08 2025 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1550149411011448.3899507603569; Thu, 14 Feb 2019 05:03:31 -0800 (PST) Received: from localhost ([127.0.0.1]:48234 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1guGfl-0003l5-E9 for importer@patchew.org; Thu, 14 Feb 2019 08:03:25 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49693) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1guGdx-0002tT-S2 for qemu-devel@nongnu.org; Thu, 14 Feb 2019 08:01:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1guGUD-0006nF-8K for qemu-devel@nongnu.org; Thu, 14 Feb 2019 07:51:31 -0500 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:38225) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1guGU2-0006Xe-OK for qemu-devel@nongnu.org; Thu, 14 Feb 2019 07:51:22 -0500 Received: by mail-wm1-x344.google.com with SMTP id v26so5975960wmh.3 for ; Thu, 14 Feb 2019 04:51:18 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j3sm1488073wmb.39.2019.02.14.04.51.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Feb 2019 04:51:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=G2EhbTfL6RgiBoe8p2qGDsQHbXzW305CIfRgaTSzQks=; b=tpiiNAkRlt5Mq4oVeOBPjfNDjT7rd4+uEtR3yNh8IAy1r9JhNNpqaGyNA/Lmqzi5H5 UgmZ9cZxBCcYcWb1qX3LHxAsrKbiiQc0A2bKR4WIBGupsZJe4f5/mkkkKdZ4jv/ZBeam Vy+ch7yIi9BOPRwYHjfQwrNyK1rk/6nMb6N/uOEOncQTiUhdCxeLqh7ltCYX9ChyCQyl Kci99sFGR5WNrhixpiyvt1xmgTjHaaaiNRuydLEW7pA+e/uzCYwBItJDAOWJkzK7EeUS OfMKw6po7mOV0YsbcXfFqoDnsD7xIZwTLmd4xoj4EjpD6EX7E5rIxv3C3whAGwU2GJjj uQqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=G2EhbTfL6RgiBoe8p2qGDsQHbXzW305CIfRgaTSzQks=; b=KlRe/wFhfnLrCg+r7Q89d/NcRgdgXOSvRZ6nH5BAQ67xKNywBMJvDs+7k1HE5Zpc3v E8ty+H2V1/i0HsgwUOS5j1weI9vAM9miVWD6DMmaGCoQKVT1GtusWwTy9L1/WKYk636P 4iDpbSc6fFaEjPU4grsNd4K+RsDsvGve2jbvzIlGXiUNuEML8JhOHRlCG43DHXf8l6b9 p8LBMlAnI+tB36O53r4+PYybsaD6w9ALQ+qqFqP7vhOVNKs+XNc489qBUClJCtgcqsOH qfBfna9PeSDzTOZFV+gzdM1sDo1tp7TFbQigKnOgG2w8s+QNq24FeNmoTCqHVDvuQxx+ +UYg== X-Gm-Message-State: AHQUAub2M9ZHYbdylSJET9iJRb+mhpIMy7HLEGUD0Q7C/ANRERgi7C75 +racJX+8L096FnoiVU8V/PEIvw== X-Google-Smtp-Source: AHgI3IY1Uv3H5pTIkg0nRJwnQaPuouQY+kNSeZKZ4hYC7hJl/dWEypKbgTdAsHmbhI2Z2yPaKxKD4g== X-Received: by 2002:a7b:cf03:: with SMTP id l3mr2650197wmg.14.1550148677565; Thu, 14 Feb 2019 04:51:17 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 14 Feb 2019 12:51:00 +0000 Message-Id: <20190214125107.22178-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190214125107.22178-1-peter.maydell@linaro.org> References: <20190214125107.22178-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH 07/14] hw/char/pl011: Use '0x' prefix when logging hex numbers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The pl011 logs when the guest makes a bad access. It prints the address offset in hex but confusingly omits the '0x' prefix; add it. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/char/pl011.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 29f4e5eb224..e5dd448f854 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -143,7 +143,7 @@ static uint64_t pl011_read(void *opaque, hwaddr offset, break; default: qemu_log_mask(LOG_GUEST_ERROR, - "pl011_read: Bad offset %x\n", (int)offset); + "pl011_read: Bad offset 0x%x\n", (int)offset); r =3D 0; break; } @@ -232,7 +232,7 @@ static void pl011_write(void *opaque, hwaddr offset, break; default: qemu_log_mask(LOG_GUEST_ERROR, - "pl011_write: Bad offset %x\n", (int)offset); + "pl011_write: Bad offset 0x%x\n", (int)offset); } } =20 --=20 2.20.1 From nobody Sat Nov 8 06:03:08 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1550149488066925.2555474469065; Thu, 14 Feb 2019 05:04:48 -0800 (PST) Received: from localhost ([127.0.0.1]:48242 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1guGh2-0004jP-4K for importer@patchew.org; Thu, 14 Feb 2019 08:04:44 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49935) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1guGeO-00034b-FP for qemu-devel@nongnu.org; Thu, 14 Feb 2019 08:02:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1guGUe-000728-Je for qemu-devel@nongnu.org; Thu, 14 Feb 2019 07:51:58 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:37870) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1guGUe-0006ZF-Ao for qemu-devel@nongnu.org; Thu, 14 Feb 2019 07:51:56 -0500 Received: by mail-wm1-x32c.google.com with SMTP id x10so5926232wmg.2 for ; Thu, 14 Feb 2019 04:51:19 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j3sm1488073wmb.39.2019.02.14.04.51.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Feb 2019 04:51:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ebn64XdcAcwAG7W2yYJLFh5oyBBZkjhw+yyDNY3aVQc=; b=nRh++iUG3stPiTw+pdpr5Sjc6NRsdcS/YRYk0cjIkqq4Zfi7Tal2abID+yOVEzYdgH iNbYbGfRHCR5TTx3rijF8pt9ppO6nI/FLuSCYr4peXGqYtozwQUssbzabDd41yrNJkhu ZRJSDanM7B0aKLxOpO3HLGEhC77JzU0VopJ2XmXY07xmjYosGiFtQuWtrA+xfNTP74JT aStUzcmODFLCFoYquJt80HI9Ts7GCs3z82+HIVevByLPKwU50YKcrQW8Jx9Rf7nTOdzC blfuOekfCQjAaNxGxZrpPmh6Mgukw0vGVYSG4os9nBiLiXbLGdXlD7eE9k8NRb/WmduM KpCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ebn64XdcAcwAG7W2yYJLFh5oyBBZkjhw+yyDNY3aVQc=; b=izLHN41Q0D0mEiIwONsQSWe88Fcw8f/ZvW81IYK30H6yIsuGg6fLk+mZyeRKc6Qa6b 9KW97EwTnqg5laeSws4X08P0jkHVZxtHmDvonkmNr9UeI13gXY3GNx3tExSFf58p83vH vwfZSHbj4gjdnUcyfM0JG/ROt9qKXiLFgolNz47fw8Y54SWuWnJkLOyJlnjjFl6RA+dZ lgmu8c3f7/qBFo3pg0bKkzIyyzrO0muRIbHyBQCtaFOaeZkmt+smIiLuBvsmArwUvJ4M 2ly3O4T8tD91lUHivTSxeJlm3mAS+bhzTZ5uT3RaEh4qfDMWVcqeLnyQAzSWBc2rYbLQ wXBg== X-Gm-Message-State: AHQUAuYH0SF14Xkm8zkoLRN9uuo0o5aSx9YrGhNj3KhbhpYdc9Trvo45 LpXPRQHVlix4CPSnWIL+mSLP03Hr5AgnCQ== X-Google-Smtp-Source: AHgI3IbqfH2MkwEDS4ptCvGH4MLbR4fgJYO1gwMqGr0F1+hzKKmyc/TZyi8kzv9UlidNiigNA9AiBQ== X-Received: by 2002:a1c:e1c4:: with SMTP id y187mr2755729wmg.50.1550148678630; Thu, 14 Feb 2019 04:51:18 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 14 Feb 2019 12:51:01 +0000 Message-Id: <20190214125107.22178-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190214125107.22178-1-peter.maydell@linaro.org> References: <20190214125107.22178-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32c Subject: [Qemu-devel] [PATCH 08/14] hw/arm/armsse: Document SRAM_ADDR_WIDTH property in header comment X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" In commit 4b635cf7a95e501211 we added a QOM property to the ARMSSE object, but forgot to add it to the documentation comment in the header. Correct the omission. Fixes: 4b635cf7a95e501211 ("hw/arm/armsse: Make SRAM bank size configurable= ") Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/arm/armsse.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index f800bafb14a..444605b44dc 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -46,6 +46,8 @@ * being the same for both, to avoid having to have separate Property * lists for different variants. This restriction can be relaxed later * if necessary.) + * + QOM property "SRAM_ADDR_WIDTH" sets the number of bits used for the + * address of each SRAM bank (and thus the total amount of internal SRA= M) * + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CP= U 0, * which are wired to its NVIC lines 32 .. n+32 * + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts f= or --=20 2.20.1 From nobody Sat Nov 8 06:03:08 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1550149663064770.9054316047332; Thu, 14 Feb 2019 05:07:43 -0800 (PST) Received: from localhost ([127.0.0.1]:48312 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1guGjr-0007AQ-S3 for importer@patchew.org; Thu, 14 Feb 2019 08:07:39 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49693) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1guGeO-0002tT-LM for qemu-devel@nongnu.org; Thu, 14 Feb 2019 08:02:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1guGUe-00071u-GD for qemu-devel@nongnu.org; Thu, 14 Feb 2019 07:51:57 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:54896) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1guGUe-0006bC-8C for qemu-devel@nongnu.org; Thu, 14 Feb 2019 07:51:56 -0500 Received: by mail-wm1-x342.google.com with SMTP id a62so6166418wmh.4 for ; Thu, 14 Feb 2019 04:51:20 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j3sm1488073wmb.39.2019.02.14.04.51.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Feb 2019 04:51:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=i7iefvAvCVRA+KRHNYGYL+qeYUkXaEz5YcRL7tedKZY=; b=RJDEqj7j8XWkG/cMdBPF8DDTmFYF71f6ppHBCIj8blVUT3Id1IvQ9u21UvtfDavnRg Gt8RKUIkzBjMxfRVL3K7MT9sdlzsytUnYN5mXm3fHFCIBCyNw4+B5TKgsuPQDu5qPeca nOukU8K7yVbm7GlLheLXUaS5fuJRlYBWvOGrasCGPOQHUqSq23v6svgWnLe8x0gjORMl tsMRyku9uF89kg4ZBgAfv5kcLJITnnZ1VNuvXiNL4Cf6ukzZOzrB0nHR4dNsrIpfPbwE oFoaCPgJypi3mGrCb2CDJ/0IjYo5ziaNHrhqdpHxFfWney7mkk7pLNB1wPbzwmLXtuHa +kAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=i7iefvAvCVRA+KRHNYGYL+qeYUkXaEz5YcRL7tedKZY=; b=Om86H/dkVN8uHAUZtpT/BzuO40OGF+GtsXHVaC3wzgCaHM9901C2llYRLDmPYNDoeP ZQGRjRa3zSfNIqqxk+ZEA8uE9uwdCEdaW8eBWG/RpGm4OMhhDCqQyCU1SdiQasG9ohSZ jgTjTbCEEWMQ2yBvBRkB/rGtMBg5Q4HDB5iCP7FWzZE4ct+YQ3liAGoIZvZRTtTjOEnh g/T3N+kDTn3PR9mRquKt7ga4EOsUGGzewRhoAdaL7rk+Kvv2rX9FwrVlcvi7mfULxxD2 zzgy1xD1KcQPyS1dJaxcWHY5+cntDdupW3hniaixGIx7GsTUK3ANoVIzIpF0dGUeiMHi BqiA== X-Gm-Message-State: AHQUAubrJt1dQPdxsm4ATsUJc7Z7YPcMRybhRws7z06McT8E9Syb+/b8 IXUZ7pdTgdC34HHh5yha6APatw== X-Google-Smtp-Source: AHgI3IZ+FGrL2VXmlrVdLteBjBJACF4FOWCTEhLe9soyNqkqbHIniMGCTrJvQ633Z92GgMcYDmI2rQ== X-Received: by 2002:a1c:c40c:: with SMTP id u12mr2530542wmf.11.1550148679746; Thu, 14 Feb 2019 04:51:19 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 14 Feb 2019 12:51:02 +0000 Message-Id: <20190214125107.22178-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190214125107.22178-1-peter.maydell@linaro.org> References: <20190214125107.22178-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH 09/14] hw/arm/armsse: Allow boards to specify init-svtor X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The Musca boards have DAPLink firmware that sets the initial secure VTOR value (the location of the vector table) differently depending on the boot mode (from flash, from RAM, etc). Export the init-svtor as a QOM property of the ARMSSE object so that the board can change it. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/arm/armsse.h | 3 +++ hw/arm/armsse.c | 8 ++++---- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 444605b44dc..84879f40dd8 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -48,6 +48,8 @@ * if necessary.) * + QOM property "SRAM_ADDR_WIDTH" sets the number of bits used for the * address of each SRAM bank (and thus the total amount of internal SRA= M) + * + QOM property "init-svtor" sets the initial value of the CPU SVTOR re= gister + * (where it expects to load the PC and SP from the vector table on res= et) * + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CP= U 0, * which are wired to its NVIC lines 32 .. n+32 * + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts f= or @@ -204,6 +206,7 @@ typedef struct ARMSSE { uint32_t exp_numirq; uint32_t mainclk_frq; uint32_t sram_addr_width; + uint32_t init_svtor; } ARMSSE; =20 typedef struct ARMSSEInfo ARMSSEInfo; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 9a8c49547db..3040ea9324e 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -505,11 +505,10 @@ static void armsse_realize(DeviceState *dev, Error **= errp) * the INITSVTOR* registers before powering up the CPUs in any cas= e, * so the hardware's default value doesn't matter. QEMU doesn't em= ulate * the control processor, so instead we behave in the way that the - * firmware does. All boards currently known about have firmware t= hat - * sets the INITSVTOR0 and INITSVTOR1 registers to 0x10000000, lik= e the - * IoTKit default. We can make this more configurable if necessary. + * firmware does. The initial value is configurable by the board c= ode + * to match whatever its firmware does. */ - qdev_prop_set_uint32(cpudev, "init-svtor", 0x10000000); + qdev_prop_set_uint32(cpudev, "init-svtor", s->init_svtor); /* * Start all CPUs except CPU0 powered down. In real hardware it is * a configurable property of the SSE-200 which CPUs start powered= up @@ -1185,6 +1184,7 @@ static Property armsse_properties[] =3D { DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0), DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), + DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), DEFINE_PROP_END_OF_LIST() }; =20 --=20 2.20.1 From nobody Sat Nov 8 06:03:08 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1550149834860682.3923338961746; Thu, 14 Feb 2019 05:10:34 -0800 (PST) Received: from localhost ([127.0.0.1]:48352 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1guGmZ-0001FA-OJ for importer@patchew.org; Thu, 14 Feb 2019 08:10:27 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49748) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1guGeN-0002vd-KB for qemu-devel@nongnu.org; Thu, 14 Feb 2019 08:02:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1guGUe-000723-Hv for qemu-devel@nongnu.org; Thu, 14 Feb 2019 07:51:58 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:37877) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1guGUe-0006dE-6T for qemu-devel@nongnu.org; Thu, 14 Feb 2019 07:51:56 -0500 Received: by mail-wm1-x333.google.com with SMTP id x10so5926348wmg.2 for ; Thu, 14 Feb 2019 04:51:22 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j3sm1488073wmb.39.2019.02.14.04.51.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Feb 2019 04:51:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Cmk9snjFVJivgWjfslWczIKV+LYGTGnCXg+808OCaPc=; b=pwjEot2G4mDp5+2iW28i7Yv7SsC4jJynE6iVdbEo1j5O6VBAx3BbcTAN2Q11Dn7+nd SnxSF782kJIcjiIaUNZYB3ZajyD4v6sUDzG52IusTqocbK4b32LXwFXugXgue2G+rxWX Xg4XpKOQt9gHOB/HEFOcrBFyEaRNK5IwRTJhfL6O4EiEs3pLYi07OSkfMRsDkValZr9e j3vEXoCXtF3idgXUfIdn2QaRvU0xQtD7kCIcwSD4CuOk48Y/Fv+FFzvxoF7ErstXYLo5 YSnsNW9iDo93tBtqoiczARpm9wNs9uKxG9PFatHpess7oQhX2JCiyYrr3XSk398f1R9s auKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Cmk9snjFVJivgWjfslWczIKV+LYGTGnCXg+808OCaPc=; b=mOuj+4m4YEcGPq344LDegrjpt9+QsF4/o298keAoUYRbCtDBjp7bRqQqZ0UROlSAGx IyWTONt0qynLl/qaHP7AI/K5Ur0aYW7TFlmdqqr/Ghqqnr0ndMJPDkQBxva4S549FOLX L8WAxKM10RGF0yFUpHUPacQM88y5cPGbaxlc6rVv1137dSF1xKuZatGYWLQW6Gz3gHLL vsAIerOBWBAxLBJgXucRuS1O8CBHaoge85uhkLWvDzxMss0yYLep6GLoqG2FmsSRSU84 cAnAP5QKjrDtbhhPqTsvMXWalX1AJaRipXN5proXTGtNczycGd2QWgrgLfHHfYiLMcvO 8rMQ== X-Gm-Message-State: AHQUAubZGBVjk9wCFWsTeUp3rnFH+nMgS2w++6MQZLDqIzZDDjuviXrR ga9LAKKWRh9QyQCBIDsJXTxdUQ== X-Google-Smtp-Source: AHgI3IaEKhgTxXMPAzP0wOVIo/br5gZ53SSyCs/uC/fbu3Zxz0lMjd8qggShroPuxDSlqB0fVes1uw== X-Received: by 2002:a7b:cb9a:: with SMTP id m26mr2770572wmi.68.1550148680940; Thu, 14 Feb 2019 04:51:20 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 14 Feb 2019 12:51:03 +0000 Message-Id: <20190214125107.22178-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190214125107.22178-1-peter.maydell@linaro.org> References: <20190214125107.22178-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::333 Subject: [Qemu-devel] [PATCH 10/14] hw/arm/musca.c: Implement models of the Musca-A and -B1 boards X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The Musca-A and Musca-B1 development boards are based on the SSE-200 subsystem for embedded. Implement an initial skeleton model of these boards, which are similar but not identical. This commit creates the board model with the SSE and the IRQ splitters to wire IRQs up to its two CPUs. As yet there are no devices and no memory: these will be added later. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/arm/Makefile.objs | 1 + hw/arm/musca.c | 197 ++++++++++++++++++++++++++++++++ MAINTAINERS | 6 + default-configs/arm-softmmu.mak | 1 + 4 files changed, 205 insertions(+) create mode 100644 hw/arm/musca.c diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index fa40e8d6412..fa57c7c7704 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -35,6 +35,7 @@ obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_soc.o aspeed.o obj-$(CONFIG_MPS2) +=3D mps2.o obj-$(CONFIG_MPS2) +=3D mps2-tz.o obj-$(CONFIG_MSF2) +=3D msf2-soc.o msf2-som.o +obj-$(CONFIG_MUSCA) +=3D musca.o obj-$(CONFIG_ARMSSE) +=3D armsse.o obj-$(CONFIG_FSL_IMX7) +=3D fsl-imx7.o mcimx7d-sabre.o obj-$(CONFIG_ARM_SMMUV3) +=3D smmu-common.o smmuv3.o diff --git a/hw/arm/musca.c b/hw/arm/musca.c new file mode 100644 index 00000000000..cc624c7d160 --- /dev/null +++ b/hw/arm/musca.c @@ -0,0 +1,197 @@ +/* + * Arm Musca-B1 test chip board emulation + * + * Copyright (c) 2019 Linaro Limited + * Written by Peter Maydell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +/* + * The Musca boards are a reference implementation of a system using + * the SSE-200 subsystem for embedded: + * https://developer.arm.com/products/system-design/development-boards/iot= -test-chips-and-boards/musca-a-test-chip-board + * https://developer.arm.com/products/system-design/development-boards/iot= -test-chips-and-boards/musca-b-test-chip-board + * We model the A and B1 variants of this board, as described in the TRMs: + * http://infocenter.arm.com/help/topic/com.arm.doc.101107_0000_00_en/inde= x.html + * http://infocenter.arm.com/help/topic/com.arm.doc.101312_0000_00_en/inde= x.html + */ + +#include "qemu/osdep.h" +#include "qemu/error-report.h" +#include "qapi/error.h" +#include "exec/address-spaces.h" +#include "hw/arm/arm.h" +#include "hw/arm/armsse.h" +#include "hw/boards.h" +#include "hw/core/split-irq.h" + +#define MUSCA_NUMIRQ_MAX 96 + +typedef enum MuscaType { + MUSCA_A, + MUSCA_B1, +} MuscaType; + +typedef struct { + MachineClass parent; + MuscaType type; + uint32_t init_svtor; + int sram_addr_width; + int num_irqs; +} MuscaMachineClass; + +typedef struct { + MachineState parent; + + ARMSSE sse; + SplitIRQ cpu_irq_splitter[MUSCA_NUMIRQ_MAX]; +} MuscaMachineState; + +#define TYPE_MUSCA_MACHINE "musca" +#define TYPE_MUSCA_A_MACHINE MACHINE_TYPE_NAME("musca-a") +#define TYPE_MUSCA_B1_MACHINE MACHINE_TYPE_NAME("musca-b1") + +#define MUSCA_MACHINE(obj) \ + OBJECT_CHECK(MuscaMachineState, obj, TYPE_MUSCA_MACHINE) +#define MUSCA_MACHINE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(MuscaMachineClass, obj, TYPE_MUSCA_MACHINE) +#define MUSCA_MACHINE_CLASS(klass) \ + OBJECT_CLASS_CHECK(MuscaMachineClass, klass, TYPE_MUSCA_MACHINE) + +/* + * Main SYSCLK frequency in Hz + * TODO this should really be different for the two cores, but we + * don't model that in our SSE-200 model yet. + */ +#define SYSCLK_FRQ 40000000 + +static void musca_init(MachineState *machine) +{ + MuscaMachineState *mms =3D MUSCA_MACHINE(machine); + MuscaMachineClass *mmc =3D MUSCA_MACHINE_GET_CLASS(mms); + MachineClass *mc =3D MACHINE_GET_CLASS(machine); + MemoryRegion *system_memory =3D get_system_memory(); + DeviceState *ssedev; + int i; + + assert(mmc->num_irqs <=3D MUSCA_NUMIRQ_MAX); + + if (strcmp(machine->cpu_type, mc->default_cpu_type) !=3D 0) { + error_report("This board can only be used with CPU %s", + mc->default_cpu_type); + exit(1); + } + + sysbus_init_child_obj(OBJECT(machine), "sse-200", &mms->sse, + sizeof(mms->sse), TYPE_SSE200); + ssedev =3D DEVICE(&mms->sse); + object_property_set_link(OBJECT(&mms->sse), OBJECT(system_memory), + "memory", &error_fatal); + qdev_prop_set_uint32(ssedev, "EXP_NUMIRQ", mmc->num_irqs); + qdev_prop_set_uint32(ssedev, "init-svtor", mmc->init_svtor); + qdev_prop_set_uint32(ssedev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width); + qdev_prop_set_uint32(ssedev, "MAINCLK", SYSCLK_FRQ); + object_property_set_bool(OBJECT(&mms->sse), true, "realized", + &error_fatal); + + /* + * We need to create splitters to feed the IRQ inputs + * for each CPU in the SSE-200 from each device in the board. + */ + for (i =3D 0; i < mmc->num_irqs; i++) { + char *name =3D g_strdup_printf("musca-irq-splitter%d", i); + SplitIRQ *splitter =3D &mms->cpu_irq_splitter[i]; + + object_initialize_child(OBJECT(machine), name, + splitter, sizeof(*splitter), + TYPE_SPLIT_IRQ, &error_fatal, NULL); + g_free(name); + + object_property_set_int(OBJECT(splitter), 2, "num-lines", + &error_fatal); + object_property_set_bool(OBJECT(splitter), true, "realized", + &error_fatal); + qdev_connect_gpio_out(DEVICE(splitter), 0, + qdev_get_gpio_in_named(ssedev, "EXP_IRQ", i)= ); + qdev_connect_gpio_out(DEVICE(splitter), 1, + qdev_get_gpio_in_named(ssedev, + "EXP_CPU1_IRQ", i)); + } + + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x200= 0000); +} + +static void musca_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->default_cpus =3D 2; + mc->min_cpus =3D mc->default_cpus; + mc->max_cpus =3D mc->default_cpus; + mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m33"); + mc->init =3D musca_init; +} + +static void musca_a_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + MuscaMachineClass *mmc =3D MUSCA_MACHINE_CLASS(oc); + + mc->desc =3D "ARM Musca-A board (dual Cortex-M33)"; + mmc->type =3D MUSCA_A; + mmc->init_svtor =3D 0x10200000; + mmc->sram_addr_width =3D 15; + mmc->num_irqs =3D 64; +} + +static void musca_b1_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + MuscaMachineClass *mmc =3D MUSCA_MACHINE_CLASS(oc); + + mc->desc =3D "ARM Musca-B1 board (dual Cortex-M33)"; + mmc->type =3D MUSCA_B1; + /* + * This matches the DAPlink firmware which boots from QSPI. There + * is also a firmware blob which boots from the eFlash, which + * uses init_svtor =3D 0x1A000000. QEMU doesn't currently support that, + * though we could in theory expose a machine property on the command + * line to allow the user to request eFlash boot. + */ + mmc->init_svtor =3D 0x10000000; + mmc->sram_addr_width =3D 17; + mmc->num_irqs =3D 96; +} + +static const TypeInfo musca_info =3D { + .name =3D TYPE_MUSCA_MACHINE, + .parent =3D TYPE_MACHINE, + .abstract =3D true, + .instance_size =3D sizeof(MuscaMachineState), + .class_size =3D sizeof(MuscaMachineClass), + .class_init =3D musca_class_init, +}; + +static const TypeInfo musca_a_info =3D { + .name =3D TYPE_MUSCA_A_MACHINE, + .parent =3D TYPE_MUSCA_MACHINE, + .class_init =3D musca_a_class_init, +}; + +static const TypeInfo musca_b1_info =3D { + .name =3D TYPE_MUSCA_B1_MACHINE, + .parent =3D TYPE_MUSCA_MACHINE, + .class_init =3D musca_b1_class_init, +}; + +static void musca_machine_init(void) +{ + type_register_static(&musca_info); + type_register_static(&musca_a_info); + type_register_static(&musca_b1_info); +} + +type_init(musca_machine_init); diff --git a/MAINTAINERS b/MAINTAINERS index 85d4b4c9f7c..9b5042b883a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -636,6 +636,12 @@ F: include/hw/misc/iotkit-sysinfo.h F: hw/misc/armsse-cpuid.c F: include/hw/misc/armsse-cpuid.h =20 +Musca +M: Peter Maydell +L: qemu-arm@nongnu.org +S: Maintained +F: hw/arm/musca.c + Musicpal M: Jan Kiszka M: Peter Maydell diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.= mak index 734ca721e9e..87ad2674946 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -89,6 +89,7 @@ CONFIG_TUSB6010=3Dy CONFIG_IMX=3Dy CONFIG_MAINSTONE=3Dy CONFIG_MPS2=3Dy +CONFIG_MUSCA=3Dy CONFIG_NSERIES=3Dy CONFIG_RASPI=3Dy CONFIG_REALVIEW=3Dy --=20 2.20.1 From nobody Sat Nov 8 06:03:08 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1550149694989393.3141880396423; Thu, 14 Feb 2019 05:08:14 -0800 (PST) Received: from localhost ([127.0.0.1]:48318 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1guGkN-0007Xq-Qm for importer@patchew.org; Thu, 14 Feb 2019 08:08:11 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49748) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1guGeQ-0002vd-JI for qemu-devel@nongnu.org; Thu, 14 Feb 2019 08:02:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1guGUW-0006yg-If for qemu-devel@nongnu.org; Thu, 14 Feb 2019 07:51:54 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:46427) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1guGUR-0006fa-HX for qemu-devel@nongnu.org; Thu, 14 Feb 2019 07:51:46 -0500 Received: by mail-wr1-x443.google.com with SMTP id l9so6308990wrt.13 for ; Thu, 14 Feb 2019 04:51:23 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j3sm1488073wmb.39.2019.02.14.04.51.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Feb 2019 04:51:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wx+BYpvHTW57CyXGJ3HudXtRv2dk+GGAZ3zOw47Rw9I=; b=M3l+fQYoOO5SzX3Fyu4sAkXuBkZf3FzJ5ASsuxfv++NmA7lBb67Xw4QoQqCNoyKrg2 EKh0fH1DjggwXP3ta4ana7uma2grGjQ1Os/KSASPZl7zLB9yxAUJlxfIVieK/E/0hxA3 04CrYdWTGsIcmB48ub+/4ksgUwklyBf72RRRiJXZAc44vVSkOw1tbb9Iy3Rm6/ddDWUW b9Aq6he96L9I60IcLvQXl6bjqjhl/3ismN6AL4et6AzvZfI3SNU5biot1d3a1E+GHj8C /PQ5BRsPOIadpeAEltWgQRVI1j3xwW6asVuQpYBqFr47A/4fd+Qkf4qtx73D+KgxUNlR NKYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wx+BYpvHTW57CyXGJ3HudXtRv2dk+GGAZ3zOw47Rw9I=; b=q1xurBhLGIukgMkM5kpbWRjwkucH+/tIyXMVwl6wS3g52P/RMfXM36zvODvCFV61yG b/ghQABBBdk6ZKurJYh5/xShSsQqDuEpZKjbRR6FMnICTO8ewMdk+oVbSjCZ09m18khR vOYnU4emPzAZkl9SMM3mda+JTk26iqEfSyR96hanwKYF736JUn2dBXu9xZ8fjgVdLvJZ oGEhltMWsaTBD7ps2llmlIRlMYaitVM/VrQqSuRONCQARGeqi8aHYCSMCdNuPtFE9cvP g6wDh+gKYD2qOTVVGX5nff/nlT3Ykn3L2uH0sJRgfMNYJQo0TJWN6LxtwOpUJcMPmask Lspg== X-Gm-Message-State: AHQUAuZQjOXZvzHx9d1eaRBF0oCezHkyX3nldQkBS8WI6lnVZYy3/JXT JvqXY2UvZhl761AY57AJEUDyI4CmWDHASw== X-Google-Smtp-Source: AHgI3IYzA0UztR0Yocth+LE77RFtK5S5c1gwRDTXuUxaVYzvEVdQP8fYEzVvCKGLjhAStrwcKPGPlQ== X-Received: by 2002:adf:f388:: with SMTP id m8mr2923482wro.133.1550148682278; Thu, 14 Feb 2019 04:51:22 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 14 Feb 2019 12:51:04 +0000 Message-Id: <20190214125107.22178-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190214125107.22178-1-peter.maydell@linaro.org> References: <20190214125107.22178-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH 11/14] hw/arm/musca: Add PPCs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Many of the devices on the Musca board live behind TrustZone Peripheral Protection Controllers (PPCs); add models of the PPCs, using a similar scheme to the MPS2 board models. This commit wires up the PPCs with "unimplemented device" stubs behind them in the correct places in the address map. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/arm/musca.c | 289 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 289 insertions(+) diff --git a/hw/arm/musca.c b/hw/arm/musca.c index cc624c7d160..8774e0b87b7 100644 --- a/hw/arm/musca.c +++ b/hw/arm/musca.c @@ -27,8 +27,11 @@ #include "hw/arm/armsse.h" #include "hw/boards.h" #include "hw/core/split-irq.h" +#include "hw/misc/tz-ppc.h" +#include "hw/misc/unimp.h" =20 #define MUSCA_NUMIRQ_MAX 96 +#define MUSCA_PPC_MAX 3 =20 typedef enum MuscaType { MUSCA_A, @@ -48,6 +51,24 @@ typedef struct { =20 ARMSSE sse; SplitIRQ cpu_irq_splitter[MUSCA_NUMIRQ_MAX]; + SplitIRQ sec_resp_splitter; + TZPPC ppc[MUSCA_PPC_MAX]; + MemoryRegion container; + UnimplementedDeviceState eflash[2]; + UnimplementedDeviceState qspi; + UnimplementedDeviceState mpc[5]; + UnimplementedDeviceState mhu[2]; + UnimplementedDeviceState pwm[3]; + UnimplementedDeviceState i2s; + UnimplementedDeviceState uart[2]; + UnimplementedDeviceState i2c[2]; + UnimplementedDeviceState spi; + UnimplementedDeviceState scc; + UnimplementedDeviceState timer; + UnimplementedDeviceState rtc; + UnimplementedDeviceState pvt; + UnimplementedDeviceState sdio; + UnimplementedDeviceState gpio; } MuscaMachineState; =20 #define TYPE_MUSCA_MACHINE "musca" @@ -68,6 +89,94 @@ typedef struct { */ #define SYSCLK_FRQ 40000000 =20 +/* + * Most of the devices in the Musca board sit behind Peripheral Protection + * Controllers. These data structures define the layout of which devices + * sit behind which PPCs. + * The devfn for each port is a function which creates, configures + * and initializes the device, returning the MemoryRegion which + * needs to be plugged into the downstream end of the PPC port. + */ +typedef MemoryRegion *MakeDevFn(MuscaMachineState *mms, void *opaque, + const char *name, hwaddr size); + +typedef struct PPCPortInfo { + const char *name; + MakeDevFn *devfn; + void *opaque; + hwaddr addr; + hwaddr size; +} PPCPortInfo; + +typedef struct PPCInfo { + const char *name; + PPCPortInfo ports[TZ_NUM_PORTS]; +} PPCInfo; + +static MemoryRegion *make_unimp_dev(MuscaMachineState *mms, + void *opaque, const char *name, hwaddr= size) +{ + /* + * Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE, + * and return a pointer to its MemoryRegion. + */ + UnimplementedDeviceState *uds =3D opaque; + + sysbus_init_child_obj(OBJECT(mms), name, uds, + sizeof(UnimplementedDeviceState), + TYPE_UNIMPLEMENTED_DEVICE); + qdev_prop_set_string(DEVICE(uds), "name", name); + qdev_prop_set_uint64(DEVICE(uds), "size", size); + object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal); + return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0); +} + +static MemoryRegion *make_musca_a_devs(MuscaMachineState *mms, void *opaqu= e, + const char *name, hwaddr size) +{ + /* + * Create the container MemoryRegion for all the devices that live + * behind the Musca-A PPC's single port. These devices don't have a PPC + * port each, but we use the PPCPortInfo struct as a convenient way + * to describe them. Note that addresses here are relative to the base + * address of the PPC port region: 0x40100000, and devices appear both + * at the 0x4... NS region and the 0x5... S region. + */ + int i; + MemoryRegion *container =3D &mms->container; + + const PPCPortInfo devices[] =3D { + { "uart0", make_unimp_dev, &mms->uart[0], 0x1000, 0x1000 }, + { "uart1", make_unimp_dev, &mms->uart[1], 0x2000, 0x1000 }, + { "spi", make_unimp_dev, &mms->spi, 0x3000, 0x1000 }, + { "i2c0", make_unimp_dev, &mms->i2c[0], 0x4000, 0x1000 }, + { "i2c1", make_unimp_dev, &mms->i2c[1], 0x5000, 0x1000 }, + { "i2s", make_unimp_dev, &mms->i2s, 0x6000, 0x1000 }, + { "pwm0", make_unimp_dev, &mms->pwm[0], 0x7000, 0x1000 }, + { "rtc", make_unimp_dev, &mms->rtc, 0x8000, 0x1000 }, + { "qspi", make_unimp_dev, &mms->qspi, 0xa000, 0x1000 }, + { "timer", make_unimp_dev, &mms->timer, 0xb000, 0x1000 }, + { "scc", make_unimp_dev, &mms->scc, 0xc000, 0x1000 }, + { "pwm1", make_unimp_dev, &mms->pwm[1], 0xe000, 0x1000 }, + { "pwm2", make_unimp_dev, &mms->pwm[2], 0xf000, 0x1000 }, + { "gpio", make_unimp_dev, &mms->gpio, 0x10000, 0x1000 }, + { "mpc0", make_unimp_dev, &mms->mpc[0], 0x12000, 0x1000 }, + { "mpc1", make_unimp_dev, &mms->mpc[1], 0x13000, 0x1000 }, + }; + + memory_region_init(container, OBJECT(mms), "musca-device-container", s= ize); + + for (i =3D 0; i < ARRAY_SIZE(devices); i++) { + const PPCPortInfo *pinfo =3D &devices[i]; + MemoryRegion *mr; + + mr =3D pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size); + memory_region_add_subregion(container, pinfo->addr, mr); + } + + return &mms->container; +} + static void musca_init(MachineState *machine) { MuscaMachineState *mms =3D MUSCA_MACHINE(machine); @@ -75,6 +184,9 @@ static void musca_init(MachineState *machine) MachineClass *mc =3D MACHINE_GET_CLASS(machine); MemoryRegion *system_memory =3D get_system_memory(); DeviceState *ssedev; + DeviceState *dev_splitter; + const PPCInfo *ppcs; + int num_ppcs; int i; =20 assert(mmc->num_irqs <=3D MUSCA_NUMIRQ_MAX); @@ -121,6 +233,183 @@ static void musca_init(MachineState *machine) "EXP_CPU1_IRQ", i)); } =20 + /* + * The sec_resp_cfg output from the SSE-200 must be split into multiple + * lines, one for each of the PPCs we create here. + */ + object_initialize(&mms->sec_resp_splitter, sizeof(mms->sec_resp_splitt= er), + TYPE_SPLIT_IRQ); + object_property_add_child(OBJECT(machine), "sec-resp-splitter", + OBJECT(&mms->sec_resp_splitter), &error_fata= l); + object_property_set_int(OBJECT(&mms->sec_resp_splitter), + ARRAY_SIZE(mms->ppc), "num-lines", &error_fata= l); + object_property_set_bool(OBJECT(&mms->sec_resp_splitter), true, + "realized", &error_fatal); + dev_splitter =3D DEVICE(&mms->sec_resp_splitter); + qdev_connect_gpio_out_named(ssedev, "sec_resp_cfg", 0, + qdev_get_gpio_in(dev_splitter, 0)); + + /* + * Most of the devices in the board are behind Peripheral Protection + * Controllers. The required order for initializing things is: + * + initialize the PPC + * + initialize, configure and realize downstream devices + * + connect downstream device MemoryRegions to the PPC + * + realize the PPC + * + map the PPC's MemoryRegions to the places in the address map + * where the downstream devices should appear + * + wire up the PPC's control lines to the SSE object + * + * The PPC mapping differs for the -A and -B1 variants; the -A version + * is much simpler, using only a single port of a single PPC and putti= ng + * all the devices behind that. + */ + const PPCInfo a_ppcs[] =3D { { + .name =3D "ahb_ppcexp0", + .ports =3D { + { "musca-devices", make_musca_a_devs, 0, 0x40100000, 0x100= 000 }, + }, + }, + }; + + /* + * Devices listed with an 0x4.. address appear in both the NS 0x4.. re= gion + * and the 0x5.. S region. Devices listed with an 0x5.. address appear + * only in the S region. + */ + const PPCInfo b1_ppcs[] =3D { { + .name =3D "apb_ppcexp0", + .ports =3D { + { "eflash0", make_unimp_dev, &mms->eflash[0], + 0x52400000, 0x1000 }, + { "eflash1", make_unimp_dev, &mms->eflash[1], + 0x52500000, 0x1000 }, + { "qspi", make_unimp_dev, &mms->qspi, 0x42800000, 0x100000= }, + { "mpc0", make_unimp_dev, &mms->mpc[0], 0x52000000, 0x1000= }, + { "mpc1", make_unimp_dev, &mms->mpc[1], 0x52100000, 0x1000= }, + { "mpc2", make_unimp_dev, &mms->mpc[2], 0x52200000, 0x1000= }, + { "mpc3", make_unimp_dev, &mms->mpc[3], 0x52300000, 0x1000= }, + { "mhu0", make_unimp_dev, &mms->mhu[0], 0x42600000, 0x1000= 00 }, + { "mhu1", make_unimp_dev, &mms->mhu[1], 0x42700000, 0x1000= 00 }, + { }, /* port 9: unused */ + { }, /* port 10: unused */ + { }, /* port 11: unused */ + { }, /* port 12: unused */ + { }, /* port 13: unused */ + { "mpc4", make_unimp_dev, &mms->mpc[4], 0x52e00000, 0x1000= }, + }, + }, { + .name =3D "apb_ppcexp1", + .ports =3D { + { "pwm0", make_unimp_dev, &mms->pwm[0], 0x40101000, 0x1000= }, + { "pwm1", make_unimp_dev, &mms->pwm[1], 0x40102000, 0x1000= }, + { "pwm2", make_unimp_dev, &mms->pwm[2], 0x40103000, 0x1000= }, + { "i2s", make_unimp_dev, &mms->i2s, 0x40104000, 0x1000 }, + { "uart0", make_unimp_dev, &mms->uart[0], 0x40105000, 0x10= 00 }, + { "uart1", make_unimp_dev, &mms->uart[1], 0x40106000, 0x10= 00 }, + { "i2c0", make_unimp_dev, &mms->i2c[0], 0x40108000, 0x1000= }, + { "i2c1", make_unimp_dev, &mms->i2c[1], 0x40109000, 0x1000= }, + { "spi", make_unimp_dev, &mms->spi, 0x4010a000, 0x1000 }, + { "scc", make_unimp_dev, &mms->scc, 0x5010b000, 0x1000 }, + { "timer", make_unimp_dev, &mms->timer, 0x4010c000, 0x1000= }, + { "rtc", make_unimp_dev, &mms->rtc, 0x4010d000, 0x1000 }, + { "pvt", make_unimp_dev, &mms->pvt, 0x4010e000, 0x1000 }, + { "sdio", make_unimp_dev, &mms->sdio, 0x4010f000, 0x1000 }, + }, + }, { + .name =3D "ahb_ppcexp0", + .ports =3D { + { }, /* port 0: unused */ + { "gpio", make_unimp_dev, &mms->gpio, 0x41000000, 0x1000 }, + }, + }, + }; + + switch (mmc->type) { + case MUSCA_A: + ppcs =3D a_ppcs; + num_ppcs =3D ARRAY_SIZE(a_ppcs); + break; + case MUSCA_B1: + ppcs =3D b1_ppcs; + num_ppcs =3D ARRAY_SIZE(b1_ppcs); + break; + default: + g_assert_not_reached(); + } + assert(num_ppcs <=3D MUSCA_PPC_MAX); + + for (i =3D 0; i < num_ppcs; i++) { + const PPCInfo *ppcinfo =3D &ppcs[i]; + TZPPC *ppc =3D &mms->ppc[i]; + DeviceState *ppcdev; + int port; + char *gpioname; + + sysbus_init_child_obj(OBJECT(machine), ppcinfo->name, ppc, + sizeof(TZPPC), TYPE_TZ_PPC); + ppcdev =3D DEVICE(ppc); + + for (port =3D 0; port < TZ_NUM_PORTS; port++) { + const PPCPortInfo *pinfo =3D &ppcinfo->ports[port]; + MemoryRegion *mr; + char *portname; + + if (!pinfo->devfn) { + continue; + } + + mr =3D pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->si= ze); + portname =3D g_strdup_printf("port[%d]", port); + object_property_set_link(OBJECT(ppc), OBJECT(mr), + portname, &error_fatal); + g_free(portname); + } + + object_property_set_bool(OBJECT(ppc), true, "realized", &error_fat= al); + + for (port =3D 0; port < TZ_NUM_PORTS; port++) { + const PPCPortInfo *pinfo =3D &ppcinfo->ports[port]; + + if (!pinfo->devfn) { + continue; + } + sysbus_mmio_map(SYS_BUS_DEVICE(ppc), port, pinfo->addr); + + gpioname =3D g_strdup_printf("%s_nonsec", ppcinfo->name); + qdev_connect_gpio_out_named(ssedev, gpioname, port, + qdev_get_gpio_in_named(ppcdev, + "cfg_nonsec= ", + port)); + g_free(gpioname); + gpioname =3D g_strdup_printf("%s_ap", ppcinfo->name); + qdev_connect_gpio_out_named(ssedev, gpioname, port, + qdev_get_gpio_in_named(ppcdev, + "cfg_ap", p= ort)); + g_free(gpioname); + } + + gpioname =3D g_strdup_printf("%s_irq_enable", ppcinfo->name); + qdev_connect_gpio_out_named(ssedev, gpioname, 0, + qdev_get_gpio_in_named(ppcdev, + "irq_enable", 0= )); + g_free(gpioname); + gpioname =3D g_strdup_printf("%s_irq_clear", ppcinfo->name); + qdev_connect_gpio_out_named(ssedev, gpioname, 0, + qdev_get_gpio_in_named(ppcdev, + "irq_clear", 0)= ); + g_free(gpioname); + gpioname =3D g_strdup_printf("%s_irq_status", ppcinfo->name); + qdev_connect_gpio_out_named(ppcdev, "irq", 0, + qdev_get_gpio_in_named(ssedev, + gpioname, 0)); + g_free(gpioname); + + qdev_connect_gpio_out(dev_splitter, i, + qdev_get_gpio_in_named(ppcdev, + "cfg_sec_resp", 0)); + } + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x200= 0000); } =20 --=20 2.20.1 From nobody Sat Nov 8 06:03:08 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1550150090164644.93405852542; Thu, 14 Feb 2019 05:14:50 -0800 (PST) Received: from localhost ([127.0.0.1]:48423 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1guGqi-0004Qv-2W for importer@patchew.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j3sm1488073wmb.39.2019.02.14.04.51.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Feb 2019 04:51:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SAS7c3NHgx+SQKlm+sDAr0gChkJR6CgxyAh5pRIpxIM=; b=o0rYZSBTLaUG5q49MQoTySeXjvJGCyjkaUCm5W0lnzfC0B0xHfbD7Bk2F36fgLgi77 fBTqT5/P2uRc01nX7ROaRk/ipcRQgQHhxza6P5COmWudUS5ThD95X+0C1+XaD7FCH/VP YIZ6VWUJIePQKWcabgsI08hB1zw5wSxCiRxJMXsPWF5ra+OHYRc2vDvuHY0jXKUqdTWN t7rtIw5U/irtrxH0UHk4T9IRFQQEwM8FqDLJjDTBx/O5CGwC0u3NGLxUbBYl61N+4rNc jUB0XKrOitSaA+AUKFMl515HS37Afj5TlYIFg6EVvzmhzKA4otOBK3g4nvnabLNvzb80 388A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SAS7c3NHgx+SQKlm+sDAr0gChkJR6CgxyAh5pRIpxIM=; b=ogll+QUBTAKlQ4ZBapbQJoY6ggCGgT3UwEdIYeoe/7mKiLx7unUw1HYdeorMgUjmf4 rM16lRBn5LIeyi6VSafvL16DTYpvH1lxjkFa6OkwJ0HkA8Fh9j3Uz60VPdcxbg8aGoVn q3ryxslrByfpJeWij+CLMpssz4ir2STQE2Jq4nIL86qQfccDGjRUwvEr2TVYQ1JUYa01 NRWGhA7kbn8/nQ7npnJF96iF28+ogY5OsqA3OF7Hk8ZDpc2Le/nf9iZlGr57z+dL5aDu 43Wq4jvXQEO7M8sE40gGWcn17IlP5TAWvjHyFiteiidRz03PUnlo0TzQJ26/+EU4Mjdk ufgA== X-Gm-Message-State: AHQUAuYAKK40ozJK9oGFu7TqJjarBfc9mOHbTnr7FVmFAYaHKkMw6b88 DzNS7pXixh7KooZrwhzNinrl0cfFSv61YQ== X-Google-Smtp-Source: AHgI3IZ8oNdbkE78SOksSf0a/ilJK49vf0CVamuN4cIStCLIRnObKVo3b/o3iqpxX6T5+BLKZmP1Cg== X-Received: by 2002:adf:a147:: with SMTP id r7mr2668837wrr.5.1550148683574; Thu, 14 Feb 2019 04:51:23 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 14 Feb 2019 12:51:05 +0000 Message-Id: <20190214125107.22178-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190214125107.22178-1-peter.maydell@linaro.org> References: <20190214125107.22178-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH 12/14] hw/arm/musca: Add MPCs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The Musca board puts its SRAM and flash behind TrustZone Memory Protection Controllers (MPCs). Each MPC sits between the CPU and the RAM/flash, and also has a set of memory mapped control registers. Wire up the MPCs, and the memory behind them. For the moment we implement the flash as simple ROM, which cannot be reprogrammed by the guest. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/arm/musca.c | 155 ++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 147 insertions(+), 8 deletions(-) diff --git a/hw/arm/musca.c b/hw/arm/musca.c index 8774e0b87b7..5fadac8c09b 100644 --- a/hw/arm/musca.c +++ b/hw/arm/musca.c @@ -27,11 +27,15 @@ #include "hw/arm/armsse.h" #include "hw/boards.h" #include "hw/core/split-irq.h" +#include "hw/misc/tz-mpc.h" #include "hw/misc/tz-ppc.h" #include "hw/misc/unimp.h" =20 #define MUSCA_NUMIRQ_MAX 96 #define MUSCA_PPC_MAX 3 +#define MUSCA_MPC_MAX 5 + +typedef struct MPCInfo MPCInfo; =20 typedef enum MuscaType { MUSCA_A, @@ -44,19 +48,23 @@ typedef struct { uint32_t init_svtor; int sram_addr_width; int num_irqs; + const MPCInfo *mpc_info; + int num_mpcs; } MuscaMachineClass; =20 typedef struct { MachineState parent; =20 ARMSSE sse; + /* RAM and flash */ + MemoryRegion ram[MUSCA_MPC_MAX]; SplitIRQ cpu_irq_splitter[MUSCA_NUMIRQ_MAX]; SplitIRQ sec_resp_splitter; TZPPC ppc[MUSCA_PPC_MAX]; MemoryRegion container; UnimplementedDeviceState eflash[2]; UnimplementedDeviceState qspi; - UnimplementedDeviceState mpc[5]; + TZMPC mpc[MUSCA_MPC_MAX]; UnimplementedDeviceState mhu[2]; UnimplementedDeviceState pwm[3]; UnimplementedDeviceState i2s; @@ -69,6 +77,7 @@ typedef struct { UnimplementedDeviceState pvt; UnimplementedDeviceState sdio; UnimplementedDeviceState gpio; + UnimplementedDeviceState cryptoisland; } MuscaMachineState; =20 #define TYPE_MUSCA_MACHINE "musca" @@ -131,6 +140,131 @@ static MemoryRegion *make_unimp_dev(MuscaMachineState= *mms, return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0); } =20 +typedef enum MPCInfoType { + MPC_RAM, + MPC_ROM, + MPC_CRYPTOISLAND, +} MPCInfoType; + +typedef struct MPCInfo { + const char *name; + hwaddr addr; + hwaddr size; + MPCInfoType type; +} MPCInfo; + +/* Order of the MPCs here must match the order of the bits in SECMPCINTSTA= TUS */ +static const MPCInfo a_mpc_info[] =3D { { + .name =3D "qspi", + .type =3D MPC_ROM, + .addr =3D 0x00200000, + .size =3D 0x00800000, + }, { + .name =3D "sram", + .type =3D MPC_RAM, + .addr =3D 0x00000000, + .size =3D 0x00200000, + } +}; + +static const MPCInfo b1_mpc_info[] =3D { { + .name =3D "qspi", + .type =3D MPC_ROM, + .addr =3D 0x00000000, + .size =3D 0x02000000, + }, { + .name =3D "sram", + .type =3D MPC_RAM, + .addr =3D 0x0a400000, + .size =3D 0x00080000, + }, { + .name =3D "eflash0", + .type =3D MPC_ROM, + .addr =3D 0x0a000000, + .size =3D 0x00200000, + }, { + .name =3D "eflash1", + .type =3D MPC_ROM, + .addr =3D 0x0a200000, + .size =3D 0x00200000, + }, { + .name =3D "cryptoisland", + .type =3D MPC_CRYPTOISLAND, + .addr =3D 0x0a000000, + .size =3D 0x00200000, + } +}; + +static MemoryRegion *make_mpc(MuscaMachineState *mms, void *opaque, + const char *name, hwaddr size) +{ + /* + * Create an MPC and the RAM or flash behind it. + * MPC 0: eFlash 0 + * MPC 1: eFlash 1 + * MPC 2: SRAM + * MPC 3: QSPI flash + * MPC 4: CryptoIsland + * For now we implement the flash regions as ROM (ie not programmable) + * (with their control interface memory regions being unimplemented + * stubs behind the PPCs). + * The whole CryptoIsland region behind its MPC is an unimplemented st= ub. + */ + MuscaMachineClass *mmc =3D MUSCA_MACHINE_GET_CLASS(mms); + TZMPC *mpc =3D opaque; + int i =3D mpc - &mms->mpc[0]; + MemoryRegion *downstream; + MemoryRegion *upstream; + UnimplementedDeviceState *uds; + char *mpcname; + const MPCInfo *mpcinfo =3D mmc->mpc_info; + + mpcname =3D g_strdup_printf("%s-mpc", mpcinfo[i].name); + + switch (mpcinfo[i].type) { + case MPC_ROM: + downstream =3D &mms->ram[i]; + memory_region_init_rom(downstream, NULL, mpcinfo[i].name, + mpcinfo[i].size, &error_fatal); + break; + case MPC_RAM: + downstream =3D &mms->ram[i]; + memory_region_init_ram(downstream, NULL, mpcinfo[i].name, + mpcinfo[i].size, &error_fatal); + break; + case MPC_CRYPTOISLAND: + /* We don't implement the CryptoIsland yet */ + uds =3D &mms->cryptoisland; + sysbus_init_child_obj(OBJECT(mms), name, uds, + sizeof(UnimplementedDeviceState), + TYPE_UNIMPLEMENTED_DEVICE); + qdev_prop_set_string(DEVICE(uds), "name", mpcinfo[i].name); + qdev_prop_set_uint64(DEVICE(uds), "size", mpcinfo[i].size); + object_property_set_bool(OBJECT(uds), true, "realized", &error_fat= al); + downstream =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0); + break; + default: + g_assert_not_reached(); + } + + sysbus_init_child_obj(OBJECT(mms), mpcname, mpc, sizeof(mms->mpc[0]), + TYPE_TZ_MPC); + object_property_set_link(OBJECT(mpc), OBJECT(downstream), + "downstream", &error_fatal); + object_property_set_bool(OBJECT(mpc), true, "realized", &error_fatal); + /* Map the upstream end of the MPC into system memory */ + upstream =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); + memory_region_add_subregion(get_system_memory(), mpcinfo[i].addr, upst= ream); + /* and connect its interrupt to the SSE-200 */ + qdev_connect_gpio_out_named(DEVICE(mpc), "irq", 0, + qdev_get_gpio_in_named(DEVICE(&mms->sse), + "mpcexp_status", i)= ); + + g_free(mpcname); + /* Return the register interface MR for our caller to map behind the P= PC */ + return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0); +} + static MemoryRegion *make_musca_a_devs(MuscaMachineState *mms, void *opaqu= e, const char *name, hwaddr size) { @@ -160,8 +294,8 @@ static MemoryRegion *make_musca_a_devs(MuscaMachineStat= e *mms, void *opaque, { "pwm1", make_unimp_dev, &mms->pwm[1], 0xe000, 0x1000 }, { "pwm2", make_unimp_dev, &mms->pwm[2], 0xf000, 0x1000 }, { "gpio", make_unimp_dev, &mms->gpio, 0x10000, 0x1000 }, - { "mpc0", make_unimp_dev, &mms->mpc[0], 0x12000, 0x1000 }, - { "mpc1", make_unimp_dev, &mms->mpc[1], 0x13000, 0x1000 }, + { "mpc0", make_mpc, &mms->mpc[0], 0x12000, 0x1000 }, + { "mpc1", make_mpc, &mms->mpc[1], 0x13000, 0x1000 }, }; =20 memory_region_init(container, OBJECT(mms), "musca-device-container", s= ize); @@ -190,6 +324,7 @@ static void musca_init(MachineState *machine) int i; =20 assert(mmc->num_irqs <=3D MUSCA_NUMIRQ_MAX); + assert(mmc->num_mpcs <=3D MUSCA_MPC_MAX); =20 if (strcmp(machine->cpu_type, mc->default_cpu_type) !=3D 0) { error_report("This board can only be used with CPU %s", @@ -285,10 +420,10 @@ static void musca_init(MachineState *machine) { "eflash1", make_unimp_dev, &mms->eflash[1], 0x52500000, 0x1000 }, { "qspi", make_unimp_dev, &mms->qspi, 0x42800000, 0x100000= }, - { "mpc0", make_unimp_dev, &mms->mpc[0], 0x52000000, 0x1000= }, - { "mpc1", make_unimp_dev, &mms->mpc[1], 0x52100000, 0x1000= }, - { "mpc2", make_unimp_dev, &mms->mpc[2], 0x52200000, 0x1000= }, - { "mpc3", make_unimp_dev, &mms->mpc[3], 0x52300000, 0x1000= }, + { "mpc0", make_mpc, &mms->mpc[0], 0x52000000, 0x1000 }, + { "mpc1", make_mpc, &mms->mpc[1], 0x52100000, 0x1000 }, + { "mpc2", make_mpc, &mms->mpc[2], 0x52200000, 0x1000 }, + { "mpc3", make_mpc, &mms->mpc[3], 0x52300000, 0x1000 }, { "mhu0", make_unimp_dev, &mms->mhu[0], 0x42600000, 0x1000= 00 }, { "mhu1", make_unimp_dev, &mms->mhu[1], 0x42700000, 0x1000= 00 }, { }, /* port 9: unused */ @@ -296,7 +431,7 @@ static void musca_init(MachineState *machine) { }, /* port 11: unused */ { }, /* port 12: unused */ { }, /* port 13: unused */ - { "mpc4", make_unimp_dev, &mms->mpc[4], 0x52e00000, 0x1000= }, + { "mpc4", make_mpc, &mms->mpc[4], 0x52e00000, 0x1000 }, }, }, { .name =3D "apb_ppcexp1", @@ -434,6 +569,8 @@ static void musca_a_class_init(ObjectClass *oc, void *d= ata) mmc->init_svtor =3D 0x10200000; mmc->sram_addr_width =3D 15; mmc->num_irqs =3D 64; + mmc->mpc_info =3D a_mpc_info; + mmc->num_mpcs =3D ARRAY_SIZE(a_mpc_info); } =20 static void musca_b1_class_init(ObjectClass *oc, void *data) @@ -453,6 +590,8 @@ static void musca_b1_class_init(ObjectClass *oc, void *= data) mmc->init_svtor =3D 0x10000000; mmc->sram_addr_width =3D 17; mmc->num_irqs =3D 96; + mmc->mpc_info =3D b1_mpc_info; + mmc->num_mpcs =3D ARRAY_SIZE(b1_mpc_info); } =20 static const TypeInfo musca_info =3D { --=20 2.20.1 From nobody Sat Nov 8 06:03:08 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1550149666302173.09864128156232; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j3sm1488073wmb.39.2019.02.14.04.51.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Feb 2019 04:51:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fPHjh0vcD+s+CvwW5rloGqyfYyS+yolZGFn/O41zExg=; b=CJ2gk9o8AkB2+K7FMlmN4yNzeVcbZiMH7mupkS/ToqRV/qSeSkfCjD1ukhP3NVht8t xm/0A2aKXV4l+y5d8PVh0rGCdfb1JYgjfWCVggo4X9KC8b/Dp9EoiLGAhTQS1qTQnRDg R+ZA+4aQjPORvrvpR4vrC2yyaIhsRoK8g2dDqDUCgAP2UiXKLyS4yyCgG+GCRkC+1/9z JqGYkUzOnkj4su8bx/SqyP5O3bhYiGMOc1TfhVio8JIU+VEPIzThjQBQw1tfwOsA7AWT 3sCsEnBtdAGVJm1DHVEqj+XekOiD8Ni5w7lvQp/W6sc8vODqe1tiEBWmLRDPkXUtPkZb bq6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fPHjh0vcD+s+CvwW5rloGqyfYyS+yolZGFn/O41zExg=; b=GLSrgLmISANYtoqI4W0MzhHEPj1BsUymqu7WUXSfVf3G/Iew5mAe5sJeXEz81ivW5M bRsFneBZcXLbGvh2YwJCCC8TrrhLz+gq7d3dZawNwL8KICsHhqhTQG99TA00sgMcXo1o GO1ymZ5PQ0mr+uE0HCY4UrpCCSmYRopAD7cOM2N2mi3zqVUpT6KQiBlhqS4uE0urqDFP yiV7kc4aAQXHWVo6BmJ27gys/QFyzSqKP72ZFXUTaX2lZnrfZ5n9z7k63CmD39Jka5GD SY3grekAZIPSAQM7BzW/Iju6tXwG6J1X7ptqKyZt3i9cOYGitYp6SBNLGrgDtJkzpchA YJfg== X-Gm-Message-State: AHQUAubgylFP2yTUrt/HgwqJOHO3flW1afEBmuF1MP5i/Ac3M0r5u02J smeO0PUOyUujzhh/NbG1mWnU2jsCZuTh8A== X-Google-Smtp-Source: AHgI3IaHfwyJbWcOQDQld1eQooUpAkdSfEir3Y6geabb1Z77oVe4O6FCdMT3TYpY4RD6k9P8Czl/aw== X-Received: by 2002:adf:f80c:: with SMTP id s12mr2644877wrp.150.1550148684789; Thu, 14 Feb 2019 04:51:24 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 14 Feb 2019 12:51:06 +0000 Message-Id: <20190214125107.22178-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190214125107.22178-1-peter.maydell@linaro.org> References: <20190214125107.22178-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH 13/14] hw/arm/musca: Wire up PL031 RTC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Wire up the PL031 RTC for the Musca board. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/arm/musca.c | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/hw/arm/musca.c b/hw/arm/musca.c index 5fadac8c09b..ec8dfee1964 100644 --- a/hw/arm/musca.c +++ b/hw/arm/musca.c @@ -30,6 +30,7 @@ #include "hw/misc/tz-mpc.h" #include "hw/misc/tz-ppc.h" #include "hw/misc/unimp.h" +#include "hw/timer/pl031.h" =20 #define MUSCA_NUMIRQ_MAX 96 #define MUSCA_PPC_MAX 3 @@ -73,7 +74,7 @@ typedef struct { UnimplementedDeviceState spi; UnimplementedDeviceState scc; UnimplementedDeviceState timer; - UnimplementedDeviceState rtc; + PL031State rtc; UnimplementedDeviceState pvt; UnimplementedDeviceState sdio; UnimplementedDeviceState gpio; @@ -98,6 +99,14 @@ typedef struct { */ #define SYSCLK_FRQ 40000000 =20 +static qemu_irq get_sse_irq_in(MuscaMachineState *mms, int irqno) +{ + /* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */ + assert(irqno < MUSCA_NUMIRQ_MAX); + + return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); +} + /* * Most of the devices in the Musca board sit behind Peripheral Protection * Controllers. These data structures define the layout of which devices @@ -265,6 +274,17 @@ static MemoryRegion *make_mpc(MuscaMachineState *mms, = void *opaque, return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0); } =20 +static MemoryRegion *make_rtc(MuscaMachineState *mms, void *opaque, + const char *name, hwaddr size) +{ + PL031State *rtc =3D opaque; + + sysbus_init_child_obj(OBJECT(mms), name, rtc, sizeof(mms->rtc), TYPE_P= L031); + object_property_set_bool(OBJECT(rtc), true, "realized", &error_fatal); + sysbus_connect_irq(SYS_BUS_DEVICE(rtc), 0, get_sse_irq_in(mms, 39)); + return sysbus_mmio_get_region(SYS_BUS_DEVICE(rtc), 0); +} + static MemoryRegion *make_musca_a_devs(MuscaMachineState *mms, void *opaqu= e, const char *name, hwaddr size) { @@ -287,7 +307,7 @@ static MemoryRegion *make_musca_a_devs(MuscaMachineStat= e *mms, void *opaque, { "i2c1", make_unimp_dev, &mms->i2c[1], 0x5000, 0x1000 }, { "i2s", make_unimp_dev, &mms->i2s, 0x6000, 0x1000 }, { "pwm0", make_unimp_dev, &mms->pwm[0], 0x7000, 0x1000 }, - { "rtc", make_unimp_dev, &mms->rtc, 0x8000, 0x1000 }, + { "rtc", make_rtc, &mms->rtc, 0x8000, 0x1000 }, { "qspi", make_unimp_dev, &mms->qspi, 0xa000, 0x1000 }, { "timer", make_unimp_dev, &mms->timer, 0xb000, 0x1000 }, { "scc", make_unimp_dev, &mms->scc, 0xc000, 0x1000 }, @@ -447,7 +467,7 @@ static void musca_init(MachineState *machine) { "spi", make_unimp_dev, &mms->spi, 0x4010a000, 0x1000 }, { "scc", make_unimp_dev, &mms->scc, 0x5010b000, 0x1000 }, { "timer", make_unimp_dev, &mms->timer, 0x4010c000, 0x1000= }, - { "rtc", make_unimp_dev, &mms->rtc, 0x4010d000, 0x1000 }, + { "rtc", make_rtc, &mms->rtc, 0x4010d000, 0x1000 }, { "pvt", make_unimp_dev, &mms->pvt, 0x4010e000, 0x1000 }, { "sdio", make_unimp_dev, &mms->sdio, 0x4010f000, 0x1000 }, }, --=20 2.20.1 From nobody Sat Nov 8 06:03:08 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15501499927827.050733751414782; Thu, 14 Feb 2019 05:13:12 -0800 (PST) Received: from localhost ([127.0.0.1]:48412 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1guGpB-0003El-OI for importer@patchew.org; Thu, 14 Feb 2019 08:13:09 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49928) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1guGeQ-00034K-JP for qemu-devel@nongnu.org; Thu, 14 Feb 2019 08:02:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1guGUc-00070P-DB for qemu-devel@nongnu.org; Thu, 14 Feb 2019 07:51:56 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:35105) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1guGUa-0006jM-Bl for qemu-devel@nongnu.org; Thu, 14 Feb 2019 07:51:54 -0500 Received: by mail-wr1-x443.google.com with SMTP id t18so6381125wrx.2 for ; Thu, 14 Feb 2019 04:51:26 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j3sm1488073wmb.39.2019.02.14.04.51.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Feb 2019 04:51:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7g9zWEgPnQ1/3e/7FE39QU99XF4zWTWG/yRPa1dvYJ4=; b=L9Ajd4o6Pgb6p4DcApMyojBNs9E6icveqCja/w7bkw12ndkmgLBvoUw4QhfXU1wvOr LQan0eZiJUA5nXl+sFcUbHdHmEaXV2uTteAytSPuM0aHhd+3Z12bK0gtodDpli/kwYEC L2S6OHfQsllwdeLRH0kuXwv0x2ARSJxViyFN/cRlsspPzEat+N4j5dthn4dgYbj5SUET YdnP8ON+n23dxzaCEP4S+jBkavrftozrRnv+DLHGmq0pJ68nqOh+kOtjLOYScepBHYUv Ez7qfNwfEW1wlKz03WmJPP/NSJaBxhpxnHnsXzIrsfVaI7HnhSv+boTtrcn99f6rKLlq TcFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7g9zWEgPnQ1/3e/7FE39QU99XF4zWTWG/yRPa1dvYJ4=; b=JOCnUhlSI8KxiQ1C8bUTEXUx4rLfVbs9937tb3fVG58f0JU1uZzQH6k+9KyRgkUehP R+QPEymIj44VMW/BXOZS8DIGspFQ8fMqLFOWHhG91KbwrKnfmjtb+t0XbPMA6V4gBmuc Jm6J8vFqmZ4AcGBG8vAgByE72f9U0hgj3m9C6aSuDr4ZZFmYgXXwtm1T60pM0spzUDww sBrFSoOyCYqfHDJrp+uDb2leNAGqbq5ZnDN3BkdXA9OMHW1YORgh6Qpk1RwFYciQyNF5 7dVXU+av68bM3gmZ0yMolzBUMXf+UfAbZzi5WvWwAl4m/daUEyL8JXaNBY/6/YvB8nmB 3agw== X-Gm-Message-State: AHQUAuYaDyEz6AQYLTvXMNqDmxZVwRKuJy+Gx/1CKKf8pasccklyha/z nUrpjtGl4t297dJ5fjLbzTDzeRKb0F792w== X-Google-Smtp-Source: AHgI3IbZ6vjOb50UZ5Am2kF8GzOc9x30M/qDdswoDLgh12yziXtxBknfDecvSx5K5B3gSzow5XaUww== X-Received: by 2002:a05:6000:1287:: with SMTP id f7mr2882462wrx.203.1550148686149; Thu, 14 Feb 2019 04:51:26 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 14 Feb 2019 12:51:07 +0000 Message-Id: <20190214125107.22178-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190214125107.22178-1-peter.maydell@linaro.org> References: <20190214125107.22178-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH 14/14] hw/arm/musca: Wire up PL011 UARTs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Wire up the two PL011 UARTs in the Musca board. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/arm/musca.c | 34 +++++++++++++++++++++++++++++----- 1 file changed, 29 insertions(+), 5 deletions(-) diff --git a/hw/arm/musca.c b/hw/arm/musca.c index ec8dfee1964..e9701533d20 100644 --- a/hw/arm/musca.c +++ b/hw/arm/musca.c @@ -23,9 +23,11 @@ #include "qemu/error-report.h" #include "qapi/error.h" #include "exec/address-spaces.h" +#include "sysemu/sysemu.h" #include "hw/arm/arm.h" #include "hw/arm/armsse.h" #include "hw/boards.h" +#include "hw/char/pl011.h" #include "hw/core/split-irq.h" #include "hw/misc/tz-mpc.h" #include "hw/misc/tz-ppc.h" @@ -69,7 +71,7 @@ typedef struct { UnimplementedDeviceState mhu[2]; UnimplementedDeviceState pwm[3]; UnimplementedDeviceState i2s; - UnimplementedDeviceState uart[2]; + PL011State uart[2]; UnimplementedDeviceState i2c[2]; UnimplementedDeviceState spi; UnimplementedDeviceState scc; @@ -285,6 +287,28 @@ static MemoryRegion *make_rtc(MuscaMachineState *mms, = void *opaque, return sysbus_mmio_get_region(SYS_BUS_DEVICE(rtc), 0); } =20 +static MemoryRegion *make_uart(MuscaMachineState *mms, void *opaque, + const char *name, hwaddr size) +{ + PL011State *uart =3D opaque; + int i =3D uart - &mms->uart[0]; + int irqbase =3D 7 + i * 6; + SysBusDevice *s; + + sysbus_init_child_obj(OBJECT(mms), name, uart, sizeof(mms->uart[0]), + TYPE_PL011); + qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i)); + object_property_set_bool(OBJECT(uart), true, "realized", &error_fatal); + s =3D SYS_BUS_DEVICE(uart); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqbase + 5)); /* combine= d */ + sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqbase + 0)); /* RX */ + sysbus_connect_irq(s, 2, get_sse_irq_in(mms, irqbase + 1)); /* TX */ + sysbus_connect_irq(s, 3, get_sse_irq_in(mms, irqbase + 2)); /* RT */ + sysbus_connect_irq(s, 4, get_sse_irq_in(mms, irqbase + 3)); /* MS */ + sysbus_connect_irq(s, 5, get_sse_irq_in(mms, irqbase + 4)); /* E */ + return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0); +} + static MemoryRegion *make_musca_a_devs(MuscaMachineState *mms, void *opaqu= e, const char *name, hwaddr size) { @@ -300,8 +324,8 @@ static MemoryRegion *make_musca_a_devs(MuscaMachineStat= e *mms, void *opaque, MemoryRegion *container =3D &mms->container; =20 const PPCPortInfo devices[] =3D { - { "uart0", make_unimp_dev, &mms->uart[0], 0x1000, 0x1000 }, - { "uart1", make_unimp_dev, &mms->uart[1], 0x2000, 0x1000 }, + { "uart0", make_uart, &mms->uart[0], 0x1000, 0x1000 }, + { "uart1", make_uart, &mms->uart[1], 0x2000, 0x1000 }, { "spi", make_unimp_dev, &mms->spi, 0x3000, 0x1000 }, { "i2c0", make_unimp_dev, &mms->i2c[0], 0x4000, 0x1000 }, { "i2c1", make_unimp_dev, &mms->i2c[1], 0x5000, 0x1000 }, @@ -460,8 +484,8 @@ static void musca_init(MachineState *machine) { "pwm1", make_unimp_dev, &mms->pwm[1], 0x40102000, 0x1000= }, { "pwm2", make_unimp_dev, &mms->pwm[2], 0x40103000, 0x1000= }, { "i2s", make_unimp_dev, &mms->i2s, 0x40104000, 0x1000 }, - { "uart0", make_unimp_dev, &mms->uart[0], 0x40105000, 0x10= 00 }, - { "uart1", make_unimp_dev, &mms->uart[1], 0x40106000, 0x10= 00 }, + { "uart0", make_uart, &mms->uart[0], 0x40105000, 0x1000 }, + { "uart1", make_uart, &mms->uart[1], 0x40106000, 0x1000 }, { "i2c0", make_unimp_dev, &mms->i2c[0], 0x40108000, 0x1000= }, { "i2c1", make_unimp_dev, &mms->i2c[1], 0x40109000, 0x1000= }, { "spi", make_unimp_dev, &mms->spi, 0x4010a000, 0x1000 }, --=20 2.20.1