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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id o2sm972713pgq.90.2019.02.13.19.43.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 13 Feb 2019 19:43:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Pc/X7bYACbirL+ncExC8NIvdujuhp6NL2EDWTl+xV4k=; b=jsJ/lgTRqYyPkT9BMPB+jtRfgkbRNxj+8d2MoF94lEucJKVAy5uaXuLtNQNbUn+Rei rA73h+M+OkTgVGLvrHU7n9hSzMzp8ryEPxmDU/cu6dNam1fD/DnVMeiYCS0aB9Wm04/Z RlzvbzcbcQMgE3y6FVx51JVGrcCktCqDIZbJoX4hdGsq9PbCUFGJPEYoUo93gHkdDJ6o BgA8sWCE7PN1L95x9dz0Izuac1hjmO6dFlS3kaky+9CKK165M5QRhfDjqXPT1UtYe+b9 vys5ux4t0HNdD9+/eKrBRLRMrRtXgTehNye70HdclGst8UablFH2IAIGLb/w6TZ1dfNs ivxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Pc/X7bYACbirL+ncExC8NIvdujuhp6NL2EDWTl+xV4k=; b=DRG0nRNJ9uyhDW30Fh/yJe6GMs2UOmGmDTfXSIkweTc4rVFYmoQRXXOyKlFHWuDpKa KzGOGta3RTnoSB1SuLLFOWYKe7bUkNvHzOHSPAlns62SmoNkxi0LlNHLxc14JHjKdegX uq3/hnR+7G/Bf4UWWuSi2KvaQmvxteyMH6FpcKixvV47mh7aWvpYcgJDpwATKHgxixnu xDM1p0Mvqe4rtYzk1IE4uggN2WjylRwCrj6Z5ZONFDV30nSvH/GnfLFo6pCSCie8QNUV WdmaNn2CxL+RQ/AouJ3/5H3GSjd2LBdULcv1PE9MTZ70WBjJHIUjRtL4ul4IrIJdcLir refg== X-Gm-Message-State: AHQUAuaRxgMVAEu9oMQe7JFApJY+lqjarKWB1+m3tkf332QaDUPR/JHn zttwgW8Ch+ZNXzkpU3E4fgVcJTshOw4= X-Google-Smtp-Source: AHgI3IbtJtzbndd8P8w9DJeGRO/sEStRPVE2/w9P/pkWL0haVqPTuo3ibCqN1K7zdRCcKiU8Z0FA4w== X-Received: by 2002:a17:902:760a:: with SMTP id k10mr1897636pll.102.1550115829227; Wed, 13 Feb 2019 19:43:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 13 Feb 2019 19:43:42 -0800 Message-Id: <20190214034345.24722-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190214034345.24722-1-richard.henderson@linaro.org> References: <20190214034345.24722-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH 1/4] target/arm: Add helpers for FMLAL and FMLSL X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Note that float16_to_float32 rightly squashes SNaN to QNaN. But of course pickNaNMulAdd, for ARM, selects SNaNs first. So we have to preserve SNaN long enough for the correct NaN to be selected. Thus float16_to_float32_by_bits. Signed-off-by: Richard Henderson --- target/arm/helper.h | 9 +++ target/arm/vec_helper.c | 154 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 163 insertions(+) diff --git a/target/arm/helper.h b/target/arm/helper.h index 53a38188c6..0302e13604 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -653,6 +653,15 @@ DEF_HELPER_FLAGS_6(gvec_fmla_idx_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(gvec_fmla_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_5(gvec_fmlal_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_fmlsl_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_fmlal_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_fmlsl_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + #ifdef TARGET_AARCH64 #include "helper-a64.h" #include "helper-sve.h" diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index 37f338732e..0c3b3de961 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -766,3 +766,157 @@ DO_FMLA_IDX(gvec_fmla_idx_s, float32, H4) DO_FMLA_IDX(gvec_fmla_idx_d, float64, ) =20 #undef DO_FMLA_IDX + +/* + * Convert float16 to float32, raising no exceptions and + * preserving exceptional values, including SNaN. + * This is effectively an unpack+repack operation. + */ +static float32 float16_to_float32_by_bits(uint32_t f16) +{ + const int f16_bias =3D 15; + const int f32_bias =3D 127; + uint32_t sign =3D extract32(f16, 15, 1); + uint32_t exp =3D extract32(f16, 10, 5); + uint32_t frac =3D extract32(f16, 0, 10); + + if (exp =3D=3D 0x1f) { + /* Inf or NaN */ + exp =3D 0xff; + } else if (exp =3D=3D 0) { + /* Zero or denormal. */ + if (frac !=3D 0) { + /* + * Denormal; these are all normal float32. + * Shift the fraction so that the msb is at bit 11, + * then remove bit 11 as the implicit bit of the + * normalized float32. Note that we still go through + * the shift for normal numbers below, to put the + * float32 fraction at the right place. + */ + int shift =3D clz32(frac) - 21; + frac =3D (frac << shift) & 0x3ff; + exp =3D f32_bias - f16_bias - shift + 1; + } + } else { + /* Normal number; adjust the bias. */ + exp +=3D f32_bias - f16_bias; + } + sign <<=3D 31; + exp <<=3D 23; + frac <<=3D 23 - 10; + + return sign | exp | frac; +} + +static float32 fmlal(float32 a, float16 n16, float16 m16, float_status *fp= st) +{ + float32 n =3D float16_to_float32_by_bits(n16); + float32 m =3D float16_to_float32_by_bits(m16); + return float32_muladd(n, m, a, 0, fpst); +} + +static float32 fmlsl(float32 a, float16 n16, float16 m16, float_status *fp= st) +{ + float32 n =3D float16_to_float32_by_bits(n16); + float32 m =3D float16_to_float32_by_bits(m16); + return float32_muladd(float32_chs(n), m, a, 0, fpst); +} + +static inline uint64_t load4_f16(uint64_t *ptr, int is_q, int is_2) +{ + /* + * Branchless load of u32[0], u64[0], u32[1], or u64[1]. + * Load the 2nd qword iff is_q & is_2. + * Shift to the 2nd dword iff !is_q & is_2. + * For !is_q & !is_2, the upper bits of the result are garbage. + */ + return ptr[is_q & is_2] >> ((is_2 & ~is_q) << 5); +} + +/* + * Note that FMLAL and FMLSL require oprsz =3D=3D 8 or oprsz =3D=3D 16, + * as there is not yet SVE versions that might use blocking. + */ + +void HELPER(gvec_fmlal_h)(void *vd, void *vn, void *vm, + void *fpst, uint32_t desc) +{ + intptr_t i, oprsz =3D simd_oprsz(desc); + int is_2 =3D extract32(desc, SIMD_DATA_SHIFT, 1); + int is_q =3D oprsz =3D=3D 16; + float32 *d =3D vd; + uint64_t n_4, m_4; + + /* Pre-load all of the f16 data, avoiding overlap issues. */ + n_4 =3D load4_f16(vn, is_q, is_2); + m_4 =3D load4_f16(vm, is_q, is_2); + + for (i =3D 0; i < oprsz / 4; i++) { + d[H4(i)] =3D fmlal(d[H4(i)], extract64(n_4, i*16, 16), + extract64(m_4, i*16, 16), fpst); + } + clear_tail(d, oprsz, simd_maxsz(desc)); +} + +void HELPER(gvec_fmlsl_h)(void *vd, void *vn, void *vm, + void *fpst, uint32_t desc) +{ + intptr_t i, oprsz =3D simd_oprsz(desc); + int is_2 =3D extract32(desc, SIMD_DATA_SHIFT, 1); + int is_q =3D oprsz =3D=3D 16; + float32 *d =3D vd; + uint64_t n_4, m_4; + + /* Pre-load all of the f16 data, avoiding overlap issues. */ + n_4 =3D load4_f16(vn, is_q, is_2); + m_4 =3D load4_f16(vm, is_q, is_2); + + for (i =3D 0; i < oprsz / 4; i++) { + d[H4(i)] =3D fmlsl(d[H4(i)], extract64(n_4, i*16, 16), + extract64(m_4, i*16, 16), fpst); + } + clear_tail(d, oprsz, simd_maxsz(desc)); +} + +void HELPER(gvec_fmlal_idx_h)(void *vd, void *vn, void *vm, + void *fpst, uint32_t desc) +{ + intptr_t i, oprsz =3D simd_oprsz(desc); + int is_2 =3D extract32(desc, SIMD_DATA_SHIFT, 1); + int index =3D extract32(desc, SIMD_DATA_SHIFT + 1, 3); + int is_q =3D oprsz =3D=3D 16; + float32 *d =3D vd; + uint64_t n_4; + float16 m_1; + + /* Pre-load all of the f16 data, avoiding overlap issues. */ + n_4 =3D load4_f16(vn, is_q, is_2); + m_1 =3D ((float16 *)vm)[H2(index)]; + + for (i =3D 0; i < oprsz / 4; i++) { + d[H4(i)] =3D fmlal(d[H4(i)], extract64(n_4, i * 16, 16), m_1, fpst= ); + } + clear_tail(d, oprsz, simd_maxsz(desc)); +} + +void HELPER(gvec_fmlsl_idx_h)(void *vd, void *vn, void *vm, + void *fpst, uint32_t desc) +{ + intptr_t i, oprsz =3D simd_oprsz(desc); + int is_2 =3D extract32(desc, SIMD_DATA_SHIFT, 1); + int index =3D extract32(desc, SIMD_DATA_SHIFT + 1, 3); + int is_q =3D oprsz =3D=3D 16; + float32 *d =3D vd; + uint64_t n_4; + float16 m_1; + + /* Pre-load all of the f16 data, avoiding overlap issues. */ + n_4 =3D load4_f16(vn, is_q, is_2); + m_1 =3D ((float16 *)vm)[H2(index)]; + + for (i =3D 0; i < oprsz / 4; i++) { + d[H4(i)] =3D fmlsl(d[H4(i)], extract64(n_4, i*16, 16), m_1, fpst); + } + clear_tail(d, oprsz, simd_maxsz(desc)); +} --=20 2.17.2 From nobody Mon Feb 9 19:08:54 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1550116832139558.1551206274601; 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X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH 2/4] target/arm: Implement FMLAL and FMLSL for aarch64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 ++++ target/arm/translate-a64.c | 49 +++++++++++++++++++++++++++++++++++++- 2 files changed, 53 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 47238e4245..15085a94ff 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3305,6 +3305,11 @@ static inline bool isar_feature_aa64_dp(const ARMISA= Registers *id) return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) !=3D 0; } =20 +static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) !=3D 0; +} + static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) !=3D 0; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e002251ac6..d2ee811489 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10891,9 +10891,26 @@ static void disas_simd_3same_float(DisasContext *s= , uint32_t insn) if (!fp_access_check(s)) { return; } - handle_3same_float(s, size, elements, fpopcode, rd, rn, rm); return; + + case 0x1d: /* FMLAL */ + case 0x3d: /* FMLSL */ + case 0x59: /* FMLAL2 */ + case 0x79: /* FMLSL2 */ + if (size & 1 || !dc_isar_feature(aa64_fhm, s)) { + unallocated_encoding(s); + return; + } + if (fp_access_check(s)) { + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, + extract32(insn, 29, 1), + extract32(insn, 23, 1) + ? gen_helper_gvec_fmlsl_h + : gen_helper_gvec_fmlal_h); + } + return; + default: unallocated_encoding(s); return; @@ -12724,6 +12741,17 @@ static void disas_simd_indexed(DisasContext *s, ui= nt32_t insn) } is_fp =3D 2; break; + case 0x00: /* FMLAL */ + case 0x04: /* FMLSL */ + case 0x18: /* FMLAL2 */ + case 0x1c: /* FMLSL2 */ + if (is_scalar || size !=3D MO_32 || !dc_isar_feature(aa64_fhm, s))= { + unallocated_encoding(s); + return; + } + size =3D MO_16; + is_fp =3D 3; + break; default: unallocated_encoding(s); return; @@ -12765,6 +12793,9 @@ static void disas_simd_indexed(DisasContext *s, uin= t32_t insn) } break; =20 + case 3: /* other fp, size already set and verified. */ + break; + default: /* integer */ switch (size) { case MO_8: @@ -12834,6 +12865,22 @@ static void disas_simd_indexed(DisasContext *s, ui= nt32_t insn) tcg_temp_free_ptr(fpst); } return; + + case 0x00: /* FMLAL */ + case 0x04: /* FMLSL */ + case 0x18: /* FMLAL2 */ + case 0x1c: /* FMLSL2 */ + { + int data =3D (index << 1) | u; + tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rn), + vec_full_reg_offset(s, rm), fpst, + is_q ? 16 : 8, vec_full_reg_size(s), data, + opcode & 4 ? gen_helper_gvec_fmlsl_idx_h + : gen_helper_gvec_fmlal_idx_h); + tcg_temp_free_ptr(fpst); + } + return; } =20 if (size =3D=3D 3) { --=20 2.17.2 From nobody Mon Feb 9 19:08:54 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1550116972199220.97661546509892; Wed, 13 Feb 2019 20:02:52 -0800 (PST) Received: from localhost ([127.0.0.1]:39490 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gu8EY-0002JR-2k for importer@patchew.org; Wed, 13 Feb 2019 23:02:46 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60093) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gu89f-0006a3-BK for qemu-devel@nongnu.org; Wed, 13 Feb 2019 22:57:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gu7wL-000750-3m for qemu-devel@nongnu.org; Wed, 13 Feb 2019 22:43:59 -0500 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:41354) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gu7wK-00071V-Qk for qemu-devel@nongnu.org; Wed, 13 Feb 2019 22:43:57 -0500 Received: by mail-pg1-x543.google.com with SMTP id m1so2291585pgq.8 for ; Wed, 13 Feb 2019 19:43:53 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id o2sm972713pgq.90.2019.02.13.19.43.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 13 Feb 2019 19:43:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+3uqZJoPHf7H0MV6qZLBPTy2QZidE62Ds6I3+3j8avw=; b=ApmbJmSvB8VSJDL5eDTlE8zZT7BoNNLMEsDwRhJFjr3eKePGIbrymDIGAXR+wDsYQp Kcx4zakuvQxGuhx6U5dwOkvnshH5f5vRdvTHmP0+RjUakhDgZGTc21MwjyrubISlZkkL eowkEfdF8TfVCU1BvXRgXWpZplhbzltfiI+ZnoXQ4vJokPrKj/gtk8wjiuDkUUe2OcRX /S/ZnIo+5J8zabDuKh/5obnB3j2yozEl0/99An5MKBkm76ZSyd6Ex8SQ/okHbtXCM1y8 8oXorhE6nIv45jWFumfDZviADbf6t3WZXaEPd9/roYkZvd54VYAp0FcSjCi5VEGMtfjX 2G3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+3uqZJoPHf7H0MV6qZLBPTy2QZidE62Ds6I3+3j8avw=; b=kzgZMuRIX+zuHNKi8k61in8rDvbwqYJ3liOsSxnRoP4o+EqgWBPpBK49KEH+LnArGK /RQ9nENZHQRI8QCMx34F3vzmAy1xkRknk1m7tV8IZ4xfBA0d8mcCGpHwbxsowpfyu6ox ILMamd6ZS3r2BoFVAJw7BEHbYDg0zZMQUZOYITgC8SR2XII+z2ERUz8n34lP5fRgAFtp CklJP9z8xoPHPtueojtXJSCbAaqjgJ0AEgiZhfsTk52HGOZxp+5VaZ06BpOW/qzoW8nT jA6h+UShNcVXfPPi9XqZhU+8ULnfPmQtkiLtWbrSPJFgBJn8cXe6y+eanxpGaq1BvtJP zibQ== X-Gm-Message-State: AHQUAuaDqYlyl1i1+7oV8TzaAQzp2o1f5WIkDzjZwuoa4WOmyyuBCgdy RDWZj/RjKXUYdWsH03+xTcv7XjZegX0= X-Google-Smtp-Source: AHgI3IbEZgqOn/69kHXXj3hkIVfFgJZjvFbyqsozgfHQwtLcI5D5IwXVbfp4H5YmAqXGgalvyqBjnw== X-Received: by 2002:a63:5761:: with SMTP id h33mr1672927pgm.283.1550115831660; Wed, 13 Feb 2019 19:43:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 13 Feb 2019 19:43:44 -0800 Message-Id: <20190214034345.24722-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190214034345.24722-1-richard.henderson@linaro.org> References: <20190214034345.24722-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH 3/4] target/arm: Implement VFMAL and VFMSL for aarch32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 ++ target/arm/translate.c | 104 +++++++++++++++++++++++++++++------------ 2 files changed, 80 insertions(+), 29 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 15085a94ff..84d24044fe 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3232,6 +3232,11 @@ static inline bool isar_feature_aa32_dp(const ARMISA= Registers *id) return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) !=3D 0; } =20 +static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) !=3D 0; +} + static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) { /* diff --git a/target/arm/translate.c b/target/arm/translate.c index 66cf28c8cb..0ed4768080 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8236,15 +8236,8 @@ static int disas_neon_insn_3same_ext(DisasContext *s= , uint32_t insn) gen_helper_gvec_3_ptr *fn_gvec_ptr =3D NULL; int rd, rn, rm, opr_sz; int data =3D 0; - bool q; - - q =3D extract32(insn, 6, 1); - VFP_DREG_D(rd, insn); - VFP_DREG_N(rn, insn); - VFP_DREG_M(rm, insn); - if ((rd | rn | rm) & q) { - return 1; - } + int off_rn, off_rm; + bool is_long =3D false, q =3D extract32(insn, 6, 1); =20 if ((insn & 0xfe200f10) =3D=3D 0xfc200800) { /* VCMLA -- 1111 110R R.1S .... .... 1000 ...0 .... */ @@ -8271,10 +8264,38 @@ static int disas_neon_insn_3same_ext(DisasContext *= s, uint32_t insn) return 1; } fn_gvec =3D u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b; + } else if ((insn & 0xff300f10) =3D=3D 0xfc200810) { + /* VFM[AS]L -- 1111 1100 S.10 .... .... 1000 .Q.1 .... */ + int sub =3D extract32(insn, 23, 1); + if (!dc_isar_feature(aa32_fhm, s)) { + return 1; + } + is_long =3D true; + fn_gvec_ptr =3D sub ? gen_helper_gvec_fmlsl_h : gen_helper_gvec_fm= lal_h; + data =3D 0; /* is_2 =3D=3D 0 */ } else { return 1; } =20 + VFP_DREG_D(rd, insn); + if (rd & q) { + return 1; + } + if (q || !is_long) { + VFP_DREG_N(rn, insn); + VFP_DREG_M(rm, insn); + if ((rn | rm) & q & !is_long) { + return 1; + } + off_rn =3D vfp_reg_offset(1, rn); + off_rm =3D vfp_reg_offset(1, rm); + } else { + rn =3D VFP_SREG_N(insn); + rm =3D VFP_SREG_M(insn); + off_rn =3D vfp_reg_offset(0, rn); + off_rm =3D vfp_reg_offset(0, rm); + } + if (s->fp_excp_el) { gen_exception_insn(s, 4, EXCP_UDEF, syn_simd_access_trap(1, 0xe, false), s->fp_excp= _el); @@ -8287,15 +8308,11 @@ static int disas_neon_insn_3same_ext(DisasContext *= s, uint32_t insn) opr_sz =3D (1 + q) * 8; if (fn_gvec_ptr) { TCGv_ptr fpst =3D get_fpstatus_ptr(1); - tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), - vfp_reg_offset(1, rn), - vfp_reg_offset(1, rm), fpst, + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), off_rn, off_rm, fpst, opr_sz, opr_sz, data, fn_gvec_ptr); tcg_temp_free_ptr(fpst); } else { - tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), - vfp_reg_offset(1, rn), - vfp_reg_offset(1, rm), + tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), off_rn, off_rm, opr_sz, opr_sz, data, fn_gvec); } return 0; @@ -8314,14 +8331,8 @@ static int disas_neon_insn_2reg_scalar_ext(DisasCont= ext *s, uint32_t insn) gen_helper_gvec_3 *fn_gvec =3D NULL; gen_helper_gvec_3_ptr *fn_gvec_ptr =3D NULL; int rd, rn, rm, opr_sz, data; - bool q; - - q =3D extract32(insn, 6, 1); - VFP_DREG_D(rd, insn); - VFP_DREG_N(rn, insn); - if ((rd | rn) & q) { - return 1; - } + int off_rn, off_rm; + bool is_long =3D false, q =3D extract32(insn, 6, 1); =20 if ((insn & 0xff000f10) =3D=3D 0xfe000800) { /* VCMLA (indexed) -- 1111 1110 S.RR .... .... 1000 ...0 .... */ @@ -8350,6 +8361,7 @@ static int disas_neon_insn_2reg_scalar_ext(DisasConte= xt *s, uint32_t insn) } else if ((insn & 0xffb00f00) =3D=3D 0xfe200d00) { /* V[US]DOT -- 1111 1110 0.10 .... .... 1101 .Q.U .... */ int u =3D extract32(insn, 4, 1); + if (!dc_isar_feature(aa32_dp, s)) { return 1; } @@ -8357,10 +8369,48 @@ static int disas_neon_insn_2reg_scalar_ext(DisasCon= text *s, uint32_t insn) /* rm is just Vm, and index is M. */ data =3D extract32(insn, 5, 1); /* index */ rm =3D extract32(insn, 0, 4); + } else if ((insn & 0xffa00f10) =3D=3D 0xfe000810) { + /* VFM[AS]L -- 1111 1110 0.0S .... .... 1000 .Q.1 .... */ + int sub =3D extract32(insn, 20, 1); + int vm20 =3D extract32(insn, 0, 3); + int vm3 =3D extract32(insn, 3, 1); + int m =3D extract32(insn, 5, 1); + int index; + + if (!dc_isar_feature(aa32_fhm, s)) { + return 1; + } + if (q) { + rm =3D vm20; + index =3D m * 2 + vm3; + } else { + rm =3D vm20 * 2 + m; + index =3D vm3; + } + is_long =3D true; + data =3D index << 1; /* is_2 =3D=3D 0 */ + fn_gvec_ptr =3D (sub ? gen_helper_gvec_fmlsl_idx_h + : gen_helper_gvec_fmlal_idx_h); } else { return 1; } =20 + VFP_DREG_D(rd, insn); + if (rd & q) { + return 1; + } + if (q || !is_long) { + VFP_DREG_N(rn, insn); + if (rn & q & !is_long) { + return 1; + } + off_rn =3D vfp_reg_offset(1, rn); + off_rm =3D vfp_reg_offset(1, rm); + } else { + rn =3D VFP_SREG_N(insn); + off_rn =3D vfp_reg_offset(0, rn); + off_rm =3D vfp_reg_offset(0, rm); + } if (s->fp_excp_el) { gen_exception_insn(s, 4, EXCP_UDEF, syn_simd_access_trap(1, 0xe, false), s->fp_excp= _el); @@ -8373,15 +8423,11 @@ static int disas_neon_insn_2reg_scalar_ext(DisasCon= text *s, uint32_t insn) opr_sz =3D (1 + q) * 8; if (fn_gvec_ptr) { TCGv_ptr fpst =3D get_fpstatus_ptr(1); - tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), - vfp_reg_offset(1, rn), - vfp_reg_offset(1, rm), fpst, + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), off_rn, off_rm, fpst, opr_sz, opr_sz, data, fn_gvec_ptr); tcg_temp_free_ptr(fpst); } else { - tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), - vfp_reg_offset(1, rn), - vfp_reg_offset(1, rm), + tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), off_rn, off_rm, opr_sz, opr_sz, data, fn_gvec); } return 0; --=20 2.17.2 From nobody Mon Feb 9 19:08:54 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1550116864382856.7189996945862; Wed, 13 Feb 2019 20:01:04 -0800 (PST) Received: from localhost ([127.0.0.1]:39463 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gu8Cr-0000pw-BL for importer@patchew.org; Wed, 13 Feb 2019 23:01:01 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60468) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gu89f-000721-9r for qemu-devel@nongnu.org; Wed, 13 Feb 2019 22:57:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gu7wL-00077Y-Mc for qemu-devel@nongnu.org; Wed, 13 Feb 2019 22:43:59 -0500 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:40950) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gu7wL-00072l-Bj for qemu-devel@nongnu.org; Wed, 13 Feb 2019 22:43:57 -0500 Received: by mail-pf1-x443.google.com with SMTP id h1so2340086pfo.7 for ; Wed, 13 Feb 2019 19:43:54 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id o2sm972713pgq.90.2019.02.13.19.43.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 13 Feb 2019 19:43:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cbskW479OhNUzyJNbm1VlQPK+6mCdYvQdwJmmMsXd+Q=; b=LCl+ylO6PbH9k5bY860RPQnrt57dxg0qBaRmREX3iYhTgfa9pCH7MFxQWgC7om83o7 boIn8uV+IBsxwiYo0pWqVQiDyjci9/SqDr94cBflTOx/KNFIpGY9/DSOIOd+vaayxgnC tbtloiH0CF5st5JAlead43XtL0+cz4cLagXdfD1Iv+Sf+uzZM6jnPf6kXiI/Lyg8YUEB 3z3/IPKf0rlJOzF6wmaPsAl6qTlCN1Zuu3vTDigmzgk//XFNxGFqvGTG3h4imXih4x7a SDeZFJSc5ZDYXfJLa9CocesK5O/xjNXy20DjNvz8L58BkqpKxx/Gqm4y0VgOIFwmyKWn PQVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cbskW479OhNUzyJNbm1VlQPK+6mCdYvQdwJmmMsXd+Q=; b=GRSrwYjU0u9pVtvfHtmsIX3356MpBqDmmVa8NiaShB8HcCcpKkSSJ7hzJpu6GsAjBu RoMxnJDyd88wLpV6/bqw4G03cBnwR8FlWQvh1t8LaPRw4iu+0HZa2jQLdAxdFGlYXmXI 5ByTcu+A8aTpGXCaAW1wJqhClNIqWQy3Kl9NCNpVZQmNHVqCeutns1i5mdxt2kAvXsQr tjC5X35qltDFuC0U2J2VbNvPVq6lV8pbg5ayuPSHYIOUl0cy5A/THCDKBAkDADVmfja4 zLvRttwJUgynHJf+y7pFkGoHwm8rNVvTRfA7yudEKvmc46khbfIWBrqWD38k8h+bohsL tC3g== X-Gm-Message-State: AHQUAubStKeLcqttl1sgzxa5909JlK6p73RQ0j4qrROTwetvEqPU3/tR ctX6pRnX6RDD6UvvLSTsg+wRB5zMOV0= X-Google-Smtp-Source: AHgI3IaCcSvei/27nutDlDPeqTQqgCZpZpiK9ZG7y94PisacF/eZyImktcYoCrGmbE24PRxHYqXvOA== X-Received: by 2002:a62:be0c:: with SMTP id l12mr1764171pff.51.1550115833004; Wed, 13 Feb 2019 19:43:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 13 Feb 2019 19:43:45 -0800 Message-Id: <20190214034345.24722-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190214034345.24722-1-richard.henderson@linaro.org> References: <20190214034345.24722-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH 4/4] target/arm: Enable ARMv8.2-FHM for -cpu max X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/cpu.c | 1 + target/arm/cpu64.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index edf6e0e1f1..f4aa6202f5 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2002,6 +2002,7 @@ static void arm_max_initfn(Object *obj) =20 t =3D cpu->isar.id_isar6; t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); + t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); cpu->isar.id_isar6 =3D t; =20 t =3D cpu->id_mmfr4; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index eff0f164dd..bffce337a4 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -308,6 +308,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); t =3D FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); cpu->isar.id_aa64isar0 =3D t; =20 t =3D cpu->isar.id_aa64isar1; @@ -345,6 +346,7 @@ static void aarch64_max_initfn(Object *obj) =20 u =3D cpu->isar.id_isar6; u =3D FIELD_DP32(u, ID_ISAR6, DP, 1); + u =3D FIELD_DP32(u, ID_ISAR6, FHM, 1); cpu->isar.id_isar6 =3D u; =20 /* --=20 2.17.2