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X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v7 30/35] target/riscv: Remove decode_RV32_64G() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Peer Adelt , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Bastian Koppelmann decodetree handles all instructions now so the fallback is not necessary anymore. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/translate.c | 21 +-------------------- 1 file changed, 1 insertion(+), 20 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 65bedc966497..59c297915158 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -646,24 +646,6 @@ bool decode_insn16(DisasContext *ctx, uint16_t insn); #include "decode_insn16.inc.c" #include "insn_trans/trans_rvc.inc.c" =20 -static void decode_RV32_64G(DisasContext *ctx) -{ - uint32_t op; - - /* We do not do misaligned address check here: the address should neve= r be - * misaligned at this point. Instructions that set PC must do the chec= k, - * since epc must be the address of the instruction that caused us to - * perform the misaligned instruction fetch */ - - op =3D MASK_OP_MAJOR(ctx->opcode); - - switch (op) { - default: - gen_exception_illegal(ctx); - break; - } -} - static void decode_opc(DisasContext *ctx) { /* check for compressed insn */ @@ -680,8 +662,7 @@ static void decode_opc(DisasContext *ctx) } else { ctx->pc_succ_insn =3D ctx->base.pc_next + 4; if (!decode_insn32(ctx, ctx->opcode)) { - /* fallback to old decoder */ - decode_RV32_64G(ctx); + gen_exception_illegal(ctx); } } } --=20 2.18.1