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X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v7 01/35] target/riscv: Move CPURISCVState pointer to DisasContext X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Bastian Koppelmann CPURISCVState is rarely used, so there is no need to pass it to every translate function. This paves the way for decodetree which only passes DisasContext to translate functions. Reviewed-by: Palmer Dabbelt Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Signed-off-by: Bastian Koppelmann --- target/riscv/translate.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index b7176cbf98e1..9e06eb8c2de5 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -54,6 +54,7 @@ typedef struct DisasContext { to any system register, which includes CSR_FRM, so we do not have to reset this known value. */ int frm; + CPURISCVState *env; } DisasContext; =20 /* convert riscv funct3 to qemu memop for load/store */ @@ -2003,7 +2004,7 @@ static void decode_opc(DisasContext *ctx) { /* check for compressed insn */ if (extract32(ctx->opcode, 0, 2) !=3D 3) { - if (!has_ext(ctx, RVC)) { + if (!riscv_has_ext(ctx->env, RVC)) { gen_exception_illegal(ctx); } else { ctx->pc_succ_insn =3D ctx->base.pc_next + 2; @@ -2058,9 +2059,9 @@ static bool riscv_tr_breakpoint_check(DisasContextBas= e *dcbase, CPUState *cpu, static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cp= u) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - CPURISCVState *env =3D cpu->env_ptr; + ctx->env =3D cpu->env_ptr; =20 - ctx->opcode =3D cpu_ldl_code(env, ctx->base.pc_next); + ctx->opcode =3D cpu_ldl_code(ctx->env, ctx->base.pc_next); decode_opc(ctx); ctx->base.pc_next =3D ctx->pc_succ_insn; =20 --=20 2.18.1