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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n6sm6212848wmk.9.2019.02.12.10.19.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Feb 2019 10:19:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=TJJbCexAnaygb5NbSxOchbhUl0UTuJ20W+GAJCoo3jc=; b=EOn8V89VnvvT8EAq1/o8XzC+UFuzrR7Z5rB1wNSUbDsMw2hteOV1RmHpJp30s/zJEo mBocajNuUSoSrX1cmVUUGHs5k2B4HeWQYEz/B96lq4/h9DW79ZH7/ad2lmB6WUtpJrP7 s3GjZe5cmIRX1AmNjHnLFDjLiUnLs8lukCK+yKD/lVtYKkiztG+3PuJHpbiEqA9ln7Yr AXGhdtAjSNzeSvE6uC9bhTPLsq7c9htY22iTGQZ7tgiapV03pm2ajqndw43/7v+kactw 1XVC7/YOvy6CNmEXABM5y2VwPyUeY0DHRL7uDIGUg2OsQTry+dJBX54ULo2trzuFcZXW l9GA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=TJJbCexAnaygb5NbSxOchbhUl0UTuJ20W+GAJCoo3jc=; b=IeeBI9DHg0uIuz7PMgVEj53woePIT/djpTJeRILq4QjKc4bBhTRPc5Temkj0ghNUl7 KKSPgnHSi4IZbbk42Y+bAFrQ73sBXHvw8wpHcOsdm+d3xhmQUdgY3bBfcsG95WE+M/4h sUfNmOd/yO6wKQp96KEJbrPjl2ytKF50gGiXzHp2XzLVkm9sMGMHqWu4dz72lhJ6N4pV v0FuM/TeKKuEDb+Jay9qo7tfCc7sz4GeMR9U3x/frXLAAd271Ej/Kt/LccTOtK67+ztV hgRiApVYWk8PlCJI1eF8xAc/08RGUytNdH0iJJnLK6j6I5aOpuOdt3GQ7lN/4tlfPmo1 U+hQ== X-Gm-Message-State: AHQUAubnSBpo1Ut/KjOIPEknh1r8z4fqL7zoqOPuEgpBQgOu9RGZP4/A MVK4UmV8jBu77xG4n52ek/nepA== X-Google-Smtp-Source: AHgI3IZcDMw/dUwVKPAFowNv0NljvB+26+h+gHpjhcCqxR823RIrCtyCDvJteyGFLQJMsSMvfndfZA== X-Received: by 2002:a1c:4301:: with SMTP id q1mr156670wma.44.1549995559920; Tue, 12 Feb 2019 10:19:19 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 12 Feb 2019 18:19:17 +0000 Message-Id: <20190212181917.8322-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH] hw/intc/armv7m_nvic: Allow byte accesses to SHPR1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Julia Suvorova , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The code for handling the NVIC SHPR1 register intends to permit byte and halfword accesses (as the architecture requires). However the 'case' line for it only lists the base address of the register, so attempts to access bytes other than the first one end up in the "bad write" default logic. This bug was added accidentally when we split out the SHPR1 logic from SHPR2 and SHPR3 to support v6M. Fixes: 7c9140afd594 ("nvic: Handle ARMv6-M SCS reserved registers") Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- The Zephyr RTOS happens to access SHPR1 byte at a time, which is how I spotted this. --- hw/intc/armv7m_nvic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 790a3d95849..2fd40f9dc4c 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1956,7 +1956,7 @@ static MemTxResult nvic_sysreg_write(void *opaque, hw= addr addr, } nvic_irq_update(s); return MEMTX_OK; - case 0xd18: /* System Handler Priority (SHPR1) */ + case 0xd18 ... 0xd1b: /* System Handler Priority (SHPR1) */ if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) { return MEMTX_OK; } --=20 2.20.1