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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id 90sm21262078wrk.95.2019.02.12.02.52.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Feb 2019 02:52:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=AOHCEzaG9WfBckXKUn2kLpZrQ8dSCiXc16/6UwtDWoA=; b=kjhrgo4VswMtKt1JpfzWWWzkx1KVGoe6fbeygfEzubE1WzVwsbIlAY8NAJUxjqJAn6 wn6Xx0O2YVt1r0oLzthgMGluILf4SZk4WZqoRvXCKw1TpWaokzUS4yRgwJEudUVd7Cm8 mnaqHvszapzi6SfBO8hTpKUI+bCoEAdyeDzBWJS7/jnK7RqGWTCnDjTx6voJfMZlh4Sh c+RygfCdsGQ7Kr2oKWJm+roKqmTpcXL6nQixMpfp7gPzyEzLT8AUj8lUd9ivMA40l8Q3 1bH38EWKYc/wNcxAn3RU7IORKE6gnYixb3lwGzJ3emeWLOAXNUuLfdovPKKXC75iJYBu 6UWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=AOHCEzaG9WfBckXKUn2kLpZrQ8dSCiXc16/6UwtDWoA=; b=bx4Qfv1h1xDp1iIeeExcBFffugaUcukvoJ3MvJHR4hgYgHVBQcQ0DDrQ5FEe0sYdKl tCZi2XJsPLKNmXAXNvXuEvQYKTCkvaX7i/A+4vyDBWjFWBmwCaxgIQuhuudv3MjM+jgR 2xK2Ybec7vJMQ4wSrYNcynWByGTZDp//QKYq3EquYWlAVmK1SD2HrnxEymaM+RbV7RBF bQ+x7kTjJuatSTYosYVRG/ZZdC5JhqYv3qtV/s2hQYlgFiNWgSmTW0damTC5Q2C5FekU dSfQLWPu0oYqj2Ny6hMsOrV3vZ0NkN0y2Y06NbA2010iAEarXQvJXoDQfk92ZIlfqY85 DuFQ== X-Gm-Message-State: AHQUAuZUzNNxvGuo4auN01vUaIiMFA6gYs0QVlgiG/t5IjlyB2m2W08j i48RuscotZEiRI79s1odKwlFiQ== X-Google-Smtp-Source: AHgI3IakgSD3ffgM31qSPAhVCY6AYYzUsh8+c/5Kyh4Teb/yIz0UtVmP7hJJGEWY1UwfvJDHUbu2Qg== X-Received: by 2002:adf:ed0f:: with SMTP id a15mr2360550wro.249.1549968723483; Tue, 12 Feb 2019 02:52:03 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 12 Feb 2019 10:52:01 +0000 Message-Id: <20190212105201.13795-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH] hw/arm/armsse: Fix miswiring of expansion IRQs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" In commit 91c1e9fcbd7548db368 where we added dual-CPU support to the ARMSSE, we set up the wiring of the expansion IRQs via nested loops: the outer loop on 'i' loops for each CPU, and the inner loop on 'j' loops for each interrupt. Fix a typo which meant we were wiring every expansion IRQ line to external IRQ 0 on CPU 0 and to external IRQ 1 on CPU 1. Fixes: 91c1e9fcbd7548db368 ("hw/arm/armsse: Support dual-CPU configuration") Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- It turns out that the ARM-TFM image I was using to test that I hadn't broken the mps2-an505 doesn't actually rely on any interrupts from the external devices... hw/arm/armsse.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 5d53071a5a0..9a8c49547db 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -565,7 +565,7 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) /* Connect EXP_IRQ/EXP_CPUn_IRQ GPIOs to the NVIC's lines 32 and u= p */ s->exp_irqs[i] =3D g_new(qemu_irq, s->exp_numirq); for (j =3D 0; j < s->exp_numirq; j++) { - s->exp_irqs[i][j] =3D qdev_get_gpio_in(cpudev, i + 32); + s->exp_irqs[i][j] =3D qdev_get_gpio_in(cpudev, j + 32); } if (i =3D=3D 0) { gpioname =3D g_strdup("EXP_IRQ"); --=20 2.20.1