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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id a90sm22088923pfj.109.2019.02.11.20.57.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Feb 2019 20:57:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=yaGBPGPY8lwKTIe/SH+HRx7tSb2km+zrbRYBmYlSMLw=; b=ebvA8oxHGmq5rnSQIAF7FVucs1rrVliYWR12vlUitvcOReBU3i3lgqTGnir83rJ0fO iv+ZrKkQBKwlegt8atfR9fJSN0Z4cZSNNBOWPC+ZRuJcTDNw1Zu+6Pnn7+YW0Q9NZNDO hJSRLQQn9RA4j9t+TLYFgRKrgsyzqHiv2lq2QUG2LIN8CEyUL/y3A3DG0ITTH3y9ck2W EjwnOaamjh4woFgg5WAwYUGMOyMJSY2kvf3un6I2+VMn7Mu+/wzwnZn0ZIX6jgysvVR9 S6TV/f/xXQARY4WEYKXZNp5r+m4O4wub4CrxpKnFrhPIjAn8ZqNKDGgAUGG/NXo4RB1y lrTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=yaGBPGPY8lwKTIe/SH+HRx7tSb2km+zrbRYBmYlSMLw=; b=ahwGnH1Kmds3jPQry7GDxVpU8R+i70ggG0kfMVMG0MzmBa+jR+mf16bgmZDIhZ+N9r HBUvsE/JrHvSUueL1l5MmBrhAKKvc5jnGZzP20JHP1+6evQQHL12au1RmfLRLJJPhaKI XnjsD688c5xjx1Zwssl7UcKQLcFaFf+qNeV/U61uWzAki12PMRS9FB4q+/MyvlR9Wae3 i/Hq4nNy295R5RmgalXR8BbC4hmUH7eSkb/WogB3n0srkZfEjk0+WvjKz3VWYe9jIi1P 9RtN9LSPGpenJTLoZGqbJMg5FLGaCO/LYZGCqPXrdGBiS3yR37scFlIz7X0I4Q2jc3xO St0Q== X-Gm-Message-State: AHQUAuZXWfra6DD2Hks63GSRPMc44qqPZ9KkF8yLQ+1nEfQ2ho0p9CjG BHWayBNThHLof2MnIDvJFT1S1bw/o/4= X-Google-Smtp-Source: AHgI3IZlF5bq5UER3yfmVwEY/ZEoinSt9wTkOc+yVlW9OHbVe0pepEIfVgxtnaJ8dGDoeQNuw+FeSA== X-Received: by 2002:a62:7042:: with SMTP id l63mr2065118pfc.1.1549947449841; Mon, 11 Feb 2019 20:57:29 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 11 Feb 2019 20:57:02 -0800 Message-Id: <20190212045721.28041-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190212045721.28041-1-richard.henderson@linaro.org> References: <20190212045721.28041-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PULL 05/24] target/hppa: Unify specializations of OR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" With decodetree.py, the specializations would conflict so we must have a single entry point for all variants of OR. Tested-by: Helge Deller Tested-by: Sven Schnelle Signed-off-by: Richard Henderson --- target/hppa/translate.c | 108 ++++++++++++++++++++++------------------ 1 file changed, 59 insertions(+), 49 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 2ca0f5da10..6c2f560fc1 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2622,21 +2622,69 @@ static bool trans_log(DisasContext *ctx, uint32_t i= nsn, const DisasInsn *di) return nullify_end(ctx); } =20 -/* OR r,0,t -> COPY (according to gas) */ -static bool trans_copy(DisasContext *ctx, uint32_t insn, const DisasInsn *= di) +static bool trans_or(DisasContext *ctx, uint32_t insn, const DisasInsn *di) { + unsigned r2 =3D extract32(insn, 21, 5); unsigned r1 =3D extract32(insn, 16, 5); + unsigned cf =3D extract32(insn, 12, 4); unsigned rt =3D extract32(insn, 0, 5); + TCGv_reg tcg_r1, tcg_r2; =20 - if (r1 =3D=3D 0) { - TCGv_reg dest =3D dest_gpr(ctx, rt); - tcg_gen_movi_reg(dest, 0); - save_gpr(ctx, rt, dest); - } else { - save_gpr(ctx, rt, cpu_gr[r1]); + if (cf =3D=3D 0) { + if (rt =3D=3D 0) { /* NOP */ + cond_free(&ctx->null_cond); + return true; + } + if (r2 =3D=3D 0) { /* COPY */ + if (r1 =3D=3D 0) { + TCGv_reg dest =3D dest_gpr(ctx, rt); + tcg_gen_movi_reg(dest, 0); + save_gpr(ctx, rt, dest); + } else { + save_gpr(ctx, rt, cpu_gr[r1]); + } + cond_free(&ctx->null_cond); + return true; + } +#ifndef CONFIG_USER_ONLY + /* These are QEMU extensions and are nops in the real architecture: + * + * or %r10,%r10,%r10 -- idle loop; wait for interrupt + * or %r31,%r31,%r31 -- death loop; offline cpu + * currently implemented as idle. + */ + if ((rt =3D=3D 10 || rt =3D=3D 31) && r1 =3D=3D rt && r2 =3D=3D rt= ) { /* PAUSE */ + TCGv_i32 tmp; + + /* No need to check for supervisor, as userland can only pause + until the next timer interrupt. */ + nullify_over(ctx); + + /* Advance the instruction queue. */ + copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); + copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var); + nullify_set(ctx, 0); + + /* Tell the qemu main loop to halt until this cpu has work. */ + tmp =3D tcg_const_i32(1); + tcg_gen_st_i32(tmp, cpu_env, -offsetof(HPPACPU, env) + + offsetof(CPUState, halted)); + tcg_temp_free_i32(tmp); + gen_excp_1(EXCP_HALTED); + ctx->base.is_jmp =3D DISAS_NORETURN; + + return nullify_end(ctx); + } +#endif } - cond_free(&ctx->null_cond); - return true; + + if (cf) { + nullify_over(ctx); + } + tcg_r1 =3D load_gpr(ctx, r1); + tcg_r2 =3D load_gpr(ctx, r2); + do_log(ctx, rt, tcg_r1, tcg_r2, cf, tcg_gen_or_reg); + return nullify_end(ctx); } =20 static bool trans_cmpclr(DisasContext *ctx, uint32_t insn, const DisasInsn= *di) @@ -2781,48 +2829,10 @@ static bool trans_ds(DisasContext *ctx, uint32_t in= sn, const DisasInsn *di) return nullify_end(ctx); } =20 -#ifndef CONFIG_USER_ONLY -/* These are QEMU extensions and are nops in the real architecture: - * - * or %r10,%r10,%r10 -- idle loop; wait for interrupt - * or %r31,%r31,%r31 -- death loop; offline cpu - * currently implemented as idle. - */ -static bool trans_pause(DisasContext *ctx, uint32_t insn, const DisasInsn = *di) -{ - TCGv_i32 tmp; - - /* No need to check for supervisor, as userland can only pause - until the next timer interrupt. */ - nullify_over(ctx); - - /* Advance the instruction queue. */ - copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); - copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var); - nullify_set(ctx, 0); - - /* Tell the qemu main loop to halt until this cpu has work. */ - tmp =3D tcg_const_i32(1); - tcg_gen_st_i32(tmp, cpu_env, -offsetof(HPPACPU, env) + - offsetof(CPUState, halted)); - tcg_temp_free_i32(tmp); - gen_excp_1(EXCP_HALTED); - ctx->base.is_jmp =3D DISAS_NORETURN; - - return nullify_end(ctx); -} -#endif - static const DisasInsn table_arith_log[] =3D { - { 0x08000240u, 0xfc00ffffu, trans_nop }, /* or x,y,0 */ - { 0x08000240u, 0xffe0ffe0u, trans_copy }, /* or x,0,t */ -#ifndef CONFIG_USER_ONLY - { 0x094a024au, 0xffffffffu, trans_pause }, /* or r10,r10,r10 */ - { 0x0bff025fu, 0xffffffffu, trans_pause }, /* or r31,r31,r31 */ -#endif + { 0x08000240u, 0xfc000fe0u, trans_or }, { 0x08000000u, 0xfc000fe0u, trans_log, .f.ttt =3D tcg_gen_andc_reg }, { 0x08000200u, 0xfc000fe0u, trans_log, .f.ttt =3D tcg_gen_and_reg }, - { 0x08000240u, 0xfc000fe0u, trans_log, .f.ttt =3D tcg_gen_or_reg }, { 0x08000280u, 0xfc000fe0u, trans_log, .f.ttt =3D tcg_gen_xor_reg }, { 0x08000880u, 0xfc000fe0u, trans_cmpclr }, { 0x08000380u, 0xfc000fe0u, trans_uxor }, --=20 2.17.2