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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id a90sm22088923pfj.109.2019.02.11.20.57.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Feb 2019 20:57:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HE5QKyxAXT0w8DfFAisrLW8mdiy54iuX4HRbpd93rG4=; b=rNw9AHitf7IwTt9uDD9SNrUeqVwn49SS1LLJo6TI2bF2LbuzrF810WaaEVFt5OR0aU 3tx0oh+GOypVn81sknykAyZpQJVE4JS7kKdjRoTS9OS43pPYh7n6OAqfqiMVy+CZz1V7 tHVzMCsZbPaJYu49cA4yZeZi1AqNy5aQ0N7L9K51YXexQ8DKBSY7eqKYLSk/mvfyb3tt z/MtudpVXXcQC8YVubUUq2jPbfqsLFI7RAP/ANsVZrghQvU1jrYwvSzaeUH15b2si5Ig IhITrmKdThfWgVwUXlHxpX72Sjlw+ujoXUQ3VLvC4JfW7CpjEZOoQTnxhk2VMhtzgspT iAOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HE5QKyxAXT0w8DfFAisrLW8mdiy54iuX4HRbpd93rG4=; b=AQM1SQudJcIXxaCM5fvWd8mx+v/S53Lx5aRquD+lBVxEJrwY1Rg8bPBgyju30jHE+G k3OrrMHQIDxDlE5Aw8v91EN+cKdS65ULjE1e1KL8oWIq4FI75bsu6iI8C/pbyjZuA7yV 29do6jN/2SqJaU4G3GRb4pKXj93D9xBuSQxad2SR4TmX0bs0YdHg1jM9vt32kBX811bm CipixqEGWjeN5ZnYzqa1NOoqAXIExWnwVETD8ol4dMzjQ3v5c3E2i347sDv9kCHl3o9B bwJkHpartqUxr5XWHulluPBtn2FHGlUxUI+5Tyri/pPzZX91hUrEshjGikdk09ql4HT4 m6OQ== X-Gm-Message-State: AHQUAuah7ylgZQIzyA/BOrxt3IRi129pkRy9fxiPRPnyXRIR+Y6ZAf9u eGap2uVLehCd2dRL98KVP6euOgUTGpU= X-Google-Smtp-Source: AHgI3IYxW3CzFedmcxtJjR2UwRKWk1GhIB+t5xsHvnLLDmd5lwIxvL1Nq28imS/9LBnwOIMizCLdgg== X-Received: by 2002:a17:902:d01:: with SMTP id 1mr2112333plu.127.1549947457451; Mon, 11 Feb 2019 20:57:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 11 Feb 2019 20:57:08 -0800 Message-Id: <20190212045721.28041-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190212045721.28041-1-richard.henderson@linaro.org> References: <20190212045721.28041-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::635 Subject: [Qemu-devel] [PULL 11/24] target/hppa: Convert shift, extract, deposit insns X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Tested-by: Helge Deller Tested-by: Sven Schnelle Signed-off-by: Richard Henderson --- target/hppa/translate.c | 215 ++++++++++++++------------------------- target/hppa/insns.decode | 15 +++ 2 files changed, 94 insertions(+), 136 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 7bdb900130..83d898212e 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3292,26 +3292,21 @@ static bool trans_movbi(DisasContext *ctx, arg_movb= i *a) return do_cbranch(ctx, a->disp, a->n, &cond); } =20 -static bool trans_shrpw_sar(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static bool trans_shrpw_sar(DisasContext *ctx, arg_shrpw_sar *a) { - unsigned rt =3D extract32(insn, 0, 5); - unsigned c =3D extract32(insn, 13, 3); - unsigned r1 =3D extract32(insn, 16, 5); - unsigned r2 =3D extract32(insn, 21, 5); TCGv_reg dest; =20 - if (c) { + if (a->c) { nullify_over(ctx); } =20 - dest =3D dest_gpr(ctx, rt); - if (r1 =3D=3D 0) { - tcg_gen_ext32u_reg(dest, load_gpr(ctx, r2)); + dest =3D dest_gpr(ctx, a->t); + if (a->r1 =3D=3D 0) { + tcg_gen_ext32u_reg(dest, load_gpr(ctx, a->r2)); tcg_gen_shr_reg(dest, dest, cpu_sar); - } else if (r1 =3D=3D r2) { + } else if (a->r1 =3D=3D a->r2) { TCGv_i32 t32 =3D tcg_temp_new_i32(); - tcg_gen_trunc_reg_i32(t32, load_gpr(ctx, r2)); + tcg_gen_trunc_reg_i32(t32, load_gpr(ctx, a->r2)); tcg_gen_rotr_i32(t32, t32, cpu_sar); tcg_gen_extu_i32_reg(dest, t32); tcg_temp_free_i32(t32); @@ -3319,7 +3314,7 @@ static bool trans_shrpw_sar(DisasContext *ctx, uint32= _t insn, TCGv_i64 t =3D tcg_temp_new_i64(); TCGv_i64 s =3D tcg_temp_new_i64(); =20 - tcg_gen_concat_reg_i64(t, load_gpr(ctx, r2), load_gpr(ctx, r1)); + tcg_gen_concat_reg_i64(t, load_gpr(ctx, a->r2), load_gpr(ctx, a->r= 1)); tcg_gen_extu_reg_i64(s, cpu_sar); tcg_gen_shr_i64(t, t, s); tcg_gen_trunc_i64_reg(dest, t); @@ -3327,79 +3322,67 @@ static bool trans_shrpw_sar(DisasContext *ctx, uint= 32_t insn, tcg_temp_free_i64(t); tcg_temp_free_i64(s); } - save_gpr(ctx, rt, dest); + save_gpr(ctx, a->t, dest); =20 /* Install the new nullification. */ cond_free(&ctx->null_cond); - if (c) { - ctx->null_cond =3D do_sed_cond(c, dest); + if (a->c) { + ctx->null_cond =3D do_sed_cond(a->c, dest); } return nullify_end(ctx); } =20 -static bool trans_shrpw_imm(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static bool trans_shrpw_imm(DisasContext *ctx, arg_shrpw_imm *a) { - unsigned rt =3D extract32(insn, 0, 5); - unsigned cpos =3D extract32(insn, 5, 5); - unsigned c =3D extract32(insn, 13, 3); - unsigned r1 =3D extract32(insn, 16, 5); - unsigned r2 =3D extract32(insn, 21, 5); - unsigned sa =3D 31 - cpos; + unsigned sa =3D 31 - a->cpos; TCGv_reg dest, t2; =20 - if (c) { + if (a->c) { nullify_over(ctx); } =20 - dest =3D dest_gpr(ctx, rt); - t2 =3D load_gpr(ctx, r2); - if (r1 =3D=3D r2) { + dest =3D dest_gpr(ctx, a->t); + t2 =3D load_gpr(ctx, a->r2); + if (a->r1 =3D=3D a->r2) { TCGv_i32 t32 =3D tcg_temp_new_i32(); tcg_gen_trunc_reg_i32(t32, t2); tcg_gen_rotri_i32(t32, t32, sa); tcg_gen_extu_i32_reg(dest, t32); tcg_temp_free_i32(t32); - } else if (r1 =3D=3D 0) { + } else if (a->r1 =3D=3D 0) { tcg_gen_extract_reg(dest, t2, sa, 32 - sa); } else { TCGv_reg t0 =3D tcg_temp_new(); tcg_gen_extract_reg(t0, t2, sa, 32 - sa); - tcg_gen_deposit_reg(dest, t0, cpu_gr[r1], 32 - sa, sa); + tcg_gen_deposit_reg(dest, t0, cpu_gr[a->r1], 32 - sa, sa); tcg_temp_free(t0); } - save_gpr(ctx, rt, dest); + save_gpr(ctx, a->t, dest); =20 /* Install the new nullification. */ cond_free(&ctx->null_cond); - if (c) { - ctx->null_cond =3D do_sed_cond(c, dest); + if (a->c) { + ctx->null_cond =3D do_sed_cond(a->c, dest); } return nullify_end(ctx); } =20 -static bool trans_extrw_sar(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static bool trans_extrw_sar(DisasContext *ctx, arg_extrw_sar *a) { - unsigned clen =3D extract32(insn, 0, 5); - unsigned is_se =3D extract32(insn, 10, 1); - unsigned c =3D extract32(insn, 13, 3); - unsigned rt =3D extract32(insn, 16, 5); - unsigned rr =3D extract32(insn, 21, 5); - unsigned len =3D 32 - clen; + unsigned len =3D 32 - a->clen; TCGv_reg dest, src, tmp; =20 - if (c) { + if (a->c) { nullify_over(ctx); } =20 - dest =3D dest_gpr(ctx, rt); - src =3D load_gpr(ctx, rr); + dest =3D dest_gpr(ctx, a->t); + src =3D load_gpr(ctx, a->r); tmp =3D tcg_temp_new(); =20 /* Recall that SAR is using big-endian bit numbering. */ tcg_gen_xori_reg(tmp, cpu_sar, TARGET_REGISTER_BITS - 1); - if (is_se) { + if (a->se) { tcg_gen_sar_reg(dest, src, tmp); tcg_gen_sextract_reg(dest, dest, 0, len); } else { @@ -3407,83 +3390,62 @@ static bool trans_extrw_sar(DisasContext *ctx, uint= 32_t insn, tcg_gen_extract_reg(dest, dest, 0, len); } tcg_temp_free(tmp); - save_gpr(ctx, rt, dest); + save_gpr(ctx, a->t, dest); =20 /* Install the new nullification. */ cond_free(&ctx->null_cond); - if (c) { - ctx->null_cond =3D do_sed_cond(c, dest); + if (a->c) { + ctx->null_cond =3D do_sed_cond(a->c, dest); } return nullify_end(ctx); } =20 -static bool trans_extrw_imm(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static bool trans_extrw_imm(DisasContext *ctx, arg_extrw_imm *a) { - unsigned clen =3D extract32(insn, 0, 5); - unsigned pos =3D extract32(insn, 5, 5); - unsigned is_se =3D extract32(insn, 10, 1); - unsigned c =3D extract32(insn, 13, 3); - unsigned rt =3D extract32(insn, 16, 5); - unsigned rr =3D extract32(insn, 21, 5); - unsigned len =3D 32 - clen; - unsigned cpos =3D 31 - pos; + unsigned len =3D 32 - a->clen; + unsigned cpos =3D 31 - a->pos; TCGv_reg dest, src; =20 - if (c) { + if (a->c) { nullify_over(ctx); } =20 - dest =3D dest_gpr(ctx, rt); - src =3D load_gpr(ctx, rr); - if (is_se) { + dest =3D dest_gpr(ctx, a->t); + src =3D load_gpr(ctx, a->r); + if (a->se) { tcg_gen_sextract_reg(dest, src, cpos, len); } else { tcg_gen_extract_reg(dest, src, cpos, len); } - save_gpr(ctx, rt, dest); + save_gpr(ctx, a->t, dest); =20 /* Install the new nullification. */ cond_free(&ctx->null_cond); - if (c) { - ctx->null_cond =3D do_sed_cond(c, dest); + if (a->c) { + ctx->null_cond =3D do_sed_cond(a->c, dest); } return nullify_end(ctx); } =20 -static const DisasInsn table_sh_ex[] =3D { - { 0xd0000000u, 0xfc001fe0u, trans_shrpw_sar }, - { 0xd0000800u, 0xfc001c00u, trans_shrpw_imm }, - { 0xd0001000u, 0xfc001be0u, trans_extrw_sar }, - { 0xd0001800u, 0xfc001800u, trans_extrw_imm }, -}; - -static bool trans_depw_imm_c(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static bool trans_depwi_imm(DisasContext *ctx, arg_depwi_imm *a) { - unsigned clen =3D extract32(insn, 0, 5); - unsigned cpos =3D extract32(insn, 5, 5); - unsigned nz =3D extract32(insn, 10, 1); - unsigned c =3D extract32(insn, 13, 3); - target_sreg val =3D low_sextract(insn, 16, 5); - unsigned rt =3D extract32(insn, 21, 5); - unsigned len =3D 32 - clen; + unsigned len =3D 32 - a->clen; target_sreg mask0, mask1; TCGv_reg dest; =20 - if (c) { + if (a->c) { nullify_over(ctx); } - if (cpos + len > 32) { - len =3D 32 - cpos; + if (a->cpos + len > 32) { + len =3D 32 - a->cpos; } =20 - dest =3D dest_gpr(ctx, rt); - mask0 =3D deposit64(0, cpos, len, val); - mask1 =3D deposit64(-1, cpos, len, val); + dest =3D dest_gpr(ctx, a->t); + mask0 =3D deposit64(0, a->cpos, len, a->i); + mask1 =3D deposit64(-1, a->cpos, len, a->i); =20 - if (nz) { - TCGv_reg src =3D load_gpr(ctx, rt); + if (a->nz) { + TCGv_reg src =3D load_gpr(ctx, a->t); if (mask1 !=3D -1) { tcg_gen_andi_reg(dest, src, mask1); src =3D dest; @@ -3492,75 +3454,58 @@ static bool trans_depw_imm_c(DisasContext *ctx, uin= t32_t insn, } else { tcg_gen_movi_reg(dest, mask0); } - save_gpr(ctx, rt, dest); + save_gpr(ctx, a->t, dest); =20 /* Install the new nullification. */ cond_free(&ctx->null_cond); - if (c) { - ctx->null_cond =3D do_sed_cond(c, dest); + if (a->c) { + ctx->null_cond =3D do_sed_cond(a->c, dest); } return nullify_end(ctx); } =20 -static bool trans_depw_imm(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static bool trans_depw_imm(DisasContext *ctx, arg_depw_imm *a) { - unsigned clen =3D extract32(insn, 0, 5); - unsigned cpos =3D extract32(insn, 5, 5); - unsigned nz =3D extract32(insn, 10, 1); - unsigned c =3D extract32(insn, 13, 3); - unsigned rr =3D extract32(insn, 16, 5); - unsigned rt =3D extract32(insn, 21, 5); - unsigned rs =3D nz ? rt : 0; - unsigned len =3D 32 - clen; + unsigned rs =3D a->nz ? a->t : 0; + unsigned len =3D 32 - a->clen; TCGv_reg dest, val; =20 - if (c) { + if (a->c) { nullify_over(ctx); } - if (cpos + len > 32) { - len =3D 32 - cpos; + if (a->cpos + len > 32) { + len =3D 32 - a->cpos; } =20 - dest =3D dest_gpr(ctx, rt); - val =3D load_gpr(ctx, rr); + dest =3D dest_gpr(ctx, a->t); + val =3D load_gpr(ctx, a->r); if (rs =3D=3D 0) { - tcg_gen_deposit_z_reg(dest, val, cpos, len); + tcg_gen_deposit_z_reg(dest, val, a->cpos, len); } else { - tcg_gen_deposit_reg(dest, cpu_gr[rs], val, cpos, len); + tcg_gen_deposit_reg(dest, cpu_gr[rs], val, a->cpos, len); } - save_gpr(ctx, rt, dest); + save_gpr(ctx, a->t, dest); =20 /* Install the new nullification. */ cond_free(&ctx->null_cond); - if (c) { - ctx->null_cond =3D do_sed_cond(c, dest); + if (a->c) { + ctx->null_cond =3D do_sed_cond(a->c, dest); } return nullify_end(ctx); } =20 -static bool trans_depw_sar(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static bool do_depw_sar(DisasContext *ctx, unsigned rt, unsigned c, + unsigned nz, unsigned clen, TCGv_reg val) { - unsigned clen =3D extract32(insn, 0, 5); - unsigned nz =3D extract32(insn, 10, 1); - unsigned i =3D extract32(insn, 12, 1); - unsigned c =3D extract32(insn, 13, 3); - unsigned rt =3D extract32(insn, 21, 5); unsigned rs =3D nz ? rt : 0; unsigned len =3D 32 - clen; - TCGv_reg val, mask, tmp, shift, dest; + TCGv_reg mask, tmp, shift, dest; unsigned msb =3D 1U << (len - 1); =20 if (c) { nullify_over(ctx); } =20 - if (i) { - val =3D load_const(ctx, low_sextract(insn, 16, 5)); - } else { - val =3D load_gpr(ctx, extract32(insn, 16, 5)); - } dest =3D dest_gpr(ctx, rt); shift =3D tcg_temp_new(); tmp =3D tcg_temp_new(); @@ -3591,11 +3536,15 @@ static bool trans_depw_sar(DisasContext *ctx, uint3= 2_t insn, return nullify_end(ctx); } =20 -static const DisasInsn table_depw[] =3D { - { 0xd4000000u, 0xfc000be0u, trans_depw_sar }, - { 0xd4000800u, 0xfc001800u, trans_depw_imm }, - { 0xd4001800u, 0xfc001800u, trans_depw_imm_c }, -}; +static bool trans_depw_sar(DisasContext *ctx, arg_depw_sar *a) +{ + return do_depw_sar(ctx, a->t, a->c, a->nz, a->clen, load_gpr(ctx, a->r= )); +} + +static bool trans_depwi_sar(DisasContext *ctx, arg_depwi_sar *a) +{ + return do_depw_sar(ctx, a->t, a->c, a->nz, a->clen, load_const(ctx, a-= >i)); +} =20 static bool trans_be(DisasContext *ctx, uint32_t insn, bool is_l) { @@ -4473,12 +4422,6 @@ static void translate_one(DisasContext *ctx, uint32_= t insn) translate_table(ctx, insn, table_fp_fused); return; =20 - case 0x34: - translate_table(ctx, insn, table_sh_ex); - return; - case 0x35: - translate_table(ctx, insn, table_depw); - return; case 0x38: trans_be(ctx, insn, false); return; diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index e891fbfac5..987cb8738b 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -195,3 +195,18 @@ addb 101000 ..... ..... ... ........... . .= @rrb_cf f=3D0 addb 101010 ..... ..... ... ........... . . @rrb_cf f=3D1 addbi 101001 ..... ..... ... ........... . . @rib_cf f=3D0 addbi 101011 ..... ..... ... ........... . . @rib_cf f=3D1 + +#### +# Shift, Extract, Deposit +#### + +shrpw_sar 110100 r2:5 r1:5 c:3 00 0 00000 t:5 +shrpw_imm 110100 r2:5 r1:5 c:3 01 0 cpos:5 t:5 + +extrw_sar 110100 r:5 t:5 c:3 10 se:1 00000 clen:5 +extrw_imm 110100 r:5 t:5 c:3 11 se:1 pos:5 clen:5 + +depw_sar 110101 t:5 r:5 c:3 00 nz:1 00000 clen:5 +depw_imm 110101 t:5 r:5 c:3 01 nz:1 cpos:5 clen:5 +depwi_sar 110101 t:5 ..... c:3 10 nz:1 00000 clen:5 i=3D%im5_16 +depwi_imm 110101 t:5 ..... c:3 11 nz:1 cpos:5 clen:5 i=3D%im5_16 --=20 2.17.2