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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id c4sm11861031pgq.85.2019.02.11.15.53.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Feb 2019 15:53:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Ju0kTjI209UCLXJK9JoNZjkA22NnBtRT7DAuiRVZe0I=; b=eM3Ut9Q8OhHf/eHwpTKfKXuR4n3UxEo0v3fKALx4rnCNGvNsCyChNUJk9M4shOWu2y v8o+idtV1ZR7V0xmQa/7/U6/7IAoSNTzxfrrnOgRERvg3OZ5sN+1Ttoo7UrSQUdZ+80N jym1TYVkP+2z9RayUAKeiVf41Iwn7bGi1Nel8eC+SCkJTaTPg53+lMWzY3HqeUg8zDdY 977BRlcLpE0W243Sz2j8SHb+pAywtQPJu3/c+ogWhslMLup8RPlPwFOqE/mUXBgqGfb8 DSOtO7DlTBlYWIv+vXkZ6EYkCsZtE2wDjYNU+bWqaj/SWp8rGuTqkxaPK4hbtScQnGvp K/lQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Ju0kTjI209UCLXJK9JoNZjkA22NnBtRT7DAuiRVZe0I=; b=kEIv57Zs/bt9PdNVAWSY/FbNpN3u6GimNrlX2gDw1XwZzK77biWxpaoGhBlVeKSzr6 BG1Zdx73/Z8cAirkcby9H8F1NYhrcfrLk6nnyBeIl4zT/TFWO1jh2Ex7IJt7r0EqKNPT aA+t39cI11/WhiO+n1WxWEKPIqqMgf6uH/s2MMzTrwQIBPf5QEubheOQOyiU/uc3EBe8 ROH8T24hTyNSICuZxOU6bRiVW0wJKyhA3m7nYMqoE0ErEmLI0nqlkUMG9yyva+Mgx/v1 jQLGfWE6rm/eDOEHLNfTtu8PUfJlttYFLrdyh4DBHzb0g/yTXb7As79KXdCDzyZNGhN6 2gtQ== X-Gm-Message-State: AHQUAua+ZMp2YzDVzH/xLejgBlsigm9EpJbObGZBizKUbgGcEvU3ZrZm LlCD3Cxup9JNHCYe8HBgTMf+z1CRAq0= X-Google-Smtp-Source: AHgI3IYyScaFHiLW44M62K/GCaZA4FsigUr15PqHP+iWpf9KBC4R7Kcwcq2gu1niowyLfrmOOfqbEQ== X-Received: by 2002:aa7:8802:: with SMTP id c2mr938329pfo.20.1549929215416; Mon, 11 Feb 2019 15:53:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 11 Feb 2019 15:52:56 -0800 Message-Id: <20190211235258.542-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211235258.542-1-richard.henderson@linaro.org> References: <20190211235258.542-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v3 26/28] target/arm: Add allocation tag storage for system mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 96 +++++++++++++++++++++++++++++++++++++---- 1 file changed, 87 insertions(+), 9 deletions(-) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 09c387e2c7..53c3ed862e 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -28,18 +28,18 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, uint64_t ptr, bool write, uintptr_t ra) { -#ifdef CONFIG_USER_ONLY ARMCPU *cpu =3D arm_env_get_cpu(env); + CPUState *cs =3D CPU(cpu); uint8_t *tags; uintptr_t index; - int flags; =20 - flags =3D page_get_flags(ptr); +#ifdef CONFIG_USER_ONLY + int flags =3D page_get_flags(ptr); =20 if (!(flags & PAGE_VALID) || !(flags & (write ? PAGE_WRITE : PAGE_READ= ))) { /* SIGSEGV */ env->exception.vaddress =3D ptr; - cpu_restore_state(CPU(cpu), ra, true); + cpu_restore_state(cs, ra, true); raise_exception(env, EXCP_DATA_ABORT, 0, 1); } =20 @@ -56,16 +56,94 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, ui= nt64_t ptr, if (tags =3D=3D NULL) { size_t alloc_size =3D TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1); tags =3D page_alloc_target_data(ptr, alloc_size); - assert(tags !=3D NULL); + } +#else + int mmu_idx; + AddressSpace *as; + CPUTLBEntry *te; + CPUIOTLBEntry *iotlbentry; + MemoryRegionSection *section; + MemoryRegion *mr; + FlatView *fv; + hwaddr physaddr, tag_physaddr, tag_len, xlat; + + /* + * Find the TLB entry for this access. + * As a side effect, this also raises an exception for invalid access. + */ + mmu_idx =3D cpu_mmu_index(env, false); + index =3D tlb_index(env, mmu_idx, ptr); + te =3D tlb_entry(env, mmu_idx, ptr); + if (!tlb_hit(write ? tlb_addr_write(te) : te->addr_read, ptr)) { + /* ??? Expose VICTIM_TLB_HIT from accel/tcg/cputlb.c. */ + tlb_fill(cs, ptr, 16, write ? MMU_DATA_STORE : MMU_DATA_LOAD, + mmu_idx, ra); + index =3D tlb_index(env, mmu_idx, ptr); + te =3D tlb_entry(env, mmu_idx, ptr); } =20 + /* If the virtual page MemAttr !=3D Tagged, nothing to do. */ + iotlbentry =3D &env->iotlb[mmu_idx][index]; + if (!iotlbentry->attrs.target_tlb_bit1) { + return NULL; + } + + /* If the board did not allocate tag memory, nothing to do. */ + as =3D cpu_get_address_space(cs, ARMASIdx_TAG); + if (!as) { + return NULL; + } + + /* Find the physical address for the virtual access. */ + section =3D iotlb_to_section(cs, iotlbentry->addr, iotlbentry->attrs); + physaddr =3D ((iotlbentry->addr & TARGET_PAGE_MASK) + ptr + + section->offset_within_address_space + - section->offset_within_region); + + /* Convert to the physical address in tag space. */ + tag_physaddr =3D physaddr >> (LOG2_TAG_GRANULE + 1); + tag_len =3D TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1); + + /* + * Find the tag physical address within the tag address space. + * + * ??? Create a new mmu_idx to cache the rest of this. + * + * ??? If we were assured of exactly one block of normal ram, + * and thus exactly one block of tag ram, then we could validate + * section->mr as ram, use the section offset vs cpu->tag_memory, + * and finish with memory_region_get_ram_ptr. + */ + rcu_read_lock(); + fv =3D address_space_to_flatview(as); + mr =3D flatview_translate(fv, tag_physaddr, &xlat, &tag_len, + write, MEMTXATTRS_UNSPECIFIED); + if (!memory_access_is_direct(mr, write)) { + /* + * This would seem to imply that the guest has marked a + * virtual page as Tagged when the physical page is not RAM. + * Should this raise some sort of bus error? + */ + rcu_read_unlock(); + qemu_log_mask(LOG_GUEST_ERROR, "Tagged virtual page 0x%" PRIx64 + " maps to physical page 0x%" PRIx64 " without RAM\n", + ptr, physaddr); + return NULL; + } + rcu_read_unlock(); + + /* The board should have created tag ram sized correctly. */ + assert(tag_len =3D=3D TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1)); + + /* FIXME: Mark the tag page dirty for migration. */ + + tags =3D qemu_map_ram_ptr(mr->ram_block, xlat); +#endif + + assert(tags !=3D NULL); index =3D extract32(ptr, LOG2_TAG_GRANULE + 1, TARGET_PAGE_BITS - LOG2_TAG_GRANULE - 1); return tags + index; -#else - /* Tag storage not implemented. */ - return NULL; -#endif } =20 static int get_allocation_tag(CPUARMState *env, uint64_t ptr, uintptr_t ra) --=20 2.17.2