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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id b24sm15712567pfe.136.2019.02.11.09.01.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Feb 2019 09:01:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ErMfI2JS9j1itVD/Qxguq0BTJBeC6WWZEVbtfCqUo1k=; b=Cr/2t0XT3FfqcrGBdNXlTS2NAaKEFdzHh321xZtuP+jdDCkDzgHIWhRB8lt33UMRE0 JkFh8QW4HB8wvDKOWhZgqCfCfiLifQ/GMhRCvjXSoWH4Mai1Sg+VeLVIKFo7iqf+y7RF X6TThTKR3dMzmTx2ec5dLYsJ7UEuZOg282M1nrvcziWoHMk2NUyuqFDNsRDUmENLBgxI +NwS0xXFzZyY7806uhbWu4d5dr/mljIedY1Z8YwaGBPGU0RtO9IAxyvfJOGF02M7Wleg WOhLSnmNMcFfah1ebGQ/pKgnBcvEYXztzfijUJa8Tq6cH3R3QF2gy0UsSTcaQ4+8bi0R 8+kQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ErMfI2JS9j1itVD/Qxguq0BTJBeC6WWZEVbtfCqUo1k=; b=k/LMk51jekXHi3dxflfqqO2T4t70YOxg2/xjFysIK869rcDbAaEsiK6/vhacNc1fFR ZMAvQfVymziRYTn/sWkXcD0rhQYNJhMNi/yQuSgRYojogjc8iEvjAXPXZ80xRzzvXm5L znz3T/e9e13GjlijgufU4sUW7PqtgXUcgzNbTejDvexovLaHQ2aaGa08XTFby3wuEFdu BFVOHdMY7oeaU2oy35UM0y4QDkHpe5kITR5fT+S+6INFFNItKzWMfovyUtiFBSwYw6aG maqcD+NtKCN32MmbqqqbUyws1cAKfdMYUfqCV8Lwt/nVM97Vl1iNMaj5e8dflYaUr375 eT6w== X-Gm-Message-State: AHQUAuafsjtDpFO0UX+A1LiSJdu+plYDFYZ61lcEvqrmA2gn+46i1g0S lWFr4iQQ3LkrfeWHDOMGVTZ+DXz38oE= X-Google-Smtp-Source: AHgI3IYIzCBjSmWJNOKKb3zOMrN3KTRqF5zmyXAsmWJacTcpZ6PO9qyRldhogpZVyuA8t8WJ7Plo2Q== X-Received: by 2002:a62:2284:: with SMTP id p4mr11146979pfj.115.1549904504807; Mon, 11 Feb 2019 09:01:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 11 Feb 2019 09:01:36 -0800 Message-Id: <20190211170136.18680-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211170136.18680-1-richard.henderson@linaro.org> References: <20190211170136.18680-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::533 Subject: [Qemu-devel] [PULL 4/4] cputlb: update TLB entry/index after tlb_fill X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" We are failing to take into account that tlb_fill() can cause a TLB resize, which renders prior TLB entry pointers/indices stale. Fix it by re-doing the TLB entry lookups immediately after tlb_fill. Fixes: 86e1eff8bc ("tcg: introduce dynamic TLB sizing", 2019-01-28) Reported-by: Max Filippov Tested-by: Max Filippov Signed-off-by: Emilio G. Cota Message-Id: <20190209162745.12668-3-cota@braap.org> Signed-off-by: Richard Henderson --- accel/tcg/softmmu_template.h | 8 ++++++++ accel/tcg/cputlb.c | 4 ++++ 2 files changed, 12 insertions(+) diff --git a/accel/tcg/softmmu_template.h b/accel/tcg/softmmu_template.h index 1fdd262ea4..e970a8b378 100644 --- a/accel/tcg/softmmu_template.h +++ b/accel/tcg/softmmu_template.h @@ -129,6 +129,8 @@ WORD_TYPE helper_le_ld_name(CPUArchState *env, target_u= long addr, if (!VICTIM_TLB_HIT(ADDR_READ, addr)) { tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, READ_ACCESS_TYPE, mmu_idx, retaddr); + index =3D tlb_index(env, mmu_idx, addr); + entry =3D tlb_entry(env, mmu_idx, addr); } tlb_addr =3D entry->ADDR_READ; } @@ -198,6 +200,8 @@ WORD_TYPE helper_be_ld_name(CPUArchState *env, target_u= long addr, if (!VICTIM_TLB_HIT(ADDR_READ, addr)) { tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, READ_ACCESS_TYPE, mmu_idx, retaddr); + index =3D tlb_index(env, mmu_idx, addr); + entry =3D tlb_entry(env, mmu_idx, addr); } tlb_addr =3D entry->ADDR_READ; } @@ -294,6 +298,8 @@ void helper_le_st_name(CPUArchState *env, target_ulong = addr, DATA_TYPE val, if (!VICTIM_TLB_HIT(addr_write, addr)) { tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, MMU_DATA_STORE, mmu_idx, retaddr); + index =3D tlb_index(env, mmu_idx, addr); + entry =3D tlb_entry(env, mmu_idx, addr); } tlb_addr =3D tlb_addr_write(entry) & ~TLB_INVALID_MASK; } @@ -372,6 +378,8 @@ void helper_be_st_name(CPUArchState *env, target_ulong = addr, DATA_TYPE val, if (!VICTIM_TLB_HIT(addr_write, addr)) { tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, MMU_DATA_STORE, mmu_idx, retaddr); + index =3D tlb_index(env, mmu_idx, addr); + entry =3D tlb_entry(env, mmu_idx, addr); } tlb_addr =3D tlb_addr_write(entry) & ~TLB_INVALID_MASK; } diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index f580e4dd7e..88cc8389e9 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1045,6 +1045,8 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, = target_ulong addr) if (unlikely(!tlb_hit(entry->addr_code, addr))) { if (!VICTIM_TLB_HIT(addr_code, addr)) { tlb_fill(ENV_GET_CPU(env), addr, 0, MMU_INST_FETCH, mmu_idx, 0= ); + index =3D tlb_index(env, mmu_idx, addr); + entry =3D tlb_entry(env, mmu_idx, addr); } assert(tlb_hit(entry->addr_code, addr)); } @@ -1125,6 +1127,8 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, if (!VICTIM_TLB_HIT(addr_write, addr)) { tlb_fill(ENV_GET_CPU(env), addr, 1 << s_bits, MMU_DATA_STORE, mmu_idx, retaddr); + index =3D tlb_index(env, mmu_idx, addr); + tlbe =3D tlb_entry(env, mmu_idx, addr); } tlb_addr =3D tlb_addr_write(tlbe) & ~TLB_INVALID_MASK; } --=20 2.17.2