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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=A8TAMIXN+69/Jk9cvH3CNk1W0843jdUBpea8zUdjfM0=; b=HNZ4pg/PDfGoe5B3SGC/gSoE9xmvAcX6RtnGXeG6dIUZe6/tEi1qhpLbMA05hfW6iI DHi36z73E7gdvDW7rFuTTfBQMzR9iimUzFkhWeid8ajzLHODHxnULMzaaTJi67IzhFJL Tt+5F4iAudruoBEIshwoKRnNBonFOUzpxIo2gys5KFK8PETcx59l3T394MtnVdv2UgH7 k6Xv7AGUhMIS9+ZcS4R70TW7W+WaEfVLrg4ZuxoyAM1RlItaf7ETXVzdOttioLU13Hdv XTC46PSbz60JQN31pMjE0kSAIuYxBebjGlIp7JeYOaMXCy0nn5DpAiiZboEuO3Wog9G5 YCvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=A8TAMIXN+69/Jk9cvH3CNk1W0843jdUBpea8zUdjfM0=; b=B684Ho0znS8jbVTJC8mTygmzUsAs7SVgQ7LYXAep+EpmYItHOcB4E8bXGL0GiCAx0Z vSR1I9rOncR2bt8xHRDNFb6RfmYaLCx6bsDfb9pqzncnyNcFhitlXhoiuBztHICZxhh8 Q4svOgsHWrj87HD8BGpa3BxeUlZq+xa1adv/Mr1BcvZkCylFA6DCAcx3vQnj9Up9qB5v 5p3t8+ySDppUYu7jCSwCs8GD7VnMMsszVOC00bYnhRaKK58RhF+KXIFzz7dSXUb9cnU0 zVqARCEJJJzBBdQeE9ah3W+cC3cFZ0uskOqwemeFNl1XPjSjchWZW5HI7kO0j/IlaoAh 6xNg== X-Gm-Message-State: AHQUAubjazOwCY4/34YBziV+P91DPC/LaQyhMsyezb6fK6jZx1pO4c5v TQT8jzjHMqos9Ndto2B5jnMAvX9vjac= X-Google-Smtp-Source: AHgI3IajHKR4XXUHLrNUBcJGLUQKLdLtaClttC0oDfehRIK0qZK4CSVM/JdvqbEwKCWt41mp3g+FMg== X-Received: by 2002:a17:902:9a84:: with SMTP id w4mr26302882plp.283.1549847340230; Sun, 10 Feb 2019 17:09:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:25 -0800 Message-Id: <20190211010829.29869-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::629 Subject: [Qemu-devel] [PATCH v2 22/26] target/arm: Create tagged ram when MTE is enabled X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/cpu.h | 4 ++++ hw/arm/virt.c | 33 +++++++++++++++++++++++++++++++++ target/arm/cpu.c | 21 ++++++++++++++++++--- 3 files changed, 55 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ca32939483..2626af4a9c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -768,6 +768,9 @@ struct ARMCPU { /* MemoryRegion to use for secure physical accesses */ MemoryRegion *secure_memory; =20 + /* MemoryRegion to use for allocation tag accesses */ + MemoryRegion *tag_memory; + /* For v8M, pointer to the IDAU interface provided by board/SoC */ Object *idau; =20 @@ -2850,6 +2853,7 @@ int cpu_mmu_index(CPUARMState *env, bool ifetch); typedef enum ARMASIdx { ARMASIdx_NS =3D 0, ARMASIdx_S =3D 1, + ARMASIdx_TAG =3D 2, } ARMASIdx; =20 /* Return the Exception Level targeted by debug exceptions. */ diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 99c2b6e60d..dccd1345a1 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1260,6 +1260,21 @@ static void create_secure_ram(VirtMachineState *vms, g_free(nodename); } =20 +static void create_tag_ram(VirtMachineState *vms, MachineState *machine, + MemoryRegion *tag_sysmem) +{ + MemoryRegion *tagram =3D g_new(MemoryRegion, 1); + hwaddr base =3D vms->memmap[VIRT_MEM].base / 32; + hwaddr size =3D machine->ram_size / 32; + + memory_region_init_ram(tagram, NULL, "mach-virt.tag", size, &error_fat= al); + memory_region_add_subregion(tag_sysmem, base, tagram); + + /* ??? Do we really need an fdt entry, or is MemTag enabled sufficient= . */ + /* ??? We appear to need secure tag mem to go with secure mem. */ + /* ??? Does that imply we need a fourth address space? */ +} + static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) { const VirtMachineState *board =3D container_of(binfo, VirtMachineState, @@ -1362,6 +1377,7 @@ static void machvirt_init(MachineState *machine) qemu_irq pic[NUM_IRQS]; MemoryRegion *sysmem =3D get_system_memory(); MemoryRegion *secure_sysmem =3D NULL; + MemoryRegion *tag_sysmem =3D NULL; int n, virt_max_cpus; MemoryRegion *ram =3D g_new(MemoryRegion, 1); bool firmware_loaded =3D bios_name || drive_get(IF_PFLASH, 0, 0); @@ -1518,6 +1534,20 @@ static void machvirt_init(MachineState *machine) "secure-memory", &error_abort); } =20 + /* + * The cpu adds the property iff MemTag is supported. + * If it is, we must allocate the ram to back that up. + */ + if (object_property_find(cpuobj, "tag-memory", NULL)) { + if (!tag_sysmem) { + tag_sysmem =3D g_new(MemoryRegion, 1); + memory_region_init(tag_sysmem, OBJECT(machine), + "tag-memory", UINT64_MAX / 32); + } + object_property_set_link(cpuobj, OBJECT(tag_sysmem), + "tag-memory", &error_abort); + } + object_property_set_bool(cpuobj, true, "realized", &error_fatal); object_unref(cpuobj); } @@ -1540,6 +1570,9 @@ static void machvirt_init(MachineState *machine) create_secure_ram(vms, secure_sysmem); create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hd(1= )); } + if (tag_sysmem) { + create_tag_ram(vms, machine, tag_sysmem); + } =20 vms->highmem_ecam &=3D vms->highmem && (!firmware_loaded || aarch64); =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index edf6e0e1f1..decf95de3e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -851,6 +851,18 @@ void arm_cpu_post_init(Object *obj) =20 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, &error_abort); + +#ifndef CONFIG_USER_ONLY + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && + cpu_isar_feature(aa64_mte, cpu)) { + object_property_add_link(obj, "tag-memory", + TYPE_MEMORY_REGION, + (Object **)&cpu->tag_memory, + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG, + &error_abort); + } +#endif } =20 static void arm_cpu_finalizefn(Object *obj) @@ -1164,16 +1176,19 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) init_cpreg_list(cpu); =20 #ifndef CONFIG_USER_ONLY + cs->num_ases =3D 1; if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { cs->num_ases =3D 2; - if (!cpu->secure_memory) { cpu->secure_memory =3D cs->memory; } cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", cpu->secure_memory); - } else { - cs->num_ases =3D 1; + } + if (cpu->tag_memory !=3D NULL) { + cs->num_ases =3D 3; + cpu_address_space_init(cs, ARMASIdx_TAG, "cpu-tag-memory", + cpu->tag_memory); } cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); =20 --=20 2.17.2