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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1ThSYlTjjjdful+PEa+IzVjavr7hehgRai0NxwGpzTA=; b=lb8pLBzY99qbbnUezoxVC8+N1IJ7AAi2fNowxzt9sV/FSUWgss64EUFGWgDrW3176P 7AU9xlHugcY9U+JJhBHxw0gL96iVsAmdi+QWAGXIGSdhO29dPUuwcUTTrfQ5a7DPYGLV dPdWLruaK4KfivPHZ35kyGllIEAJhoa8CGGt665Ae9wrnVcJ6MkmjwGokxhEfjaQZrXa cory593DEWqeNGx17URLtv7Ej0nnNwK0d9r02xxyz/gVQyHoEaTdnFHGTmcABGk5bwz1 UzJ+tcfRahzgTzozABie++4bZo0XL8EsGrCKTy4MBTu+2II9sEMd02Unqw1roPAkVY/k deYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1ThSYlTjjjdful+PEa+IzVjavr7hehgRai0NxwGpzTA=; b=kjLXM/Iw1Z3M6jj9/V6ple5F+tLb4Vz1316Pi5OGMFr+rQFIThAGwoeBfYkSJ6h5wU AdFKd69zYBZBmnwpHFU3GyQZ43AMHMcLvSL/Od9fYvmIUadykpZe83Z3+f39a2/TJd1e 8Rtosf36fnf10tQSbxHnuc1BvfZEgnWHz13ng7ptwsWpNjGYx9yubI172tYtX0kQhzvp TjLatW74NOWhV0q6CgKfai0Hi1CeRxrF2PEfYuUxRiQybxJwiCfMOCIAb21qPye+42Yo IRSQTcFQ3fki1whhhVvc7RxFEAgP710btsl7pxJpA5KVMYS0tSjqYkMr7esFPiTJAVIG NZow== X-Gm-Message-State: AHQUAuadS3GwHo0d276AmUqx3/ugK1MjDY61H3Nab+ClVBjlmBiIH7YK IrgvJq3hjvQzR+JmGnOcFHVStUihZOA= X-Google-Smtp-Source: AHgI3IYw1XDACfVbfbwxFwwW/MDf3zBGdIE3lCl9UB8/v4IwwY+G9TWLZfwmYhGwXp3hQOWDKRXDjQ== X-Received: by 2002:a17:902:8bc6:: with SMTP id r6mr34676795plo.67.1549847335170; Sun, 10 Feb 2019 17:08:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:21 -0800 Message-Id: <20190211010829.29869-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v2 18/26] target/arm: Implement data cache set allocation tags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is DC GVA and DC GZVA. Signed-off-by: Richard Henderson --- v2: Use allocation_tag_mem + memset. --- target/arm/cpu.h | 4 +++- target/arm/helper-a64.h | 1 + target/arm/helper.c | 16 ++++++++++++++++ target/arm/mte_helper.c | 26 ++++++++++++++++++++++++++ target/arm/translate-a64.c | 9 +++++++++ 5 files changed, 55 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 74633a7a78..ca32939483 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2160,7 +2160,9 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpreg= id) #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) -#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA +#define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600) +#define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700) +#define ARM_LAST_SPECIAL ARM_CP_DC_GZVA #define ARM_CP_FPU 0x1000 #define ARM_CP_SVE 0x2000 #define ARM_CP_NO_GDB 0x4000 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index a00364fb4c..4ad900d36e 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -113,3 +113,4 @@ DEF_HELPER_FLAGS_2(stg, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_2(st2g, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_2(stg_parallel, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_2(st2g_parallel, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_2(dc_gva, TCG_CALL_NO_RWG, void, env, i64) diff --git a/target/arm/helper.c b/target/arm/helper.c index 74bace81e4..9fac3628e5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5820,6 +5820,22 @@ static const ARMCPRegInfo mte_reginfo[] =3D { { .name =3D "CIGDVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 5, .type =3D ARM_CP_NOP, .access =3D PL1_W }, + { .name =3D "GVA", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 4, .opc2 =3D 3, + .access =3D PL0_W, .type =3D ARM_CP_DC_GVA, +#ifndef CONFIG_USER_ONLY + /* Avoid overhead of an access check that always passes in user-mode= */ + .accessfn =3D aa64_zva_access, +#endif + }, + { .name =3D "GZVA", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 4, .opc2 =3D 4, + .access =3D PL0_W, .type =3D ARM_CP_DC_GZVA, +#ifndef CONFIG_USER_ONLY + /* Avoid overhead of an access check that always passes in user-mode= */ + .accessfn =3D aa64_zva_access, +#endif + }, REGINFO_SENTINEL }; #endif diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 13befdbf86..93f7cccee2 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -386,3 +386,29 @@ uint64_t HELPER(st2g_parallel)(CPUARMState *env, uint6= 4_t ptr) { return do_st2g(env, ptr, GETPC(), store_tag1_parallel); } + +void HELPER(dc_gva)(CPUARMState *env, uint64_t ptr) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + int el =3D arm_current_el(env); + uint64_t sctlr =3D arm_sctlr(env, el); + size_t blocklen =3D 4 << cpu->dcz_blocksize; + uint8_t *mem; + int rtag; + + ptr =3D QEMU_ALIGN_DOWN(ptr, blocklen); + + /* Trap if accessing an invalid page. */ + mem =3D allocation_tag_mem(env, ptr, true, GETPC()); + + /* No action if page does not support tags, or if access is disabled. = */ + if (!mem || !allocation_tag_access_enabled(env, el, sctlr)) { + return; + } + + rtag =3D allocation_tag_from_addr(ptr); + rtag |=3D rtag << 4; + + assert(blocklen % (2 << LOG2_TAG_GRANULE) =3D=3D 0); + memset(mem, rtag, blocklen / (2 << LOG2_TAG_GRANULE)); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9bd68d522c..a3bd2e27ef 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1811,6 +1811,15 @@ static void handle_sys(DisasContext *s, uint32_t ins= n, bool isread, tcg_rt =3D cpu_reg(s, rt); gen_helper_dc_zva(cpu_env, tcg_rt); return; + case ARM_CP_DC_GVA: + tcg_rt =3D cpu_reg(s, rt); + gen_helper_dc_gva(cpu_env, tcg_rt); + return; + case ARM_CP_DC_GZVA: + tcg_rt =3D cpu_reg(s, rt); + gen_helper_dc_zva(cpu_env, tcg_rt); + gen_helper_dc_gva(cpu_env, tcg_rt); + return; default: break; } --=20 2.17.2