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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=t1Ac8wdCYYJyzUaPePYMhujZZB6jvuYyMH+INQ2PV8M=; b=zFz7sTPfqDnYF/jbhcnb/KEZRnordxjRQ+IJglgMBj+JArhgiwbROjQ/dQS/WC5oBS kokP0wQ2jKpTS8zfONNip6cMNr6KXQ/OxVSqnlSx0KeJUxFSE98mg8JkncvoupCR8Swd eJHGH7wukmoPPjBivleVo5N3pcMuJj5ztSO3wzGPo6YjbHhn52Otp/+oJTYSwtAwzwhP KrNz40VoDXADBqT7uXDgowgRUBTw9UkGzXMk+QJOmncu13mAfbjO7uSikcLVO3SIsdEV pHveLwIr/O+CZyRrUpsVBdwGGyOpIfUrn2BW27Q29RAvp7jff7Xey1bwjSDUPzlnp7P2 075Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=t1Ac8wdCYYJyzUaPePYMhujZZB6jvuYyMH+INQ2PV8M=; b=gv5own8UJOBFNJPkIUnmuPjH0p9nVh6OgKSTCRJmhlOAO22iWhLT5Q+GxFVbhkahGd HIsKxeYj01KRXPRCsFY+by5lJknBZlQLBx/PG9Kp1kD5LYKItRye4EklG1O0UQN1TERF SugC05slh23JQi2Xn5bXxD86li66aIJAGv5Qv5E7Ac0mKPo3VpQFUPJ9wn3IjDXrARK/ gn3ZZeX221SaB2imPaxt2xPVJAN1ktbvWywY5V5ncwjBnAVH0RlfBVULqBNpJJDIiaT0 YJwK23cKSwg7oEuNYZnyPczM1vzYDrP16OZY0Jtt3MWVP4it1AgxM3gZYTj5KhbJQP1/ ThKw== X-Gm-Message-State: AHQUAuaVyzkpMz0H34BZpFh8M27uu/GLPKFxfRkxzLTaLozVh0ZmEAjU aJBYsn9xw/8Srbr7rjm5Du3a4FtIyxo= X-Google-Smtp-Source: AHgI3IYiIUwYIo6VwmTJpKdu/B3dPQDQYsQ9q4KVdJ6wcaCElD/EeOHjCzlkFdAivK3Z02Vmd07hRA== X-Received: by 2002:a63:5462:: with SMTP id e34mr20081740pgm.97.1549847313272; Sun, 10 Feb 2019 17:08:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:04 -0800 Message-Id: <20190211010829.29869-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v2 01/26] target/arm: Split out arm_sctlr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Minimize the number of places that will need updating when the virtual host extensions are added. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 26 ++++++++++++++++---------- target/arm/helper.c | 8 ++------ 2 files changed, 18 insertions(+), 16 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 29663a264d..20be9fb53a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2987,11 +2987,20 @@ static inline bool arm_sctlr_b(CPUARMState *env) (env->cp15.sctlr_el[1] & SCTLR_B) !=3D 0; } =20 +static inline uint64_t arm_sctlr(CPUARMState *env, int el) +{ + if (el =3D=3D 0) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + return env->cp15.sctlr_el[1]; + } else { + return env->cp15.sctlr_el[el]; + } +} + + /* Return true if the processor is in big-endian mode. */ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) { - int cur_el; - /* In 32bit endianness is determined by looking at CPSR's E bit */ if (!is_a64(env)) { return @@ -3010,15 +3019,12 @@ static inline bool arm_cpu_data_is_big_endian(CPUAR= MState *env) arm_sctlr_b(env) || #endif ((env->uncached_cpsr & CPSR_E) ? 1 : 0); + } else { + int cur_el =3D arm_current_el(env); + uint64_t sctlr =3D arm_sctlr(env, cur_el); + + return (sctlr & (cur_el ? SCTLR_EE : SCTLR_E0E)) !=3D 0; } - - cur_el =3D arm_current_el(env); - - if (cur_el =3D=3D 0) { - return (env->cp15.sctlr_el[1] & SCTLR_E0E) !=3D 0; - } - - return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) !=3D 0; } =20 #include "exec/cpu-all.h" diff --git a/target/arm/helper.c b/target/arm/helper.c index 520ceea7a4..d4abbb5076 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13796,12 +13796,8 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target= _ulong *pc, flags =3D FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); } =20 - if (current_el =3D=3D 0) { - /* FIXME: ARMv8.1-VHE S2 translation regime. */ - sctlr =3D env->cp15.sctlr_el[1]; - } else { - sctlr =3D env->cp15.sctlr_el[current_el]; - } + sctlr =3D arm_sctlr(env, current_el); + if (cpu_isar_feature(aa64_pauth, cpu)) { /* * In order to save space in flags, we record only whether --=20 2.17.2 From nobody Fri May 3 10:47:40 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549847471971900.8783224825436; Sun, 10 Feb 2019 17:11:11 -0800 (PST) Received: from localhost ([127.0.0.1]:42102 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt07i-000777-KB for importer@patchew.org; Sun, 10 Feb 2019 20:11:02 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37139) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt05X-0005Sa-Ix for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:08:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gt05S-00085F-1X for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:08:44 -0500 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:46859) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gt05N-0007yC-49 for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:08:39 -0500 Received: by mail-pl1-x641.google.com with SMTP id o6so4487133pls.13 for ; Sun, 10 Feb 2019 17:08:35 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.33 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hbKS6AD3am/sY2oZ+gJOc5vr5/ws9wlGISFwMC+r3mY=; b=q0QbfSM7mQnomNySomDc9n9qQHWL6/bfueUP6si8383ziySXHEE4mIsY4X/4o7Qe6s TprNvXnR33w7Bx6NgL/1D4lfyLoj6o5FhsE+q+vRgMStEsLavXet4mYDnHXYRHSAblsk g1f0ikcNDKFhhlZncXd3+Iwd1JEDnYnJEGeLMMTsSRlg7yIktWKVkmRAcct5IfJTg0O/ RApYXKwC03SnO2hbzrlqlOuJGwX4FHfWMIoZZ4J+JzY/qMgn6crSWw5l/mcV/DJLIhwS MWyPrq+vJOpbFLW10gPvDxmJocKC+Pu/HHZkRmcBnR+aAeZ9aHG/K+lMWC2Pc2jnJecY ySHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hbKS6AD3am/sY2oZ+gJOc5vr5/ws9wlGISFwMC+r3mY=; b=KGw+WRroOsk3utN/2c/9YCq8QH7DlFbQv5TkVx5w53BUTMxX55Yy68iq96KqLqS6Dy suM/QcjAuZuz/Kp7BbI7dUbBBpECCdTIZOEoPpkf79erTrWh2jKeWDXLZ0XBm8WuMzaG b6bcgcCjg48y9Rvd+gkOZpHY2Onkpsx8+6gnEbwWYmaQ6YYoT2Ur3yx2Tt4EapumFxPR 4CB/Ksg8iO47Hdb/1Orv10FgEanrRIEnzxP/do1pLiJrcR/Cqcs+YKpoNrt5vAdej518 DO5p1CUt5XtpAiZYkaPHfB7ynJLWZfgJpXOL8/P35FyiCQj5+uJwpe5JqhlGYDNMZstk hpdA== X-Gm-Message-State: AHQUAubjN926qmHO8UQziL2ELK8bngI+ylKuQtzPqc8gR3rwrsDD6I3N frVQqzJ6xpRxI91USMF4NvIIeHPpERE= X-Google-Smtp-Source: AHgI3IY346xSKGzDLHVH7L7918SiY+bfVAccsnfEUP+35TwFzBoZh16xB5qAO4mxf2hh8dHNysi6bQ== X-Received: by 2002:a17:902:a50e:: with SMTP id s14mr23327027plq.311.1549847314566; Sun, 10 Feb 2019 17:08:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:05 -0800 Message-Id: <20190211010829.29869-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v2 02/26] target/arm: Split helper_msr_i_pstate into 3 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The EL0+UMA check is unique to DAIF. While SPSel had avoided the check by nature of already checking EL >=3D 1, the other post v8.0 extensions to MSR (imm) allow EL0 and do not require UMA. Avoid the unconditional write to pc and use raise_exception_ra to unwind. Signed-off-by: Richard Henderson --- target/arm/helper-a64.h | 3 +++ target/arm/helper.h | 1 - target/arm/internals.h | 15 ++++++++++++++ target/arm/helper-a64.c | 30 +++++++++++++++++++++++++++ target/arm/op_helper.c | 42 -------------------------------------- target/arm/translate-a64.c | 41 ++++++++++++++++++++++--------------- 6 files changed, 73 insertions(+), 59 deletions(-) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index aff8d6c9f3..a915c1247f 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -19,6 +19,9 @@ DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64) DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64) +DEF_HELPER_2(msr_i_spsel, void, env, i32) +DEF_HELPER_2(msr_i_daifset, void, env, i32) +DEF_HELPER_2(msr_i_daifclear, void, env, i32) DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr) DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr) DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr) diff --git a/target/arm/helper.h b/target/arm/helper.h index 53a38188c6..28b1dd6252 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -77,7 +77,6 @@ DEF_HELPER_2(get_cp_reg, i32, env, ptr) DEF_HELPER_3(set_cp_reg64, void, env, ptr, i64) DEF_HELPER_2(get_cp_reg64, i64, env, ptr) =20 -DEF_HELPER_3(msr_i_pstate, void, env, i32, i32) DEF_HELPER_1(clear_pstate_ss, void, env) =20 DEF_HELPER_2(get_r13_banked, i32, env, i32) diff --git a/target/arm/internals.h b/target/arm/internals.h index a4bd1becb7..587a1ddf58 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -968,4 +968,19 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *e= nv, uint64_t va, ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data); =20 +static inline int exception_target_el(CPUARMState *env) +{ + int target_el =3D MAX(1, arm_current_el(env)); + + /* + * No such thing as secure EL1 if EL3 is aarch32, + * so update the target EL to EL3 in this case. + */ + if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el =3D=3D = 1) { + target_el =3D 3; + } + + return target_el; +} + #endif diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 101fa6d3ea..87b8f36122 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -61,6 +61,36 @@ uint64_t HELPER(rbit64)(uint64_t x) return revbit64(x); } =20 +void HELPER(msr_i_spsel)(CPUARMState *env, uint32_t imm) +{ + update_spsel(env, imm); +} + +static void daif_check(CPUARMState *env, uint32_t op, + uint32_t imm, uintptr_t ra) +{ + /* DAIF update to PSTATE. This is OK from EL0 only if UMA is set. */ + if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_UM= A)) { + raise_exception_ra(env, EXCP_UDEF, + syn_aa64_sysregtrap(0, extract32(op, 0, 3), + extract32(op, 3, 3), 4, + imm, 0x1f, 0), + exception_target_el(env), ra); + } +} + +void HELPER(msr_i_daifset)(CPUARMState *env, uint32_t imm) +{ + daif_check(env, 0x1e, imm, GETPC()); + env->daif |=3D (imm << 6) & PSTATE_DAIF; +} + +void HELPER(msr_i_daifclear)(CPUARMState *env, uint32_t imm) +{ + daif_check(env, 0x1f, imm, GETPC()); + env->daif &=3D ~((imm << 6) & PSTATE_DAIF); +} + /* Convert a softfloat float_relation_ (as returned by * the float*_compare functions) to the correct ARM * NZCV flag state. diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index c998eadfaa..c5721a866d 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -68,20 +68,6 @@ void raise_exception_ra(CPUARMState *env, uint32_t excp,= uint32_t syndrome, cpu_loop_exit_restore(cs, ra); } =20 -static int exception_target_el(CPUARMState *env) -{ - int target_el =3D MAX(1, arm_current_el(env)); - - /* No such thing as secure EL1 if EL3 is aarch32, so update the target= EL - * to EL3 in this case. - */ - if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el =3D=3D = 1) { - target_el =3D 3; - } - - return target_el; -} - uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, void *vn, uint32_t maxindex) { @@ -875,34 +861,6 @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *= rip) return res; } =20 -void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, uint32_t imm) -{ - /* MSR_i to update PSTATE. This is OK from EL0 only if UMA is set. - * Note that SPSel is never OK from EL0; we rely on handle_msr_i() - * to catch that case at translate time. - */ - if (arm_current_el(env) =3D=3D 0 && !(env->cp15.sctlr_el[1] & SCTLR_UM= A)) { - uint32_t syndrome =3D syn_aa64_sysregtrap(0, extract32(op, 0, 3), - extract32(op, 3, 3), 4, - imm, 0x1f, 0); - raise_exception(env, EXCP_UDEF, syndrome, exception_target_el(env)= ); - } - - switch (op) { - case 0x05: /* SPSel */ - update_spsel(env, imm); - break; - case 0x1e: /* DAIFSet */ - env->daif |=3D (imm << 6) & PSTATE_DAIF; - break; - case 0x1f: /* DAIFClear */ - env->daif &=3D ~((imm << 6) & PSTATE_DAIF); - break; - default: - g_assert_not_reached(); - } -} - void HELPER(clear_pstate_ss)(CPUARMState *env) { env->pstate &=3D ~PSTATE_SS; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 27b90d5778..13e010d27b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1647,29 +1647,38 @@ static void handle_sync(DisasContext *s, uint32_t i= nsn, static void handle_msr_i(DisasContext *s, uint32_t insn, unsigned int op1, unsigned int op2, unsigned int = crm) { + TCGv_i32 t1; int op =3D op1 << 3 | op2; + + /* End the TB by default, chaining is ok. */ + s->base.is_jmp =3D DISAS_TOO_MANY; + switch (op) { case 0x05: /* SPSel */ if (s->current_el =3D=3D 0) { - unallocated_encoding(s); - return; + goto do_unallocated; } - /* fall through */ - case 0x1e: /* DAIFSet */ - case 0x1f: /* DAIFClear */ - { - TCGv_i32 tcg_imm =3D tcg_const_i32(crm); - TCGv_i32 tcg_op =3D tcg_const_i32(op); - gen_a64_set_pc_im(s->pc - 4); - gen_helper_msr_i_pstate(cpu_env, tcg_op, tcg_imm); - tcg_temp_free_i32(tcg_imm); - tcg_temp_free_i32(tcg_op); - /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. = */ - gen_a64_set_pc_im(s->pc); - s->base.is_jmp =3D (op =3D=3D 0x1f ? DISAS_EXIT : DISAS_JUMP); + t1 =3D tcg_const_i32(crm & PSTATE_SP); + gen_helper_msr_i_spsel(cpu_env, t1); + tcg_temp_free_i32(t1); break; - } + + case 0x1e: /* DAIFSet */ + t1 =3D tcg_const_i32(crm); + gen_helper_msr_i_daifset(cpu_env, t1); + tcg_temp_free_i32(t1); + break; + + case 0x1f: /* DAIFClear */ + t1 =3D tcg_const_i32(crm); + gen_helper_msr_i_daifclear(cpu_env, t1); + tcg_temp_free_i32(t1); + /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. = */ + s->base.is_jmp =3D DISAS_UPDATE; + break; + default: + do_unallocated: unallocated_encoding(s); return; } --=20 2.17.2 From nobody Fri May 3 10:47:40 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549847819351567.9722772564504; Sun, 10 Feb 2019 17:16:59 -0800 (PST) Received: from localhost ([127.0.0.1]:42187 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt0DM-0003RN-51 for importer@patchew.org; Sun, 10 Feb 2019 20:16:52 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37315) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt05l-0005ik-6h for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gt05i-0008O3-Ib for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:01 -0500 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:40736) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gt05i-0007za-5I for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:08:58 -0500 Received: by mail-pf1-x442.google.com with SMTP id h1so1653993pfo.7 for ; Sun, 10 Feb 2019 17:08:37 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ItNJF+IPQ2RCWNqC/N6zjDNVc+cTfSXBzvGik2fXPgw=; b=EQslcFmeP6zD+i79OugPlC+uJRaMb1tZ+Y2s3/tMfGfvNocqaYyxRqxeWUpHPTAXUJ c/3ZYRKIdW3jyTPYwtN1qwJzls3DqxaNXON2BSlmIVzsQIWD8XIahQeKuWYUxQamMey3 F54jNjMPVaOj2Cqf+CH8fin2KBtA7AC/4d4FX73Www23h3AVN9yzQMpkoWyydVZkOh7e 28WDmyxFVjRJ4OzyxvK8qdPat1C661UBo8MqyO6Gd97iQOcmEEiE3MEeaSdLwBCVV9MW l2iJAycJqwBCkif/OQj5P5iQ+B4BrHE0hwYDTWWUQ+ujMS7tiw9NRsLi19+u3bCaOfoD ycPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ItNJF+IPQ2RCWNqC/N6zjDNVc+cTfSXBzvGik2fXPgw=; b=ul+RfAplHa5IuKgQIMe83mC/52Ic2vM/pQxZMUYugdeDN5W9YZhUeMu+7eo1ePKaiK 9QcMldDq4bssjaG8UfliDZD+UMXGHxk6+6RYWeox6KrUXSCxoFZ9ThJpAf6L2GCsIoMa mzWDQ9bRJK4SrmQcDUSDLwMAG+R1s4ZjfXqRxOHCZqBqAP8A1LVEFwjBHvEJTk5NWzYX dyM2Mfk54jzEClxw/043ybVsKIzhCMdzFAWmQr3s7OcTb4mBI2hUO0lqb5rnzY+Ktx2g 4l6JlyT0Kxnxs/kX1VQrrLQHbxLyEMnoYHtMEYsYrySLUNhq/cjzjJrybl5r+hKY80Sf /7iQ== X-Gm-Message-State: AHQUAuZDOKWY0fhpbEbK/F5zLS3q0hl3D+JA5aWPQYz3I1GTLV3/jG6o ufzxnCIDz0xCv0jlPPn8MqmvJmBmO5Q= X-Google-Smtp-Source: AHgI3IblyI65G6y2m1tThjo0QGec9vdoMzSu1Z6WEl6/nwkLpcHP03RBPAetYROtN1oz8yDUC3DGaw== X-Received: by 2002:a63:580f:: with SMTP id m15mr26451747pgb.342.1549847315806; Sun, 10 Feb 2019 17:08:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:06 -0800 Message-Id: <20190211010829.29869-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v2 03/26] target/arm: Add clear_pstate_bits, share gen_ss_advance X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We do not need an out-of-line helper for clearing bits in pstate. While changing things, share the implementation of gen_ss_advance. Signed-off-by: Richard Henderson --- target/arm/helper.h | 2 -- target/arm/translate.h | 19 +++++++++++++++++++ target/arm/op_helper.c | 5 ----- target/arm/translate-a64.c | 11 ----------- target/arm/translate.c | 11 ----------- 5 files changed, 19 insertions(+), 29 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 28b1dd6252..c21fa2edfe 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -77,8 +77,6 @@ DEF_HELPER_2(get_cp_reg, i32, env, ptr) DEF_HELPER_3(set_cp_reg64, void, env, ptr, i64) DEF_HELPER_2(get_cp_reg64, i64, env, ptr) =20 -DEF_HELPER_1(clear_pstate_ss, void, env) - DEF_HELPER_2(get_r13_banked, i32, env, i32) DEF_HELPER_3(set_r13_banked, void, env, i32, i32) =20 diff --git a/target/arm/translate.h b/target/arm/translate.h index 17748ddfb9..33af50a13f 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -202,6 +202,25 @@ static inline TCGv_i32 get_ahp_flag(void) return ret; } =20 +/* Clear bits within PSTATE. */ +static inline void clear_pstate_bits(uint32_t bits) +{ + TCGv_i32 p =3D tcg_temp_new_i32(); + + tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate)); + tcg_gen_andi_i32(p, p, ~bits); + tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate)); + tcg_temp_free_i32(p); +} + +/* If the singlestep state is Active-not-pending, advance to Active-pendin= g. */ +static inline void gen_ss_advance(DisasContext *s) +{ + if (s->ss_active) { + s->pstate_ss =3D 0; + clear_pstate_bits(PSTATE_SS); + } +} =20 /* Vector operations shared between ARM and AArch64. */ extern const GVecGen3 bsl_op; diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index c5721a866d..8698b4dc83 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -861,11 +861,6 @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *= rip) return res; } =20 -void HELPER(clear_pstate_ss)(CPUARMState *env) -{ - env->pstate &=3D ~PSTATE_SS; -} - void HELPER(pre_hvc)(CPUARMState *env) { ARMCPU *cpu =3D arm_env_get_cpu(env); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 13e010d27b..ba139bba26 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -421,17 +421,6 @@ static void gen_exception_bkpt_insn(DisasContext *s, i= nt offset, s->base.is_jmp =3D DISAS_NORETURN; } =20 -static void gen_ss_advance(DisasContext *s) -{ - /* If the singlestep state is Active-not-pending, advance to - * Active-pending. - */ - if (s->ss_active) { - s->pstate_ss =3D 0; - gen_helper_clear_pstate_ss(cpu_env); - } -} - static void gen_step_complete_exception(DisasContext *s) { /* We just completed step of an insn. Move from Active-not-pending diff --git a/target/arm/translate.c b/target/arm/translate.c index 66cf28c8cb..baf6068ec1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -298,17 +298,6 @@ static void gen_exception(int excp, uint32_t syndrome,= uint32_t target_el) tcg_temp_free_i32(tcg_excp); } =20 -static void gen_ss_advance(DisasContext *s) -{ - /* If the singlestep state is Active-not-pending, advance to - * Active-pending. - */ - if (s->ss_active) { - s->pstate_ss =3D 0; - gen_helper_clear_pstate_ss(cpu_env); - } -} - static void gen_step_complete_exception(DisasContext *s) { /* We just completed step of an insn. Move from Active-not-pending --=20 2.17.2 From nobody Fri May 3 10:47:40 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549847790646284.3296480732258; Sun, 10 Feb 2019 17:16:30 -0800 (PST) Received: from localhost ([127.0.0.1]:42185 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt0Cu-00034R-81 for importer@patchew.org; Sun, 10 Feb 2019 20:16:24 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37160) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt05d-0005Za-0h for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:08:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gt05X-0008A2-8e for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:08:52 -0500 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:43588) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gt05Q-00082b-5x for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:08:42 -0500 Received: by mail-pg1-x541.google.com with SMTP id v28so4197817pgk.10 for ; Sun, 10 Feb 2019 17:08:38 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=u8vIigM0XidhvWGsqidNf3fdHBLrU/fl3iVBMrH5xqs=; b=H2lbbNAIgpOSDrAmUvk0pdNFdbGT4e+wgn3fXiWBHae8DqIBZo8AC0vX7ug64JEnhA KqPFM2Xd+y5legzS7ai+6XCZ4Cx5Ua5VcKSDqZiDX1JWj6Rb9AqEfYYQ2ZKGssC2/sGU Vlc1LzMdv1uDVwuC0ahfpdhUUNBYmcAuK1UXZxcaKBWqpDPgGYz/EyIR7WMMQbxWvGiG +nBIMTqqVLVC15/1zm2PPINTQCNLJUCpPLkt/X3OUdzQL2fss7rl4QvhkvdvZJZdn7N8 yKQm9ekplC9VQ7Rf215HrxNsCDozyUSVGPCG7uMkqIuwaeetau6eIZIqNj/4LURDCCQ6 uI0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=u8vIigM0XidhvWGsqidNf3fdHBLrU/fl3iVBMrH5xqs=; b=jrLzAQCk4+DASwuFkICxVaJDLuVSpWu9FCHPDX0d+al2Xp2uM0GBOnC4N8IxOXoZWW nGuDEynWHZOdm7/tumsBrvSlgDOdyKxeFX3SYh4SkWOxOUDaWmmhzLiJ5MqxYlQAgH43 YCzrcRuE8BAkoMmqqsyIvutHZ/UVE79uEP2toxwF7XfrFPvEeXQKkebjxngoKjoFtp+o tY+VTWENp9E669SMmJFCsucho5fufS36PImr+wIvtYaYkFwK7v5+5gac+YcBeuhABoFs A2OpT98mdlRedsPHEBDkSqD/iZUfluE9pzQVqgX1Ywu8jQQZBncB00Cx6kM9+3Kn5AGw XgNw== X-Gm-Message-State: AHQUAuZMIo/zMKyUNv8/94neEiIw91ZWYsmgYg4WnYqYV1x94SP6glPU RfS0T3Kwq+wxoX98FetoJbISu93b/Rc= X-Google-Smtp-Source: AHgI3Ibj6g5kymn4yWJ3x4HmkiUmUdeTvMZ+LIgu6oRr+pvIqo26+UtUNShY6OBV6V6j3VqItgXlvw== X-Received: by 2002:a63:eb02:: with SMTP id t2mr31641029pgh.57.1549847317127; Sun, 10 Feb 2019 17:08:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:07 -0800 Message-Id: <20190211010829.29869-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v2 04/26] target/arm: Add MTE_ACTIVE to tb_flags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When MTE is fully enabled, i.e. access to tags are enabled and tag checks affect the PE, then arrange to perform the check while stripping the TBI. The check is not yet implemented, just the plumbing to that point. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Clean TBI bits exactly. Fix license to lgpl 2.1. --- target/arm/cpu.h | 12 ++++++++ target/arm/helper-a64.h | 2 ++ target/arm/internals.h | 18 ++++++++++++ target/arm/translate.h | 2 ++ target/arm/helper.c | 51 ++++++++++++++++++++++++++-------- target/arm/mte_helper.c | 57 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 9 +++++- target/arm/Makefile.objs | 2 +- 8 files changed, 140 insertions(+), 13 deletions(-) create mode 100644 target/arm/mte_helper.c diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 20be9fb53a..2776df6981 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1215,6 +1215,7 @@ void pmu_init(ARMCPU *cpu); #define PSTATE_BTYPE (3U << 10) #define PSTATE_IL (1U << 20) #define PSTATE_SS (1U << 21) +#define PSTATE_TCO (1U << 25) #define PSTATE_V (1U << 28) #define PSTATE_C (1U << 29) #define PSTATE_Z (1U << 30) @@ -3071,6 +3072,7 @@ FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) FIELD(TBFLAG_A64, BT, 9, 1) FIELD(TBFLAG_A64, BTYPE, 10, 2) FIELD(TBFLAG_A64, TBID, 12, 2) +FIELD(TBFLAG_A64, MTE_ACTIVE, 14, 1) =20 static inline bool bswap_code(bool sctlr_b) { @@ -3361,6 +3363,16 @@ static inline bool isar_feature_aa64_bti(const ARMIS= ARegisters *id) return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) !=3D 0; } =20 +static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *i= d) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) !=3D 0; +} + +static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >=3D 2; +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index a915c1247f..fa4c371a47 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -102,3 +102,5 @@ DEF_HELPER_FLAGS_3(autda, TCG_CALL_NO_WG, i64, env, i64= , i64) DEF_HELPER_FLAGS_3(autdb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_2(xpaci, TCG_CALL_NO_RWG_SE, i64, env, i64) DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) + +DEF_HELPER_FLAGS_2(mte_check, TCG_CALL_NO_WG, i64, env, i64) diff --git a/target/arm/internals.h b/target/arm/internals.h index 587a1ddf58..6c018e773c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -983,4 +983,22 @@ static inline int exception_target_el(CPUARMState *env) return target_el; } =20 +/* Determine if allocation tags are available. */ +static inline bool allocation_tag_access_enabled(CPUARMState *env, int el, + uint64_t sctlr) +{ + if (el < 3 + && arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_ATA)) { + return false; + } + if (el < 2 + && arm_feature(env, ARM_FEATURE_EL2) + && !(arm_hcr_el2_eff(env) & HCR_ATA)) { + return false; + } + sctlr &=3D (el =3D=3D 0 ? SCTLR_ATA0 : SCTLR_ATA); + return sctlr !=3D 0; +} + #endif diff --git a/target/arm/translate.h b/target/arm/translate.h index 33af50a13f..5a101e1c6d 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -70,6 +70,8 @@ typedef struct DisasContext { bool ss_same_el; /* True if v8.3-PAuth is active. */ bool pauth_active; + /* True if v8.5-MTE tag checks affect the PE. */ + bool mte_active; /* True with v8.5-BTI and SCTLR_ELx.BT* set. */ bool bt; /* diff --git a/target/arm/helper.c b/target/arm/helper.c index d4abbb5076..e73bdbf041 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1862,6 +1862,9 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) if (cpu_isar_feature(aa64_pauth, cpu)) { valid_mask |=3D SCR_API | SCR_APK; } + if (cpu_isar_feature(aa64_mte, cpu)) { + valid_mask |=3D SCR_ATA; + } =20 /* Clear all-context RES0 bits. */ value &=3D valid_mask; @@ -4056,22 +4059,31 @@ static void sctlr_write(CPUARMState *env, const ARM= CPRegInfo *ri, { ARMCPU *cpu =3D arm_env_get_cpu(env); =20 - if (raw_read(env, ri) =3D=3D value) { - /* Skip the TLB flush if nothing actually changed; Linux likes - * to do a lot of pointless SCTLR writes. - */ - return; - } - if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { /* M bit is RAZ/WI for PMSA with no MPU implemented */ value &=3D ~SCTLR_M; } =20 - raw_write(env, ri, value); + if (!cpu_isar_feature(aa64_mte, cpu)) { + if (ri->opc1 =3D=3D 6) { /* SCTLR_EL3 */ + value &=3D ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA); + } else { + value &=3D ~(SCTLR_ITFSB | SCTLR_TCF0 | SCTLR_TCF | + SCTLR_ATA0 | SCTLR_ATA); + } + } + /* ??? Lots of these bits are not implemented. */ - /* This may enable/disable the MMU, so do a TLB flush. */ - tlb_flush(CPU(cpu)); + + if (raw_read(env, ri) !=3D value) { + /* + * This may enable/disable the MMU, so do a TLB flush. + * Skip the TLB flush if nothing actually changed; + * Linux likes to do a lot of pointless SCTLR writes. + */ + raw_write(env, ri, value); + tlb_flush(CPU(cpu)); + } } =20 static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo = *ri, @@ -4564,6 +4576,9 @@ static void hcr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) if (cpu_isar_feature(aa64_pauth, cpu)) { valid_mask |=3D HCR_API | HCR_APK; } + if (cpu_isar_feature(aa64_mte, cpu)) { + valid_mask |=3D HCR_ATA; + } =20 /* Clear RES0 bits. */ value &=3D valid_mask; @@ -13756,6 +13771,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, if (is_a64(env)) { ARMCPU *cpu =3D arm_env_get_cpu(env); uint64_t sctlr; + int tbid; =20 *pc =3D env->pc; flags =3D FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); @@ -13764,7 +13780,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, { ARMMMUIdx stage1 =3D stage_1_mmu_idx(mmu_idx); ARMVAParameters p0 =3D aa64_va_parameters_both(env, 0, stage1); - int tbii, tbid; + int tbii; =20 /* FIXME: ARMv8.1-VHE S2 translation regime. */ if (regime_el(env, stage1) < 2) { @@ -13817,6 +13833,19 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target= _ulong *pc, } flags =3D FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); } + + /* + * If MTE is enabled, and tag checks affect the PE, + * then we check the tag as we strip the TBI field. + * Note that if TBI is disabled, all accesses are unchecked. + */ + if (tbid + && cpu_isar_feature(aa64_mte, cpu) + && allocation_tag_access_enabled(env, current_el, sctlr) + && !(env->pstate & PSTATE_TCO) + && (sctlr & (current_el =3D=3D 0 ? SCTLR_TCF0 : SCTLR_TCF))) { + flags =3D FIELD_DP32(flags, TBFLAG_A64, MTE_ACTIVE, 1); + } } else { *pc =3D env->regs[15]; flags =3D FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c new file mode 100644 index 0000000000..f1174d6f9f --- /dev/null +++ b/target/arm/mte_helper.c @@ -0,0 +1,57 @@ +/* + * ARM v8.5-MemTag Operations + * + * Copyright (c) 2019 Linaro, Ltd. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" +#include "exec/exec-all.h" +#include "exec/cpu_ldst.h" +#include "exec/helper-proto.h" + + +static uint64_t strip_tbi(CPUARMState *env, uint64_t ptr) +{ + /* + * We know some TBI is enabled, because MTE is enabled enough to + * arrive here. We simply need to check how to apply the TBI strip. + */ + if (arm_current_el(env) >=3D 2) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + /* Only one address space half, and TBI enabled. */ + return extract64(ptr, 0, 56); + } else { + /* + * Two address space halves, but we don't know for sure that + * TBI is enabled for both halves. Check. + */ + uint64_t tcr =3D env->cp15.tcr_el[1].raw_tcr; + bool tbi =3D extract64(tcr, 37 + extract64(ptr, 55, 1), 1); + + if (tbi) { + return sextract64(ptr, 0, 56); + } + return ptr; + } +} + +uint64_t HELPER(mte_check)(CPUARMState *env, uint64_t ptr) +{ + /* Only unchecked implemented so far. */ + return strip_tbi(env, ptr); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ba139bba26..e782a0e579 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -343,7 +343,13 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 s= rc) static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) { TCGv_i64 clean =3D new_tmp_a64(s); - gen_top_byte_ignore(s, clean, addr, s->tbid); + + /* FIXME: SP+OFS is always unchecked. */ + if (s->tbid && s->mte_active) { + gen_helper_mte_check(clean, cpu_env, addr); + } else { + gen_top_byte_ignore(s, clean, addr, s->tbid); + } return clean; } =20 @@ -14041,6 +14047,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->pauth_active =3D FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE); dc->bt =3D FIELD_EX32(tb_flags, TBFLAG_A64, BT); dc->btype =3D FIELD_EX32(tb_flags, TBFLAG_A64, BTYPE); + dc->mte_active =3D FIELD_EX32(tb_flags, TBFLAG_A64, MTE_ACTIVE); dc->vec_len =3D 0; dc->vec_stride =3D 0; dc->cp_regs =3D arm_cpu->cp_regs; diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 1a4fc06448..c86cb1af5c 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -8,7 +8,7 @@ obj-y +=3D translate.o op_helper.o helper.o cpu.o obj-y +=3D neon_helper.o iwmmxt_helper.o vec_helper.o obj-y +=3D gdbstub.o obj-$(TARGET_AARCH64) +=3D cpu64.o translate-a64.o helper-a64.o gdbstub64.o -obj-$(TARGET_AARCH64) +=3D pauth_helper.o +obj-$(TARGET_AARCH64) +=3D pauth_helper.o mte_helper.o obj-y +=3D crypto_helper.o obj-$(CONFIG_SOFTMMU) +=3D arm-powerctl.o =20 --=20 2.17.2 From nobody Fri May 3 10:47:40 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549847862210298.0698369581587; Sun, 10 Feb 2019 17:17:42 -0800 (PST) Received: from localhost ([127.0.0.1]:42189 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt0E7-00040D-56 for importer@patchew.org; Sun, 10 Feb 2019 20:17:39 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37321) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt05l-0005iu-9Q for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gt05i-0008Nk-Ed for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:01 -0500 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:33991) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gt05i-00083e-2s for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:08:58 -0500 Received: by mail-pf1-x444.google.com with SMTP id j18so4472061pfe.1 for ; Sun, 10 Feb 2019 17:08:39 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sSJPTVVkjcWARcwigg6wJDNen7ofl5R1qSbWzhReSSs=; b=FQDvJD7X8KF0GRw0sY2830x6AnmWusQUNVX7SS0DYdHC6tlba90hIx11mLgAFhMvpv F0RZkJ9Luj1x1E9dCqsbINcm4jN1roGKKzOfVdWCeWptIZ1KZUrbMk4K9xVpSgOjnj48 jCJYtRM8oc9G9ojvPlVmmblaRTY9vRk0FtzDQwAhCaiNPxmOX8nochL+738utLGi4nc3 JccCPdYA5dlBfF4Lqfl/IdOm0zM9dvDQfPhl3dWO6E3xCoR0FRLHgtI4/fjy07/Z+uwq Saz36uXt6PSXPhWtE7RDkwNSWNuvNLLfIBnFi1rjau/SGersaoyaKEah4osMrULkkxoz NcRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sSJPTVVkjcWARcwigg6wJDNen7ofl5R1qSbWzhReSSs=; b=abhoPvIHmbhDkSRy0WDiZLlL4ZvwyFJPgtadg+IRsbXXzBIQUSu7Asmsa0x8g++4P3 KcibxVgRydGFo1lho/p8O4nq3y0ExB2hqZ73yMiCOoyc1Pi/xrWK8wNHWm+akoctrpJB iZ2Grpwmig3wbxTeLkYBy/QTwuXWF1mJf1JENxCvCWBAxiog1WbQKayJgOTc6Q80MxAq pKnCvzzZunapDR1D4LBlnQxU2b/DWf09fFUoQdlR047XawwfEoA1CFkEfoQpK6lTdbf1 PKkCj5epIHQo1bzcdF4WzbrGxO2b6YzbGFnS5/r1Pu+MEeJ97o1ba1yZrB/Ax6vFi+CI Njrw== X-Gm-Message-State: AHQUAubJ3m+LkklXOgf0LVHFBGMsB3vQA52JkZC5q/nGDHneTOOCRvGs XHsA6hRB9SiU8YF7t+AwJMszavN5EHg= X-Google-Smtp-Source: AHgI3IbL5Rps8NmaIEOATygyIqiHfUaBLJ3RY7bY90GmmtmmWjNJy+wxg32Ez4bAlKlgWei2wU6KFA== X-Received: by 2002:a62:5182:: with SMTP id f124mr24442444pfb.238.1549847318456; Sun, 10 Feb 2019 17:08:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:08 -0800 Message-Id: <20190211010829.29869-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v2 05/26] target/arm: Extract TCMA with ARMVAParameters X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 1 + target/arm/helper.c | 8 ++++++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 6c018e773c..2922324f63 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -959,6 +959,7 @@ typedef struct ARMVAParameters { bool tbid : 1; bool epd : 1; bool hpd : 1; + bool tcma : 1; bool using16k : 1; bool using64k : 1; } ARMVAParameters; diff --git a/target/arm/helper.c b/target/arm/helper.c index e73bdbf041..cbe3500f78 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10447,7 +10447,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState= *env, uint64_t va, { uint64_t tcr =3D regime_tcr(env, mmu_idx)->raw_tcr; uint32_t el =3D regime_el(env, mmu_idx); - bool tbi, tbid, epd, hpd, using16k, using64k; + bool tbi, tbid, epd, hpd, tcma, using16k, using64k; int select, tsz; =20 /* @@ -10462,11 +10462,12 @@ ARMVAParameters aa64_va_parameters_both(CPUARMSta= te *env, uint64_t va, using16k =3D extract32(tcr, 15, 1); if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { /* VTCR_EL2 */ - tbi =3D tbid =3D hpd =3D false; + tbi =3D tbid =3D hpd =3D tcma =3D false; } else { tbi =3D extract32(tcr, 20, 1); hpd =3D extract32(tcr, 24, 1); tbid =3D extract32(tcr, 29, 1); + tcma =3D extract32(tcr, 30, 1); } epd =3D false; } else if (!select) { @@ -10477,6 +10478,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState= *env, uint64_t va, tbi =3D extract64(tcr, 37, 1); hpd =3D extract64(tcr, 41, 1); tbid =3D extract64(tcr, 51, 1); + tcma =3D extract64(tcr, 57, 1); } else { int tg =3D extract32(tcr, 30, 2); using16k =3D tg =3D=3D 1; @@ -10486,6 +10488,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState= *env, uint64_t va, tbi =3D extract64(tcr, 38, 1); hpd =3D extract64(tcr, 42, 1); tbid =3D extract64(tcr, 52, 1); + tcma =3D extract64(tcr, 58, 1); } tsz =3D MIN(tsz, 39); /* TODO: ARMv8.4-TTST */ tsz =3D MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ @@ -10497,6 +10500,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState= *env, uint64_t va, .tbid =3D tbid, .epd =3D epd, .hpd =3D hpd, + .tcma =3D tcma, .using16k =3D using16k, .using64k =3D using64k, }; --=20 2.17.2 From nobody Fri May 3 10:47:40 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549847502150818.5697667432056; Sun, 10 Feb 2019 17:11:42 -0800 (PST) Received: from localhost ([127.0.0.1]:42104 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt08A-0007UY-1I for importer@patchew.org; Sun, 10 Feb 2019 20:11:30 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37211) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt05i-0005eY-3m for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:08:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gt05g-0008Ks-98 for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:08:58 -0500 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:43853) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gt05d-00084f-3B for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:08:55 -0500 Received: by mail-pl1-x644.google.com with SMTP id f90so4270496plb.10 for ; Sun, 10 Feb 2019 17:08:41 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=EkQDtq1xSIGU1XROXRBBDpDZ5vELkcoeXfK8fEl97xA=; b=XGdu+rT5c+sQC5EaiIx2SL8bIfqzBCHpC502b9FR+2GlFrTaCZ4vShU+2Og6FJk2fU V2FjZauGmz0K9gXbe8nC7dJUsYPo/a90gxBCnHBxnMqymY29+TeZ8wrahAAgFN6rFByc FGEALc6IZ73OZ/bLvzMjFCB5IV08Ss3tIc6DZkZWFOp+OUTQLs5DDcZEWskt3exAOie8 V6MflrDSg/GDqyVJebGnYW/iWemYiwIY2DImTVWhax9pt+CxoNvKLBBr9Ge6lujzZi3F PXOKOFUB0lrxYeU56wsSboAX530Ym0RwMOgpUhUU9kmMDFOoXR3/fyV8G6cnVcNh9dn6 ohjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EkQDtq1xSIGU1XROXRBBDpDZ5vELkcoeXfK8fEl97xA=; b=KiRGriGV7OjCwU5KUE7RY+ItGymRdey5Ajzm3s/4ZcptRF326bSjzrJr6QEhxKdV9l pnl69BwHx00PShRESh7pbMgc+xiQTW1rVz4bZDvR046uPxkgJ29ZaNcrVI/XNpFWAHkn +GIORucTRV023IEWhYPhNjULCHnXrLS4DCq/Z4gKegTFHL2mPbsbiPAZ6Lzvfsi15sN9 IDaj1IGn8N5LcoIwY483W2n+tY7VRuOUPcg2eoMpJs9LoWq+9ZDkLdfKsP9B3QQ/Atx2 iAlDoY3qtqkRufmPv9uQXK+2oKzbeVmrFSObPm/HvNtfveWgWZ99iuTxrFdLWNyinuqZ ZXTg== X-Gm-Message-State: AHQUAuav0Bcub6liWNhrXDvAiOSAxnfDfyVjR3KEqJKQ9o+zd3qonFdt 6Qdvm5cCuDO1TqQ6GUuqUqXIpQlKkCk= X-Google-Smtp-Source: AHgI3Ia5Zf4oYm6iRLGFocCxOcz2kE7vFCyBberLmoF3qwonzmSOxgjVz5+BckLPTunNdVkwJcBrBQ== X-Received: by 2002:a17:902:112c:: with SMTP id d41mr33972748pla.144.1549847319697; Sun, 10 Feb 2019 17:08:39 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:09 -0800 Message-Id: <20190211010829.29869-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v2 06/26] target/arm: Add MTE system registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is TFSRE0_EL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, RGSR_EL1, GCR_EL1, and PSTATE.TCO. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 +++++ target/arm/translate.h | 11 ++++++++++ target/arm/helper.c | 45 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 11 ++++++++++ 4 files changed, 72 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2776df6981..74633a7a78 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -495,6 +495,11 @@ typedef struct CPUARMState { uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ uint64_t vpidr_el2; /* Virtualization Processor ID Register */ uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register = */ +#ifdef TARGET_AARCH64 + uint64_t tfsr_el[4]; /* tfsrel0_el1 is index 0. */ + uint64_t gcr_el1; + uint64_t rgsr_el1; +#endif } cp15; =20 struct { diff --git a/target/arm/translate.h b/target/arm/translate.h index 5a101e1c6d..a24757d3d7 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -204,6 +204,17 @@ static inline TCGv_i32 get_ahp_flag(void) return ret; } =20 +/* Set bits within PSTATE. */ +static inline void set_pstate_bits(uint32_t bits) +{ + TCGv_i32 p =3D tcg_temp_new_i32(); + + tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate)); + tcg_gen_ori_i32(p, p, bits); + tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate)); + tcg_temp_free_i32(p); +} + /* Clear bits within PSTATE. */ static inline void clear_pstate_bits(uint32_t bits) { diff --git a/target/arm/helper.c b/target/arm/helper.c index cbe3500f78..2d9c070bb3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5732,6 +5732,48 @@ static const ARMCPRegInfo pauth_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, apib_key.hi) }, REGINFO_SENTINEL }; + +static uint64_t tco_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pstate & PSTATE_TCO; +} + +static void tco_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= al) +{ + env->pstate =3D (env->pstate & ~PSTATE_TCO) | (val & PSTATE_TCO); +} + +static const ARMCPRegInfo mte_reginfo[] =3D { + { .name =3D "TFSRE0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 6, .crm =3D 6, .opc2 =3D 1, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.tfsr_el[0]) }, + { .name =3D "TFSR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 6, .crm =3D 5, .opc2 =3D 0, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.tfsr_el[1]) }, + { .name =3D "TFSR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 6, .crm =3D 5, .opc2 =3D 0, + .access =3D PL2_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.tfsr_el[2]) }, + { .name =3D "TFSR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 6, .crm =3D 6, .opc2 =3D 0, + .access =3D PL3_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.tfsr_el[3]) }, + { .name =3D "RGSR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 5, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.rgsr_el1) }, + { .name =3D "GCR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 6, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.gcr_el1) }, + { .name =3D "TCO", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 4, .crm =3D 2, .opc2 =3D 7, + .type =3D ARM_CP_NO_RAW, + .access =3D PL0_RW, .readfn =3D tco_read, .writefn =3D tco_write }, + REGINFO_SENTINEL +}; #endif =20 void register_cp_regs_for_features(ARMCPU *cpu) @@ -6577,6 +6619,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_pauth, cpu)) { define_arm_cp_regs(cpu, pauth_reginfo); } + if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) { + define_arm_cp_regs(cpu, mte_reginfo); + } #endif } =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e782a0e579..8e9f40f2a6 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1672,6 +1672,17 @@ static void handle_msr_i(DisasContext *s, uint32_t i= nsn, s->base.is_jmp =3D DISAS_UPDATE; break; =20 + case 0x1c: /* TCO */ + if (!dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + if (crm & 1) { + set_pstate_bits(PSTATE_TCO); + } else { + clear_pstate_bits(PSTATE_TCO); + } + break; + default: do_unallocated: unallocated_encoding(s); --=20 2.17.2 From nobody Fri May 3 10:47:40 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MeANllhl1EJDV5sKJLIW0fjvttmmw3UOBcxKU9DzMxw=; b=JzV2yK8u9V9hmkNEC+LMvb/OE/CZhY++ro6NYUgPvcw2kv3oKiWM8Agu4XizJpDor9 cBEaf7HVeKp6iJNmEc+1OmbEuOqUp0ZzO3ykJGiI4gCc1AJJv/qwXQuh1bU/CDTeOukV F6b9BQ84WvnF1ugdRHOQzbMzppLILEYLsfjcukm7AHmbpgkFh0RINKrzjC5duUSA2QCM qTwLGNakTKK0aNETuoEX90ZQo98Ex8P63j5lN7aTX6LG+Vvj/qorOHMZXBC+Luf5Nq6C gtWmSt38tJ3ypJlRTyNsRocg9gtpXeGm/GFiTz5ClMoBv+zp8o9GTyrWpYrQcOoh0uKQ OwMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MeANllhl1EJDV5sKJLIW0fjvttmmw3UOBcxKU9DzMxw=; b=C2kpwLD4AJvA5cbgXLJYtv3oKuV3uYzmOfvW/0npsqpYBE9BZ9JVFrIDtF+vxATGdm 8HoslYhpSscFKqciRv8WCjqFnNqg5p/6IvSHvI3NezVFZ0zc4UK/IHUTTRgACAJ98D3e NEMMwOzu9JNjM33oB+tKqRoZbVPTepckM8+7986r0x6uRPfE1NqePoauSu4N6TNwumds mCcpPshg7YG9RDrAdsxw8Z+KdM4yEXqbSnS5erKYHArEv/i9ogDxso4udQUIGewJ5a1X 4tvWg2hHrAmG0fRN0wyDDjg1BHdEtVVvD77e+hrUmWoEkexfmGotQjNu70O4J3BLTXHA RLXA== X-Gm-Message-State: AHQUAuYUDNptQg8Df9xQJ2BU/hY0+CRiXX7to1DhPz1rhzq8jkObQDNS 1Qhv1WQUOQY7PvFxG4RKGRuNDgyCv/s= X-Google-Smtp-Source: AHgI3IZoNiFnHk0r77I48SrSCiv6giH6xwUw5Fxy5LerizpfQQUHECf1wnVtbSlZfFajORUGRQfU1A== X-Received: by 2002:a17:902:1122:: with SMTP id d31mr34969423pla.246.1549847320949; Sun, 10 Feb 2019 17:08:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:10 -0800 Message-Id: <20190211010829.29869-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::631 Subject: [Qemu-devel] [PATCH v2 07/26] target/arm: Assert no manual change to CACHED_PSTATE_BITS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These bits are stored elsewhere; changing env->pstate has no effect. Suggested-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/arm/translate.h b/target/arm/translate.h index a24757d3d7..296d1ac72c 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -209,6 +209,8 @@ static inline void set_pstate_bits(uint32_t bits) { TCGv_i32 p =3D tcg_temp_new_i32(); =20 + tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); + tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate)); tcg_gen_ori_i32(p, p, bits); tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate)); @@ -220,6 +222,8 @@ static inline void clear_pstate_bits(uint32_t bits) { TCGv_i32 p =3D tcg_temp_new_i32(); =20 + tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); + tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate)); tcg_gen_andi_i32(p, p, ~bits); tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate)); --=20 2.17.2 From nobody Fri May 3 10:47:40 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549848087646317.65459527288544; Sun, 10 Feb 2019 17:21:27 -0800 (PST) Received: from localhost ([127.0.0.1]:42266 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt0Hk-0006n9-Ea for importer@patchew.org; Sun, 10 Feb 2019 20:21:24 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37480) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt05r-0005sa-M9 for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gt05p-0008Vv-TQ for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:07 -0500 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]:36069) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gt05o-00085p-54 for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:05 -0500 Received: by mail-pl1-x635.google.com with SMTP id g9so4514744plo.3 for ; Sun, 10 Feb 2019 17:08:43 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=btPp8hltDkFrd7qKQ50LGQORF7TOq+f4+8xGAfmBZ5M=; b=sJ6MFe1O9QLLEm0oNmM3TWjy7Y4iPUj26h91DwSCp4z74dlfzii4jjdnDkwUlIvKdJ puuyz0A3lYE/ShWtJ2uek0f782rfPe67kvRvfQJzbS2CEusicN86rhVysDyI0p39pdJE wovlj8XBud1Apk/+mEyV1jsaIcPINA2EyPo4D7cTTrk+q/Av8Fyj02/nhE7M7V4+30Km H87wCqrYg68JsrvGzdksCs/57rsAwPBnI/aHF/L18i6LPqhldm9ioY926+gUtrIdngpn KNfFydJXdSHXpUxwUgEMB+lE35VL98Pz7NtTq5ajfT33JopIII+SDm2pHtSGXnOJoUez +LCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=btPp8hltDkFrd7qKQ50LGQORF7TOq+f4+8xGAfmBZ5M=; b=S5QTCECFOTTOWuBZ6jCDCOWz54HdRtRqVjL/0c1VTuJizHggAM6/znpKbSZ/ZIYQHw 9VmsxzrghqmawERzP61Sc+nC0TtaknrURsrAtMhkQu1YOfh3aun/7zN1ShOJJx8zHQSj O/7bSH4MDZhGcsmJa3h0vv5req4y292op8sWqPeLBp6utLQtlBZNfT3wsGsrudkbzyX0 /4Qh60tnaK+QMc+ka7KtO4tUyV/5/OLZX/VIZYo6FKlANrImGh0j7ZCFPXzh0T4clKH3 92eDdm9wOeGQmE6aus4lb/CnEwF6727Cios6ZFQU9iV5WAKUjsAwtsgUqe+gtgO7WpiU 5dkQ== X-Gm-Message-State: AHQUAuZbEFq0EVzz2rfkcZHGdvQ+/uNtgw+xiRa3JnOzoF1vrWUgByRt IEDKHp7k26UxfsVPy88C9BIU75hIWvo= X-Google-Smtp-Source: AHgI3Ib54t+tANc+wKnwbJiG4RZvW0fVmJpyN+WkC7Q5a/m8JYscARLAeZrlYXJB1BzZSqpgkTnVvg== X-Received: by 2002:a17:902:298a:: with SMTP id h10mr35277076plb.312.1549847322224; Sun, 10 Feb 2019 17:08:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:11 -0800 Message-Id: <20190211010829.29869-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::635 Subject: [Qemu-devel] [PATCH v2 08/26] target/arm: Fill in helper_mte_check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implements the rules of "PE generation of Checked and Unchecked accesses" which aren't already implied by TB_FLAGS_MTE_ACTIVE. Implements the rules of "PE handling of Tag Check Failure". Does not implement tag physical address space, so all operations reduce to unchecked so far. Signed-off-by: Richard Henderson --- v2: Fix TFSR update. --- target/arm/mte_helper.c | 94 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 92 insertions(+), 2 deletions(-) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index f1174d6f9f..d086925a91 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -25,6 +25,8 @@ #include "exec/helper-proto.h" =20 =20 +#if 0 +/* Don't break bisect. This will gain another user before we're done. */ static uint64_t strip_tbi(CPUARMState *env, uint64_t ptr) { /* @@ -49,9 +51,97 @@ static uint64_t strip_tbi(CPUARMState *env, uint64_t ptr) return ptr; } } +#endif + +static int get_allocation_tag(CPUARMState *env, uint64_t ptr, uintptr_t ra) +{ + /* Tag storage not implemented. */ + return -1; +} + +static int allocation_tag_from_addr(uint64_t ptr) +{ + ptr +=3D 1ULL << 55; /* carry ptr[55] into ptr[59:56]. */ + return extract64(ptr, 56, 4); +} =20 uint64_t HELPER(mte_check)(CPUARMState *env, uint64_t ptr) { - /* Only unchecked implemented so far. */ - return strip_tbi(env, ptr); + ARMMMUIdx mmu_idx =3D arm_stage1_mmu_idx(env); + ARMVAParameters param =3D aa64_va_parameters(env, ptr, mmu_idx, true); + int el =3D arm_current_el(env); + int ptr_tag, mem_tag; + uintptr_t ra =3D GETPC(); + + /* + * If TBI is disabled, then the access is unchecked. + * While we filtered out TBI0=3D=3D0 && TBI1=3D=3D0 in cpu_get_tb_cpu_= state, + * we did not save separate bits for TBI0 !=3D TBI1. + */ + if (!param.tbi) { + /* Do not ignore the top byte. */ + return ptr; + } + + /* + * If TCMA is enabled, then physical tag 0 is unchecked. + * Note the rules R0076 & R0077 are written with logical tags, + * and we need the physical tag below anyway. + */ + ptr_tag =3D allocation_tag_from_addr(ptr); + if (param.tcma && ptr_tag =3D=3D 0) { + goto pass; + } + + /* + * If an access is made to an address that does not provide tag storag= e, + * the result is implementation defined (R0006). We choose to treat t= he + * access as unchecked. + * This is similar to MemAttr !=3D Tagged, which are also unchecked. + */ + mem_tag =3D get_allocation_tag(env, ptr, ra); + if (mem_tag < 0) { + goto pass; + } + + /* If the tags do not match, the tag check operation fails. */ + if (ptr_tag !=3D mem_tag) { + int tcf; + + if (el =3D=3D 0) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + tcf =3D extract64(env->cp15.sctlr_el[1], 38, 2); + } else { + tcf =3D extract64(env->cp15.sctlr_el[el], 40, 2); + } + if (tcf =3D=3D 1) { + /* + * Tag check fail causes a synchronous exception. + * + * In restore_state_to_opc, we set the exception syndrome + * for the load or store operation. Do that first so we + * may overwrite that with the syndrome for the tag check. + */ + cpu_restore_state(ENV_GET_CPU(env), ra, true); + env->exception.vaddress =3D ptr; + raise_exception(env, EXCP_DATA_ABORT, + syn_data_abort_no_iss(el !=3D 0, 0, 0, 0, 0, 0= x11), + exception_target_el(env)); + } else if (tcf =3D=3D 2) { + /* Tag check fail causes asynchronous flag set. */ + env->cp15.tfsr_el[el] |=3D 1 << param.select; + } + } + + pass: + /* + * Unchecked, tag check pass, or tag check fail does not trap. + * Ignore the top byte. + */ + if (el >=3D 2) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + return extract64(ptr, 0, 56); + } else { + return sextract64(ptr, 0, 56); + } } --=20 2.17.2 From nobody Fri May 3 10:47:40 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549847688911536.5521364482327; Sun, 10 Feb 2019 17:14:48 -0800 (PST) Received: from localhost ([127.0.0.1]:42132 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt0BG-0001bo-MD for importer@patchew.org; Sun, 10 Feb 2019 20:14:42 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37213) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt05i-0005ee-43 for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:08:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gt05g-0008L9-An for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:08:58 -0500 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:40715) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gt05d-00086W-3Q for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:08:56 -0500 Received: by mail-pl1-x644.google.com with SMTP id bj4so1844710plb.7 for ; Sun, 10 Feb 2019 17:08:44 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=EWm2iSaAOLbuCw7Om0ASn9c3AgIfiLyR0Kyc+wT9FkU=; b=lvp2di77SaCF2rO1WxM3Ab50ZSnlL+YNt85x5N2OAnMxt6yZDHlEmu8BR/oLnuja/+ kjMAR8nPTUsS7K1uxU5+nQOl1wHpBjeZYHS4yYphnlLJolCBwTGJc/uwbyYKYdEjFfSt tUynHLBQQWXTSutERZCiQ3S1HI48d1/hg1FbtAM39hungjsoAFPpGHliYBID4LJ/R+6U eObr83lTBdk/j0uZwCqWIHAh+HJnw+Y2BLvtaL75bmggrxnKia6Nkq30n3cjMmYeUjqa 1RmyW71Q7PjhBrkX0MsZ2TIfj8Gvvs7T0kyf/t2CXNUAuqJxjkYZQ/1arU7InlMwM/9/ KGcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EWm2iSaAOLbuCw7Om0ASn9c3AgIfiLyR0Kyc+wT9FkU=; b=oiE8NUI8T0bmIvE7TomPrDwVg12WtyxizaSE+DwcPdvU3sKf+uPiGQ9RNV33jX1r6G mb6lTnAEbpN2ZCnKbVMy1/Ow8hQnyrfzGbVt5SPONAU4HFUjGwWZO56JsHeEyw+y8kr8 WrJrD34V6HGwTpjzl0rElyg1cVae1LOe8a6VueyOLh0IeFs3qCqQEWPsarJ5Gsoaa1jn 5C2nGf29/Uzt7q9+VDR/O2RuTSvNsmFWjkyQ6887T7zm8KWZ7Gsi2D14blZlwt9wpDBD Jae6bxsPXRCRPchaPQa/mxCQaid5uPSb2OTmvmQZN9jrPNzi+V6Xa+3qTT5YcTi1ELIj V1VQ== X-Gm-Message-State: AHQUAubsX36p/siEX4k7tM00rhIU0xmW90DFUXPPSQYb55K/Ea+JNN8q bwnBpiOXX8Xc9mKadB0mGGlYrgfHtZ8= X-Google-Smtp-Source: AHgI3IbU0dS7FJ90vPdQN0+jrkXuuKDIZ0YO+suLw8QPfKuN0zYCuMcf2+ZIWdXV4A/rfyG2BuGloA== X-Received: by 2002:a17:902:7608:: with SMTP id k8mr29077063pll.245.1549847323738; Sun, 10 Feb 2019 17:08:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:12 -0800 Message-Id: <20190211010829.29869-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v2 09/26] target/arm: Suppress tag check for sp+offset X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" R0078 specifies that base register, or base register plus immediate offset, is unchecked when the base register is SP. Signed-off-by: Richard Henderson --- v2: Include writeback addresses as checked. --- target/arm/translate-a64.c | 37 ++++++++++++++++++------------------- 1 file changed, 18 insertions(+), 19 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 8e9f40f2a6..d0f8c314c9 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -340,12 +340,11 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 = src) * This is always a fresh temporary, as we need to be able to * increment this independently of a dirty write-back address. */ -static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) +static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr, bool check) { TCGv_i64 clean =3D new_tmp_a64(s); =20 - /* FIXME: SP+OFS is always unchecked. */ - if (s->tbid && s->mte_active) { + if (check && s->mte_active) { gen_helper_mte_check(clean, cpu_env, addr); } else { gen_top_byte_ignore(s, clean, addr, s->tbid); @@ -2379,7 +2378,7 @@ static void gen_compare_and_swap(DisasContext *s, int= rs, int rt, if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn), rn !=3D 31); tcg_gen_atomic_cmpxchg_i64(tcg_rs, clean_addr, tcg_rs, tcg_rt, memidx, size | MO_ALIGN | s->be_data); } @@ -2397,7 +2396,7 @@ static void gen_compare_and_swap_pair(DisasContext *s= , int rs, int rt, if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn), rn !=3D 31); =20 if (size =3D=3D 2) { TCGv_i64 cmp =3D tcg_temp_new_i64(); @@ -2522,7 +2521,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } - clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn), rn !=3D 31); gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, false); return; =20 @@ -2531,7 +2530,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn), rn !=3D 31); s->is_ldex =3D true; gen_load_exclusive(s, rt, rt2, clean_addr, size, false); if (is_lasr) { @@ -2551,7 +2550,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) gen_check_sp_alignment(s); } tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn), rn !=3D 31); do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); return; @@ -2567,7 +2566,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn), rn !=3D 31); do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, true,= rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); @@ -2581,7 +2580,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } - clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn), rn !=3D 31= ); gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, true); return; } @@ -2599,7 +2598,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn), rn !=3D 31= ); s->is_ldex =3D true; gen_load_exclusive(s, rt, rt2, clean_addr, size, true); if (is_lasr) { @@ -2789,7 +2788,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t= insn) if (!postindex) { tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); } - clean_addr =3D clean_data_tbi(s, dirty_addr); + clean_addr =3D clean_data_tbi(s, dirty_addr, wback || rn !=3D 31); =20 if (is_vector) { if (is_load) { @@ -2927,7 +2926,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, if (!post_index) { tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); } - clean_addr =3D clean_data_tbi(s, dirty_addr); + clean_addr =3D clean_data_tbi(s, dirty_addr, writeback || rn !=3D 31); =20 if (is_vector) { if (is_store) { @@ -3034,7 +3033,7 @@ static void disas_ldst_reg_roffset(DisasContext *s, u= int32_t insn, ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0); =20 tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm); - clean_addr =3D clean_data_tbi(s, dirty_addr); + clean_addr =3D clean_data_tbi(s, dirty_addr, true); =20 if (is_vector) { if (is_store) { @@ -3119,7 +3118,7 @@ static void disas_ldst_reg_unsigned_imm(DisasContext = *s, uint32_t insn, dirty_addr =3D read_cpu_reg_sp(s, rn, 1); offset =3D imm12 << size; tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); - clean_addr =3D clean_data_tbi(s, dirty_addr); + clean_addr =3D clean_data_tbi(s, dirty_addr, rn !=3D 31); =20 if (is_vector) { if (is_store) { @@ -3203,7 +3202,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32= _t insn, if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn), rn !=3D 31); tcg_rs =3D read_cpu_reg(s, rs, true); =20 if (o3_opc =3D=3D 1) { /* LDCLR */ @@ -3265,7 +3264,7 @@ static void disas_ldst_pac(DisasContext *s, uint32_t = insn, tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); =20 /* Note that "clean" and "dirty" here refer to TBI not PAC. */ - clean_addr =3D clean_data_tbi(s, dirty_addr); + clean_addr =3D clean_data_tbi(s, dirty_addr, is_wback || rn !=3D 31); =20 tcg_rt =3D cpu_reg(s, rt); do_gpr_ld(s, tcg_rt, clean_addr, size, /* is_signed */ false, @@ -3425,7 +3424,7 @@ static void disas_ldst_multiple_struct(DisasContext *= s, uint32_t insn) elements =3D (is_q ? 16 : 8) / ebytes; =20 tcg_rn =3D cpu_reg_sp(s, rn); - clean_addr =3D clean_data_tbi(s, tcg_rn); + clean_addr =3D clean_data_tbi(s, tcg_rn, is_postidx || rn !=3D 31); tcg_ebytes =3D tcg_const_i64(ebytes); =20 for (r =3D 0; r < rpt; r++) { @@ -3568,7 +3567,7 @@ static void disas_ldst_single_struct(DisasContext *s,= uint32_t insn) } =20 tcg_rn =3D cpu_reg_sp(s, rn); - clean_addr =3D clean_data_tbi(s, tcg_rn); + clean_addr =3D clean_data_tbi(s, tcg_rn, is_postidx || rn !=3D 31); tcg_ebytes =3D tcg_const_i64(ebytes); =20 for (xs =3D 0; xs < selem; xs++) { --=20 2.17.2 From nobody Fri May 3 10:47:40 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549848212572757.9939312792652; Sun, 10 Feb 2019 17:23:32 -0800 (PST) Received: from localhost ([127.0.0.1]:42286 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt0Jg-0008DO-HG for importer@patchew.org; Sun, 10 Feb 2019 20:23:24 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37308) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt05l-0005ig-5K for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gt05i-0008N3-7G for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:08:59 -0500 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:43589) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gt05g-00089B-Ck for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:08:58 -0500 Received: by mail-pg1-x541.google.com with SMTP id v28so4197911pgk.10 for ; Sun, 10 Feb 2019 17:08:46 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3Dd817zt1y/TGuEmTtxVfosE+MfIs8+VAHxl36iblpQ=; b=TwELF4AmRVVHwOXmRY8bPlGw/WabjF2SjIxw2wIfBnVJa8CUU3nRZuN7ibMngRRMWb f2VTZstIUS96YDaR6Z2+7HAEuaFh8rwYqk2LUx6Y+POXz4wVyFUBMZRypkXg8EOQKfro zP+BDDxUGEwnHQd07U3Xu/CJwkn4hoI6a5enunXWLTYdW35MZOXZea6umpDcNnO0QuPe On+ezL63ZFeeEtf7KE52ZyxU3nmhvFPzWuq7cv5MbksgLoRFwS7iQrCz/gLAv3MEJCQZ hXPVtdiH5h9VIbE2tpSSh8wsGHQ09zyP9xeW0e9eUvmUapgZwfc93Rpgyg8QD4vaTm31 TFLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3Dd817zt1y/TGuEmTtxVfosE+MfIs8+VAHxl36iblpQ=; b=WovQDVQ66J0CjwQO8bwLql8F66DdZFTKCywL5ULyyV4yweo+jbTWO2Cq8jXUsYI98y 7qtmr192kwPkQ97We7ntKXoxfKynzymU+8Kp6SuZR/6Uf1e0qwF/LV/myD5plF1L11FK O+94XD9tG3BsXAxW08kPwuOXMX8r62XAg0p0XbLpZyIeNFBa3YRNz+zVSgghZkG/4CcQ Aq6QuzGqdJlol7x/c84epvmIaiqcWT/V8HSJTG7hziLLdgVs01/5Jt8YhbLDvwQpAEhK iatsZyWbDUxeXm/agzdd+AXj0VM1rKrcMjZJiepLhRGiZXkbnyv7M3aTaPpr6uipF9zL IN9g== X-Gm-Message-State: AHQUAubEyG2kvlK1ftq8ZJm+fzUoeMWuNtYpH++lCDnwhjLNu4+9yS8v qFPGuh/ON88PQNg2NZVUkGsjjTu6i6Y= X-Google-Smtp-Source: AHgI3IY3/GqVbulm+3X4q4hFgadBbEo+VGcLddiR9qsmbNe9q+ONfmunePl5sFK1bc7BySPTcBzYlg== X-Received: by 2002:a62:e201:: with SMTP id a1mr33670343pfi.75.1549847324960; Sun, 10 Feb 2019 17:08:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:13 -0800 Message-Id: <20190211010829.29869-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v2 10/26] target/arm: Implement the IRG instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- v2: Update to 00eac5. Merge choose_random_nonexcluded_tag into helper_irg since that pseudo function no longer exists separately. --- target/arm/helper-a64.h | 1 + target/arm/mte_helper.c | 57 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 7 +++++ 3 files changed, 65 insertions(+) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index fa4c371a47..7a6051fdab 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -104,3 +104,4 @@ DEF_HELPER_FLAGS_2(xpaci, TCG_CALL_NO_RWG_SE, i64, env,= i64) DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) =20 DEF_HELPER_FLAGS_2(mte_check, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index d086925a91..493c2f7bb2 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -65,6 +65,31 @@ static int allocation_tag_from_addr(uint64_t ptr) return extract64(ptr, 56, 4); } =20 +static int choose_nonexcluded_tag(int tag, int offset, uint16_t exclude) +{ + if (exclude =3D=3D 0xffff) { + return 0; + } + if (offset =3D=3D 0) { + while (exclude & (1 << tag)) { + tag =3D (tag + 1) & 15; + } + } else { + do { + do { + tag =3D (tag + 1) & 15; + } while (exclude & (1 << tag)); + } while (--offset > 0); + } + return tag; +} + +static uint64_t address_with_allocation_tag(uint64_t ptr, int rtag) +{ + rtag -=3D extract64(ptr, 55, 1); + return deposit64(ptr, 56, 4, rtag); +} + uint64_t HELPER(mte_check)(CPUARMState *env, uint64_t ptr) { ARMMMUIdx mmu_idx =3D arm_stage1_mmu_idx(env); @@ -145,3 +170,35 @@ uint64_t HELPER(mte_check)(CPUARMState *env, uint64_t = ptr) return sextract64(ptr, 0, 56); } } + +uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm) +{ + int el =3D arm_current_el(env); + uint64_t sctlr =3D arm_sctlr(env, el); + int rtag =3D 0; + + if (allocation_tag_access_enabled(env, el, sctlr)) { + /* + * Our IMPDEF choice for GCR_EL1.RRND=3D=3D1 is to behave as if + * GCR_EL1.RRND=3D=3D0, always producing deterministic results. + */ + uint16_t exclude =3D extract32(rm | env->cp15.gcr_el1, 0, 16); + int start =3D extract32(env->cp15.rgsr_el1, 0, 4); + int seed =3D extract32(env->cp15.rgsr_el1, 8, 16); + int offset, i; + + /* RandomTag */ + for (i =3D offset =3D 0; i < 4; ++i) { + /* NextRandomTagBit */ + int top =3D (extract32(seed, 5, 1) ^ extract32(seed, 3, 1) ^ + extract32(seed, 2, 1) ^ extract32(seed, 0, 1)); + seed =3D (top << 15) | (seed >> 1); + offset |=3D top << i; + } + rtag =3D choose_nonexcluded_tag(start, offset, exclude); + + env->cp15.rgsr_el1 =3D rtag | (seed << 8); + } + + return address_with_allocation_tag(rn, rtag); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d0f8c314c9..5e7d7f2d5e 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5126,6 +5126,13 @@ static void disas_data_proc_2src(DisasContext *s, ui= nt32_t insn) case 3: /* SDIV */ handle_div(s, true, sf, rm, rn, rd); break; + case 4: /* IRG */ + if (sf =3D=3D 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + gen_helper_irg(cpu_reg_sp(s, rd), cpu_env, + cpu_reg_sp(s, rn), cpu_reg(s, rm)); + break; case 8: /* LSLV */ handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd); break; --=20 2.17.2 From nobody Fri May 3 10:47:40 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 154984835916674.84880288607496; Sun, 10 Feb 2019 17:25:59 -0800 (PST) Received: from localhost ([127.0.0.1]:42344 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt0M8-0001jq-32 for importer@patchew.org; Sun, 10 Feb 2019 20:25:56 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37304) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt05l-0005ic-5H for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gt05i-0008NB-9D for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:08:59 -0500 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:34397) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gt05g-0008Ao-FU for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:08:58 -0500 Received: by mail-pg1-x533.google.com with SMTP id d9so4216483pgl.1 for ; Sun, 10 Feb 2019 17:08:47 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pzLCNeCqKG16DdlKX6doEukj/XDWLvUBLDoMwO5fXQ0=; b=pFkFUD6PrbUaGsI+cecPKBdbsvm3GqCyIUau853t8sF2CzcURgoQ55mE1IWUF35FOO Z8O42LGsuHjz1SgA5/qjIR1t3UD9pBOriP1HG6dhx23+Gg4//1H9k14wWQ3o5yVDH9KY duv1TFAGb0gBmqNPVcAL12Lh3+MDsBk5oM+RZItDozm19kujfdWKy12cwkh+wUeLqqjH CQSct8GX8Aql8Mv8RF8SupQQnUYIzdVF7eCNWBji+msAbUAPrxWVUNSYj5RPqGo0AzmL hBTxZepXNjpBnswx4SVQwG/BYgsONoH/V/yi1VFANnw/g3JZj9knGNSJV0TgiqCAcqfi VhfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pzLCNeCqKG16DdlKX6doEukj/XDWLvUBLDoMwO5fXQ0=; b=UH/58wysWuPB4OBkwwSG0/LFgeKSyDS1P4OTOXpfj4JuQ+bpj2y2HJ8tO85wiu+miG ECHY/qJEqdkSWhWEbLH7/QGykqgs7SqVRDR/I/TGlM2NDlJJVLevzpWUC5zPbp5t6iqV HLYbA7u0x4W1EHn6G5KaRh3bwMinwIYXmaacBgjt742hg+YvUgEJBAoAxxQdlafNPdWA sJxT7pVrgb6CpBc4oXpqn0ejw/kWSWEQinmRSJGfMJvScOJZ9WuMdmb1mKR6Fcp9prqp VaejNSRLGODE6ubRmMkQZOSaPy+ZY5iF7UthayKFtdBtPkpfvYjPVsWyTO4eB/BJT0TX Qa5w== X-Gm-Message-State: AHQUAuaB/mbwhRPRKc5Ib8adwvMX5Fh9pyf/Sy04CODFq/HWG+Vdli92 d1h4QpQLdIyGs4x/zsUXGI+YvOP7ke8= X-Google-Smtp-Source: AHgI3IYiwGRrUhtqgZw5GtIquwmqtNxbucHHi+PeGbgnJBxc+k5pChHB7D1iSDbMz/Ku06DHYaHAbg== X-Received: by 2002:a63:ab0b:: with SMTP id p11mr32074688pgf.264.1549847326558; Sun, 10 Feb 2019 17:08:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:14 -0800 Message-Id: <20190211010829.29869-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::533 Subject: [Qemu-devel] [PATCH v2 11/26] target/arm: Implement ADDG, SUBG instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Shift offset in translate; use extract32. --- target/arm/helper-a64.h | 2 ++ target/arm/internals.h | 3 ++ target/arm/mte_helper.c | 32 +++++++++++++++++ target/arm/translate-a64.c | 71 ++++++++++++++++++++++++++------------ 4 files changed, 85 insertions(+), 23 deletions(-) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 7a6051fdab..47577207b2 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -105,3 +105,5 @@ DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env,= i64) =20 DEF_HELPER_FLAGS_2(mte_check, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_4(addg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) +DEF_HELPER_FLAGS_4(subg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) diff --git a/target/arm/internals.h b/target/arm/internals.h index 2922324f63..a5a249b001 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1002,4 +1002,7 @@ static inline bool allocation_tag_access_enabled(CPUA= RMState *env, int el, return sctlr !=3D 0; } =20 +/* We associate one allocation tag per 16 bytes, the minimum. */ +#define LOG2_TAG_GRANULE 4 + #endif diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 493c2f7bb2..3eb5d622fc 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -202,3 +202,35 @@ uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, ui= nt64_t rm) =20 return address_with_allocation_tag(rn, rtag); } + +uint64_t HELPER(addg)(CPUARMState *env, uint64_t ptr, + uint32_t offset, uint32_t tag_offset) +{ + int el =3D arm_current_el(env); + uint64_t sctlr =3D arm_sctlr(env, el); + int rtag =3D 0; + + if (allocation_tag_access_enabled(env, el, sctlr)) { + int start_tag =3D allocation_tag_from_addr(ptr); + uint16_t exclude =3D extract32(env->cp15.gcr_el1, 0, 16); + rtag =3D choose_nonexcluded_tag(start_tag, tag_offset, exclude); + } + + return address_with_allocation_tag(ptr + offset, rtag); +} + +uint64_t HELPER(subg)(CPUARMState *env, uint64_t ptr, + uint32_t offset, uint32_t tag_offset) +{ + int el =3D arm_current_el(env); + uint64_t sctlr =3D arm_sctlr(env, el); + int rtag =3D 0; + + if (allocation_tag_access_enabled(env, el, sctlr)) { + int start_tag =3D allocation_tag_from_addr(ptr); + uint16_t exclude =3D extract32(env->cp15.gcr_el1, 0, 16); + rtag =3D choose_nonexcluded_tag(start_tag, tag_offset, exclude); + } + + return address_with_allocation_tag(ptr - offset, rtag); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 5e7d7f2d5e..3d71a9701f 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3672,7 +3672,9 @@ static void disas_pc_rel_adr(DisasContext *s, uint32_= t insn) * sf: 0 -> 32bit, 1 -> 64bit * op: 0 -> add , 1 -> sub * S: 1 -> set flags - * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12 + * shift: 00 -> LSL imm by 0, + * 01 -> LSL imm by 12 + * 10 -> ADDG, SUBG */ static void disas_add_sub_imm(DisasContext *s, uint32_t insn) { @@ -3683,10 +3685,10 @@ static void disas_add_sub_imm(DisasContext *s, uint= 32_t insn) bool setflags =3D extract32(insn, 29, 1); bool sub_op =3D extract32(insn, 30, 1); bool is_64bit =3D extract32(insn, 31, 1); + bool is_tag =3D false; =20 TCGv_i64 tcg_rn =3D cpu_reg_sp(s, rn); TCGv_i64 tcg_rd =3D setflags ? cpu_reg(s, rd) : cpu_reg_sp(s, rd); - TCGv_i64 tcg_result; =20 switch (shift) { case 0x0: @@ -3694,35 +3696,58 @@ static void disas_add_sub_imm(DisasContext *s, uint= 32_t insn) case 0x1: imm <<=3D 12; break; + case 0x2: + /* ADDG, SUBG */ + if (!is_64bit || setflags || (imm & 0x30) || + !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + is_tag =3D true; + break; default: + do_unallocated: unallocated_encoding(s); return; } =20 - tcg_result =3D tcg_temp_new_i64(); - if (!setflags) { - if (sub_op) { - tcg_gen_subi_i64(tcg_result, tcg_rn, imm); - } else { - tcg_gen_addi_i64(tcg_result, tcg_rn, imm); - } - } else { - TCGv_i64 tcg_imm =3D tcg_const_i64(imm); - if (sub_op) { - gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); - } else { - gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); - } - tcg_temp_free_i64(tcg_imm); - } + if (is_tag) { + TCGv_i32 tag_offset =3D tcg_const_i32(imm & 15); + TCGv_i32 offset =3D tcg_const_i32((imm >> 6) << LOG2_TAG_GRANULE); =20 - if (is_64bit) { - tcg_gen_mov_i64(tcg_rd, tcg_result); + if (sub_op) { + gen_helper_subg(tcg_rd, cpu_env, tcg_rn, offset, tag_offset); + } else { + gen_helper_addg(tcg_rd, cpu_env, tcg_rn, offset, tag_offset); + } + tcg_temp_free_i32(tag_offset); + tcg_temp_free_i32(offset); } else { - tcg_gen_ext32u_i64(tcg_rd, tcg_result); - } + TCGv_i64 tcg_result; =20 - tcg_temp_free_i64(tcg_result); + if (!setflags) { + tcg_result =3D tcg_rd; + if (sub_op) { + tcg_gen_subi_i64(tcg_result, tcg_rn, imm); + } else { + tcg_gen_addi_i64(tcg_result, tcg_rn, imm); + } + } else { + TCGv_i64 tcg_imm =3D tcg_const_i64(imm); + tcg_result =3D new_tmp_a64(s); + if (sub_op) { + gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); + } else { + gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); + } + tcg_temp_free_i64(tcg_imm); + } + + if (is_64bit) { + tcg_gen_mov_i64(tcg_rd, tcg_result); + } else { + tcg_gen_ext32u_i64(tcg_rd, tcg_result); + } + } } =20 /* The input should be a value in the bottom e bits (with higher --=20 2.17.2 From nobody Fri May 3 10:47:40 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549848533732767.818763422898; Sun, 10 Feb 2019 17:28:53 -0800 (PST) Received: from localhost ([127.0.0.1]:42372 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt0Oq-0003zb-L6 for importer@patchew.org; Sun, 10 Feb 2019 20:28:44 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37482) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt05r-0005se-MU for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gt05q-00005H-Lx for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:07 -0500 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:38625) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gt05p-0008E1-QP for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:06 -0500 Received: by mail-pl1-x641.google.com with SMTP id e5so4510630plb.5 for ; Sun, 10 Feb 2019 17:08:48 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v2 12/26] target/arm: Implement the GMI instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-a64.h | 1 + target/arm/mte_helper.c | 6 ++++++ target/arm/translate-a64.c | 6 ++++++ 3 files changed, 13 insertions(+) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 47577207b2..ef340cb6f9 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -107,3 +107,4 @@ DEF_HELPER_FLAGS_2(mte_check, TCG_CALL_NO_WG, i64, env,= i64) DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_4(addg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) DEF_HELPER_FLAGS_4(subg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) +DEF_HELPER_FLAGS_2(gmi, TCG_CALL_NO_RWG_SE, i64, i64, i64) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 3eb5d622fc..fc9e172c95 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -234,3 +234,9 @@ uint64_t HELPER(subg)(CPUARMState *env, uint64_t ptr, =20 return address_with_allocation_tag(ptr - offset, rtag); } + +uint64_t HELPER(gmi)(uint64_t ptr, uint64_t mask) +{ + int tag =3D allocation_tag_from_addr(ptr); + return mask | (1ULL << tag); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 3d71a9701f..2e0d797294 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5158,6 +5158,12 @@ static void disas_data_proc_2src(DisasContext *s, ui= nt32_t insn) gen_helper_irg(cpu_reg_sp(s, rd), cpu_env, cpu_reg_sp(s, rn), cpu_reg(s, rm)); break; + case 5: /* GMI */ + if (sf =3D=3D 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + gen_helper_gmi(cpu_reg(s, rd), cpu_reg_sp(s, rn), cpu_reg(s, rm)); + break; case 8: /* LSLV */ handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd); break; --=20 2.17.2 From nobody Fri May 3 10:47:40 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549848008216207.57596150491952; Sun, 10 Feb 2019 17:20:08 -0800 (PST) Received: from localhost ([127.0.0.1]:42225 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt0GT-0005dL-59 for importer@patchew.org; Sun, 10 Feb 2019 20:20:05 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37307) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt05l-0005ie-5M for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gt05i-0008Np-G5 for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:08:59 -0500 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]:44318) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gt05i-0008Em-2E for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:08:58 -0500 Received: by mail-pl1-x62a.google.com with SMTP id p4so4492102plq.11 for ; Sun, 10 Feb 2019 17:08:50 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PJAqbiDKYxYxOSUmg7S9N0tHoZ0pCVJBOmi1qgJP2Co=; b=lofp4ue2VWOtrXmgafqy5UhMs5IUAsUzs24ekVb5xrimAeSAz9V9es4dtwpzeT1Uzx 7fdeM3iyhnGr2qsdAuv53nYdLUGWmnINHHGAoP9OxjWxpfr3FUeTP91Ub+Fk04apyJ/9 W75e3qoULTbuGRaUxpkAZGAt/yVCIB2AeWvN6fEizbCECYbJSlxLEEuCseAic8O44Hca d4UHMIJKm5I4QQTnB4IrjPEMkBeHsieAwouhhdy8HyDU5W4HxtBJdsB5XP7ZGvJFHLRF 1spVW7dIwKxEw0e/8knN0jGhwtK5Yv1UrktFekgLnmH0eWbPfC1xPYgHSlf3xdEGplum y/DQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PJAqbiDKYxYxOSUmg7S9N0tHoZ0pCVJBOmi1qgJP2Co=; b=bxEQpa/i7FPPc8qOBkMXeoZ2c/9n4scUCODP+taDSxWMS6KlS2dzPOKFb8RoPFScyA PU1S1eN2qrpAfWDMLhLHs77JAGqykCiY76HwqtnbcXsKA+raideDULpWQYODvm8EKKt1 3qNZS15opy5oz/abSOjPuL9fqjDpsW6Z5wJf18ZeD2dz49rn4GeK3+GbSUB4DjQBGVKk jO2xtc5tj/IsFyV4jr9WEFa289pKhoLsF1Gc9MmgXs8yCv20cf1llVLV/UD/t7xJnk8M JF+LktD+xKhi9NgVRogYE7QxdBj5uf/HkcoI/y7CMxnlkQYj8S+iyAItL0LDiEWWmwG+ GZdg== X-Gm-Message-State: AHQUAubdb6srcAC6AA6oUM0+E9j7IjTXwJLJ/rTQJc+SDB5dzOo9iAsE AKHTpcbshJed7aauCXW2DiiSFrhHRJ0= X-Google-Smtp-Source: AHgI3IYJpMPy8RtzoitaG8vuaBpo1VIB/WnbYEQBJB8NMd0pExTX2AFr6evT/ZFkIMdwvhOi1Huqyg== X-Received: by 2002:a17:902:aa07:: with SMTP id be7mr34837830plb.63.1549847329012; Sun, 10 Feb 2019 17:08:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:16 -0800 Message-Id: <20190211010829.29869-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62a Subject: [Qemu-devel] [PATCH v2 13/26] target/arm: Implement the SUBP instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Fix extraction length. --- target/arm/translate-a64.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2e0d797294..3e46ee6f69 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5132,19 +5132,39 @@ static void handle_crc32(DisasContext *s, */ static void disas_data_proc_2src(DisasContext *s, uint32_t insn) { - unsigned int sf, rm, opcode, rn, rd; + unsigned int sf, rm, opcode, rn, rd, setflag; sf =3D extract32(insn, 31, 1); + setflag =3D extract32(insn, 29, 1); rm =3D extract32(insn, 16, 5); opcode =3D extract32(insn, 10, 6); rn =3D extract32(insn, 5, 5); rd =3D extract32(insn, 0, 5); =20 - if (extract32(insn, 29, 1)) { + if (setflag && opcode !=3D 0) { unallocated_encoding(s); return; } =20 switch (opcode) { + case 0: /* SUBP(S) */ + if (sf =3D=3D 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } else { + TCGv_i64 tcg_n, tcg_m, tcg_d; + + tcg_n =3D read_cpu_reg_sp(s, rn, true); + tcg_m =3D read_cpu_reg_sp(s, rm, true); + tcg_gen_sextract_i64(tcg_n, tcg_n, 0, 56); + tcg_gen_sextract_i64(tcg_m, tcg_m, 0, 56); + tcg_d =3D cpu_reg(s, rd); + + if (setflag) { + gen_sub_CC(true, tcg_d, tcg_n, tcg_m); + } else { + tcg_gen_sub_i64(tcg_d, tcg_n, tcg_m); + } + } + break; case 2: /* UDIV */ handle_div(s, false, sf, rm, rn, rd); break; --=20 2.17.2 From nobody Fri May 3 10:47:40 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 154984764414941.14851628493602; Sun, 10 Feb 2019 17:14:04 -0800 (PST) Received: from localhost ([127.0.0.1]:42130 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt0Ab-00012y-43 for importer@patchew.org; Sun, 10 Feb 2019 20:14:01 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37306) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt05l-0005id-5J for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gt05i-0008OE-Kq for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:08:59 -0500 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:34269) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gt05i-0008FU-Bp for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:08:58 -0500 Received: by mail-pl1-x642.google.com with SMTP id w4so4525589plz.1 for ; Sun, 10 Feb 2019 17:08:51 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AmqIDdbNf59JA1t3/NmXQ2mwEInbv+gIdpyKJXCMyoQ=; b=B1QiOMZnSPrk9MyjosQyjsyNuen03qqhyAoKV/xGBtTRGiG04TVGbjQU65p4ENWKVl Y6SF2Jr0MCr3fzQJx7+F0A3PpKwNafSodW/cpznDd6YrhihqWXvejNr98oIXWO7+Ri9T I+zZv0sLYtOA6bsknsWCvdcRHKsKLkGzCxztJRzhzKThxBa8Z1z4SK0Kpu8HdaR6lVn/ cfYi4BvROGkx8q+ptlmzGUi15Y85iZAn45BpYy8X1rpp8VQp7D84IoRhGHbdeXfwhRyw 7fu+UJP4qCZY/0DeCUPwp12CYf/DjnEqQCbSGLSe2F6Nlwb7NMw8jSIV25oR6D98YeuS vvjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AmqIDdbNf59JA1t3/NmXQ2mwEInbv+gIdpyKJXCMyoQ=; b=p0ySa3TbyV3VwD87LYY0B5+tRJ2AVqclQu8ZU15V0ozeEhvMGeATK5EYUhaV4VKL0V bP15QPeliW6hF2rqfOJRieHmGnGS7Ce5POE52KzNsrigYjayqs5YAH05cCXL3+dwCaV+ vGehoXhU7CmX9jMi8smCb2FdHBmnT1NRwAZif8BducV/DglUSfoFXuBhWTRoA42I9Bd8 siKzVgFT+9WOxUGZWoC8k1I/lTqdbBmnMX3ZR1ny/p5FgT9YcBwgOeZmXK41dZxAUu/W YOVRFgt2lURJDOvid8VK4Ga1DX7moq/fTh7HWyDlSefNdVk+5IROVVUWp9ZfCsmqfrN9 fXkw== X-Gm-Message-State: AHQUAuYeUgVMV3j1F8cIoMkSLXTPJVKO5PkIuOYk1YIfxhQD9n/KukDS z9xByM2KpvAyimU9q8YcnF/U9Bp5Ms4= X-Google-Smtp-Source: AHgI3IasxpHqTAeTvetzpdCFztkEjLYIvp65fS5QebC/bcYAN+cd4soy5NEyflrGhmvtmBLrXMbGnQ== X-Received: by 2002:a17:902:2bc9:: with SMTP id l67mr666069plb.241.1549847330237; Sun, 10 Feb 2019 17:08:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:17 -0800 Message-Id: <20190211010829.29869-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v2 14/26] target/arm: Define arm_cpu_do_unaligned_access for CONFIG_USER_ONLY X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We will need this to raise unaligned exceptions from user mode. Signed-off-by: Richard Henderson --- target/arm/op_helper.c | 33 ++++++++++++++++----------------- 1 file changed, 16 insertions(+), 17 deletions(-) diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 8698b4dc83..d3cf362e4b 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -87,8 +87,6 @@ uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, vo= id *vn, return val; } =20 -#if !defined(CONFIG_USER_ONLY) - static inline uint32_t merge_syn_data_abort(uint32_t template_syn, unsigned int target_el, bool same_el, bool ea, @@ -179,6 +177,22 @@ static void deliver_fault(ARMCPU *cpu, vaddr addr, MMU= AccessType access_type, raise_exception(env, exc, syn, target_el); } =20 +/* Raise a data fault alignment exception for the specified virtual addres= s */ +void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + ARMMMUFaultInfo fi =3D {}; + + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr, true); + + fi.type =3D ARMFault_Alignment; + deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); +} + +#ifndef CONFIG_USER_ONLY /* try to fill the TLB and return an exception if error. If retaddr is * NULL, it means that the function was called in C code (i.e. not * from generated code or from helper.c) @@ -200,21 +214,6 @@ void tlb_fill(CPUState *cs, target_ulong addr, int siz= e, } } =20 -/* Raise a data fault alignment exception for the specified virtual addres= s */ -void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - ARMMMUFaultInfo fi =3D {}; - - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr, true); - - fi.type =3D ARMFault_Alignment; - deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); -} - /* arm_cpu_do_transaction_failed: handle a memory system error response * (eg "no device/memory present at address") by raising an external abort * exception --=20 2.17.2 From nobody Fri May 3 10:47:40 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549848620170438.5488305709529; Sun, 10 Feb 2019 17:30:20 -0800 (PST) Received: from localhost ([127.0.0.1]:42392 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt0QL-0005IN-3s for importer@patchew.org; Sun, 10 Feb 2019 20:30:17 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37772) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt05z-00061P-Mm for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gt05t-0000AU-2j for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:15 -0500 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:46861) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gt05s-0008Gi-Ay for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:08 -0500 Received: by mail-pl1-x642.google.com with SMTP id o6so4487431pls.13 for ; Sun, 10 Feb 2019 17:08:52 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dC5MZGfEehm1QYmsC6MCd0iZ0BCsKh0q/AMqCYY4vLc=; b=vAH1BOLHx+z97wMwFUAdNTT6yDT7hdhi5MjSIRvaF2w+XMq71keITZMXoouyTo2ZHI pTTVZSGj72fbRHKunbixonT2f4dY2dimHnj4gzVuhYe5CkmFHPWW/sKXzrH9itsL9oYB 9bVuZoYj/yjE600YbrtNqDDmeQBrBz4n/rc2vNktmXT2yTYIa6OA7NxRJCvycefZuNjL reKKhHunLDiCUqsNBgtYen1KN4nauQ8c2OkW3nj5gWqa2CQfnpXUqTTfwwoo5piav5y6 EHpOFIP9Ij+cScHEbyZ/9JCfjwtjq9W5iiiwhnUU3ln+kysEFIxbQOVNgwKrLTpxx2kn 3M0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dC5MZGfEehm1QYmsC6MCd0iZ0BCsKh0q/AMqCYY4vLc=; b=bxNMgyyuNz52z8iq82G5x0JtlW7Pduu0KakG87PX2Hb9Jo8DP+9c8AZf081sUF63Oe akkldrWrAuvLDD0qD9GVmgleeXSezXH1C9bFHBAbS+ylUkpFabGWazm0l0764mUSTk5s 7NaCz+nNopZQXdHGBdiNANe3tRPPSDXHrCl3eot6/6NbDK9W9whFc0sZZs2RkdkqZWaH RPZYa0o3X4U6hEJv7/N/wHnrvt5hcGJDEJM+pc5NZVyJ4SJ77tRgZMCLri2lwFuETKJ+ RJgObmA76ojYhzB/dxgAIAbNOH2gE6RKhkR7GLzEQFIERMcgFVkVfvp+jBqIIttc8jA5 a1sw== X-Gm-Message-State: AHQUAuYsgpinzj4S5xvO+YJuo5ETRj3g187aRtyDDofarQeyLmtwP+4y lwpggXla3SblEoEl1GzGbs7mJ3icink= X-Google-Smtp-Source: AHgI3IY/eN4cOEVNsZWM8FpZN/TmWDtp4FfuH87LEx1s9hFe9qaUgIj9v1Ax3FZnCNLu1qu0b2sw8Q== X-Received: by 2002:a17:902:7889:: with SMTP id q9mr27910824pll.134.1549847331485; Sun, 10 Feb 2019 17:08:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:18 -0800 Message-Id: <20190211010829.29869-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v2 15/26] target/arm: Implement LDG, STG, ST2G instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- v2: Split out allocation_tag_mem. Handle atomicity of stores. --- target/arm/helper-a64.h | 5 ++ target/arm/mte_helper.c | 152 ++++++++++++++++++++++++++++++++++++- target/arm/translate-a64.c | 114 ++++++++++++++++++++++++++++ 3 files changed, 268 insertions(+), 3 deletions(-) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index ef340cb6f9..a00364fb4c 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -108,3 +108,8 @@ DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64,= i64) DEF_HELPER_FLAGS_4(addg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) DEF_HELPER_FLAGS_4(subg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) DEF_HELPER_FLAGS_2(gmi, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(ldg, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_2(stg, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_2(st2g, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_2(stg_parallel, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_2(st2g_parallel, TCG_CALL_NO_WG, i64, env, i64) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index fc9e172c95..13befdbf86 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -25,8 +25,6 @@ #include "exec/helper-proto.h" =20 =20 -#if 0 -/* Don't break bisect. This will gain another user before we're done. */ static uint64_t strip_tbi(CPUARMState *env, uint64_t ptr) { /* @@ -51,10 +49,22 @@ static uint64_t strip_tbi(CPUARMState *env, uint64_t pt= r) return ptr; } } -#endif + +static uint8_t *allocation_tag_mem(CPUARMState *env, uint64_t ptr, + bool write, uintptr_t ra) +{ + /* Tag storage not implemented. */ + return NULL; +} =20 static int get_allocation_tag(CPUARMState *env, uint64_t ptr, uintptr_t ra) { + uint8_t *mem =3D allocation_tag_mem(env, ptr, false, ra); + + if (mem) { + int ofs =3D extract32(ptr, LOG2_TAG_GRANULE, 1) * 4; + return extract32(atomic_read(mem), ofs, 4); + } /* Tag storage not implemented. */ return -1; } @@ -240,3 +250,139 @@ uint64_t HELPER(gmi)(uint64_t ptr, uint64_t mask) int tag =3D allocation_tag_from_addr(ptr); return mask | (1ULL << tag); } + +uint64_t HELPER(ldg)(CPUARMState *env, uint64_t ptr) +{ + int el =3D arm_current_el(env); + uint64_t sctlr =3D arm_sctlr(env, el); + int rtag; + + /* Trap if accessing an invalid page. */ + rtag =3D get_allocation_tag(env, ptr, GETPC()); + + /* + * The tag is squashed to zero if the page does not support tags, + * or if the OS is denying access to the tags. + */ + if (rtag < 0 || !allocation_tag_access_enabled(env, el, sctlr)) { + rtag =3D 0; + } + + return address_with_allocation_tag(ptr, rtag); +} + +static void check_tag_aligned(CPUARMState *env, uint64_t ptr, uintptr_t ra) +{ + if (unlikely(ptr & MAKE_64BIT_MASK(0, LOG2_TAG_GRANULE))) { + arm_cpu_do_unaligned_access(ENV_GET_CPU(env), ptr, MMU_DATA_STORE, + cpu_mmu_index(env, false), ra); + g_assert_not_reached(); + } +} + +/* For use in a non-parallel context, store to the given nibble. */ +static void store_tag1(uint64_t ptr, uint8_t *mem, int tag) +{ + int ofs =3D extract32(ptr, LOG2_TAG_GRANULE, 1) * 4; + uint8_t old =3D atomic_read(mem); + uint8_t new =3D deposit32(old, ofs, 4, tag); + + atomic_set(mem, new); +} + +/* For use in a parallel context, atomically store to the given nibble. */ +static void store_tag1_parallel(uint64_t ptr, uint8_t *mem, int tag) +{ + int ofs =3D extract32(ptr, LOG2_TAG_GRANULE, 1) * 4; + uint8_t old =3D atomic_read(mem); + + while (1) { + uint8_t new =3D deposit32(old, ofs, 4, tag); + uint8_t cmp =3D atomic_cmpxchg(mem, old, new); + if (likely(cmp =3D=3D old)) { + return; + } + old =3D cmp; + } +} + +static uint64_t do_stg(CPUARMState *env, uint64_t ptr, uintptr_t ra, + void (*store1)(uint64_t, uint8_t *, int)) +{ + int el =3D arm_current_el(env); + uint64_t sctlr =3D arm_sctlr(env, el); + uint8_t *mem; + + check_tag_aligned(env, ptr, ra); + + /* Trap if accessing an invalid page. */ + mem =3D allocation_tag_mem(env, ptr, true, ra); + + /* Store if page supports tags and access is enabled. */ + if (mem && allocation_tag_access_enabled(env, el, sctlr)) { + store1(ptr, mem, allocation_tag_from_addr(ptr)); + } + + /* Clean the pointer for use by stzg. */ + return strip_tbi(env, ptr); +} + +uint64_t HELPER(stg)(CPUARMState *env, uint64_t ptr) +{ + return do_stg(env, ptr, GETPC(), store_tag1); +} + +uint64_t HELPER(stg_parallel)(CPUARMState *env, uint64_t ptr) +{ + return do_stg(env, ptr, GETPC(), store_tag1_parallel); +} + +static uint64_t do_st2g(CPUARMState *env, uint64_t ptr1, uintptr_t ra, + void (*store1)(uint64_t, uint8_t *, int)) +{ + int el =3D arm_current_el(env); + uint64_t sctlr =3D arm_sctlr(env, el); + uint64_t ptr2 =3D ptr1 + (1 << LOG2_TAG_GRANULE); + uint8_t *mem1, *mem2; + + check_tag_aligned(env, ptr1, ra); + + /* Trap if accessing an invalid page(s). */ + mem1 =3D mem2 =3D allocation_tag_mem(env, ptr1, true, ra); + if (unlikely((ptr1 ^ ptr2) & TARGET_PAGE_MASK)) { + /* The two stores are across two pages. */ + mem2 =3D allocation_tag_mem(env, ptr2, true, ra); + } + + /* Store if page supports tags and access is enabled. */ + if ((mem1 || mem2) && allocation_tag_access_enabled(env, el, sctlr)) { + int tag =3D allocation_tag_from_addr(ptr1); + + if (likely(mem1 =3D=3D mem2)) { + /* The two stores are to the same byte. */ + tag |=3D tag << 4; + atomic_set(mem1, tag); + } else { + /* The two stores are across two bytes. */ + if (mem1) { + store1(ptr1, mem1, tag); + } + if (mem2) { + store1(ptr2, mem2, tag); + } + } + } + + /* Clean the pointer for use by stz2g. */ + return strip_tbi(env, ptr1); +} + +uint64_t HELPER(st2g)(CPUARMState *env, uint64_t ptr) +{ + return do_st2g(env, ptr, GETPC(), store_tag1); +} + +uint64_t HELPER(st2g_parallel)(CPUARMState *env, uint64_t ptr) +{ + return do_st2g(env, ptr, GETPC(), store_tag1_parallel); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 3e46ee6f69..539c25a80b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3603,6 +3603,117 @@ static void disas_ldst_single_struct(DisasContext *= s, uint32_t insn) } } =20 +/* + * Load/Store memory tags + * + * 31 30 29 24 22 21 12 10 5 0 + * +-----+-------------+-----+---+------+-----+------+------+ + * | 1 1 | 0 1 1 0 0 1 | op1 | 1 | imm9 | op2 | Rn | Rt | + * +-----+-------------+-----+---+------+-----+------+------+ + */ +static void disas_ldst_tag(DisasContext *s, uint32_t insn) +{ + int rt =3D extract32(insn, 0, 5); + int rn =3D extract32(insn, 5, 5); + uint64_t offset =3D sextract64(insn, 12, 9) << LOG2_TAG_GRANULE; + int op2 =3D extract32(insn, 10, 3); + int op1 =3D extract32(insn, 22, 2); + bool is_load =3D false, is_pair =3D false, is_zero =3D false; + int index =3D 0; + TCGv_i64 dirty_addr, clean_addr; + + if ((insn & 0xff200000) !=3D 0xd9200000 + || !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + + switch (op1) { + case 0: /* STG */ + if (op2 !=3D 0) { + /* STG */ + index =3D op2 - 2; + break; + } + goto do_unallocated; + case 1: + if (op2 !=3D 0) { + /* STZG */ + is_zero =3D true; + index =3D op2 - 2; + } else { + /* LDG */ + is_load =3D true; + } + break; + case 2: + if (op2 !=3D 0) { + /* ST2G */ + is_pair =3D true; + index =3D op2 - 2; + break; + } + goto do_unallocated; + case 3: + if (op2 !=3D 0) { + /* STZ2G */ + is_pair =3D is_zero =3D true; + index =3D op2 - 2; + break; + } + goto do_unallocated; + + default: + do_unallocated: + unallocated_encoding(s); + return; + } + + dirty_addr =3D read_cpu_reg_sp(s, rn, true); + if (index <=3D 0) { + /* pre-index or signed offset */ + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); + } + + clean_addr =3D tcg_temp_new_i64(); + if (is_load) { + gen_helper_ldg(cpu_reg(s, rt), cpu_env, dirty_addr); + } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { + if (is_pair) { + gen_helper_st2g_parallel(clean_addr, cpu_env, dirty_addr); + } else { + gen_helper_stg_parallel(clean_addr, cpu_env, dirty_addr); + } + } else { + if (is_pair) { + gen_helper_st2g(clean_addr, cpu_env, dirty_addr); + } else { + gen_helper_stg(clean_addr, cpu_env, dirty_addr); + } + } + + if (is_zero) { + TCGv_i64 tcg_zero =3D tcg_const_i64(0); + int mem_index =3D get_mem_index(s); + int i, n =3D (1 + is_pair) << LOG2_TAG_GRANULE; + + for (i =3D 0; i < n; i +=3D 8) { + tcg_gen_qemu_st_i64(tcg_zero, clean_addr, mem_index, MO_Q); + tcg_gen_addi_i64(clean_addr, clean_addr, 8); + } + tcg_temp_free_i64(tcg_zero); + } + tcg_temp_free_i64(clean_addr); + + if (index !=3D 0) { + /* pre-index or post-index */ + if (index > 0) { + /* post-index */ + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); + } + tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr); + } +} + /* Loads and stores */ static void disas_ldst(DisasContext *s, uint32_t insn) { @@ -3627,6 +3738,9 @@ static void disas_ldst(DisasContext *s, uint32_t insn) case 0x0d: /* AdvSIMD load/store single structure */ disas_ldst_single_struct(s, insn); break; + case 0x19: /* Load/store tag */ + disas_ldst_tag(s, insn); + break; default: unallocated_encoding(s); break; --=20 2.17.2 From nobody Fri May 3 10:47:40 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549848692260205.85315687927448; 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=n4B8y8+rNu+NTfg8hfCg33xodySkURfq2FGlIVTIp5U=; b=IxV42RnRrS15dVJKns6jDSdjgAuPFwL/uwFwQtINaxy48JKpTNa85PzMSSaFXCUByf aEgzffwd7IEEcvA10u33zF+2h9VKlifCY0L7bo6mboKYikNQWtoaZiIMWUbhdFAvujk/ 7Ghy0TLRhjyuN4lMQhcHdVKTWQiffR0QciHRNyt+4Z8PWUAEnTXwvL38cl+fuwKLBoN9 q9AcFfX24wUyLu/X4kAHKY+S8zvKMThvE8hKL3HvNjvBaCvMFFs6D1oKRPs8JY9+aJo7 SvCPXeve4RV9EGZR2ABHAQ1kf11GRIjtcw5wE5WxO2OM1rA0VzrLcCGZxxDMlkIoBWYu iPOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=n4B8y8+rNu+NTfg8hfCg33xodySkURfq2FGlIVTIp5U=; b=nYUg93p3P1hZEUYvKD6Be58ZhHgMUFrjVMiNV4csdgyLmphFufHEfMTnU3rEw0/sHx Dm3vf8Mflez2KIBxoiv9RQWXzNyrB1wtBSnileBVNPFxNwtTrA+LrLLJrwC80dpAS7XE 9AmH04SGvnbQtyN9CMVpGF82yOlE4rYgLnpCbmoS0ylj2fFiMiLFAiIJX+GLKp3Pjk0w WGncKvCrq8YJsihyaRBgz9K9vuiPOl02y5zMP/mx0xz0V9NbU5DwMHC6M3sVcnS0L49Q X8AOgfzdDZB7S+6h72gQiEkcGCQaz+oJZUup3Nw+RXwmdJLrIRyNOJUG96jdQeYWzX22 N7ew== X-Gm-Message-State: AHQUAua2ligxuz5DVmyHSDWbN+Mf4UKGgm4OjxAb1HNVXJpwjNltvqkR QFiixCvxnEh8xmeRQ7A8hG35oGXJ34I= X-Google-Smtp-Source: AHgI3IYe+gTn78INHw6WY8psjzHUlmof5e7uQRS1e6fvLpyLZIm7ujQSExarbMc3/P5p82+hzMdN9Q== X-Received: by 2002:a62:3888:: with SMTP id f130mr33614130pfa.132.1549847332766; Sun, 10 Feb 2019 17:08:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:19 -0800 Message-Id: <20190211010829.29869-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::434 Subject: [Qemu-devel] [PATCH v2 16/26] target/arm: Implement the STGP instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 539c25a80b..9bd68d522c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2701,7 +2701,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t in= sn) * +-----+-------+---+---+-------+---+-------+-------+------+------+ * * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit - * LDPSW 01 + * LDPSW/STGP 01 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit * V: 0 -> GPR, 1 -> Vector * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index, @@ -2726,6 +2726,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t= insn) bool is_signed =3D false; bool postindex =3D false; bool wback =3D false; + bool set_tag =3D false; =20 TCGv_i64 clean_addr, dirty_addr; =20 @@ -2738,6 +2739,14 @@ static void disas_ldst_pair(DisasContext *s, uint32_= t insn) =20 if (is_vector) { size =3D 2 + opc; + } else if (opc =3D=3D 1 && !is_load) { + /* STGP */ + if (!dc_isar_feature(aa64_mte_insn_reg, s) || index =3D=3D 0) { + unallocated_encoding(s); + return; + } + size =3D 3; + set_tag =3D true; } else { size =3D 2 + extract32(opc, 1, 1); is_signed =3D extract32(opc, 0, 1); @@ -2788,7 +2797,12 @@ static void disas_ldst_pair(DisasContext *s, uint32_= t insn) if (!postindex) { tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); } - clean_addr =3D clean_data_tbi(s, dirty_addr, wback || rn !=3D 31); + if (set_tag) { + clean_addr =3D new_tmp_a64(s); + gen_helper_stg(clean_addr, cpu_env, dirty_addr); + } else { + clean_addr =3D clean_data_tbi(s, dirty_addr, wback || rn !=3D 31); + } =20 if (is_vector) { if (is_load) { --=20 2.17.2 From nobody Fri May 3 10:47:40 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549848340079330.6593967009327; Sun, 10 Feb 2019 17:25:40 -0800 (PST) Received: from localhost ([127.0.0.1]:42321 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt0Lp-0001Ul-SH for importer@patchew.org; Sun, 10 Feb 2019 20:25:37 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37648) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt05w-0005xO-6v for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gt05t-0000Bn-C8 for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:12 -0500 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:45062) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gt05s-0008Jg-RO for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:09 -0500 Received: by mail-pl1-x641.google.com with SMTP id a14so4492056plm.12 for ; Sun, 10 Feb 2019 17:08:55 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7HsOcQyaMevodOsm6h2V5NoXxK7MjvAqlm4dwXNbUE0=; b=hazg7KQhTZgxswEpm5yJjmAMfTbG7j/FcXuwRaLquCo3kaZdQpB/E/33P2w64PGymB cMyF6wmmXlg6+V52JA9IQaWThN4xAyyl0QpNkjsG+ujVfWQTnZh7V9b5M4hcCe9OqyS9 0zXuNDRI9Hk89T8aHKzy7Hov3gcNrGPf3OpRUr39rYxq8i/TeHBNhJhM1YxndjeTC3cr jUvy5f+TWYdnyq6SiIlg3G8VloTn2PQBw7Cn3Dhoo6E2/x5GYC+FCAhBeyRyH7bbdFuH gqdhYM7xBRrp//2aIR00NMpd8ZZp7BPe0oqFnc6tKZN4utkCtrrprn2hy+HNKLLhqZBF SOkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7HsOcQyaMevodOsm6h2V5NoXxK7MjvAqlm4dwXNbUE0=; b=HpONsgkFNf2qSVJ5SexIJwjFUUYStaWULaP29xutNJBd/NHOSZohAJjgVl3dptnyc0 lv4kpzl3klL89GAvXjw6cHqZuctNICVr1hbE42CZ1aA85K9KhnHTQipjPTx+rq0dFwfc Sl0aSO1xtN+eYWFoaacnxWOsRcTA6ymcFsGAF8XL8QhyjGR+Pjp4vn2zCFIZeRB5XBjf Zqe8724+0gD3Rh6WuqJOr0emeBafP1t0U3aswn8ieTvTMRTSshD0QQ4fvzJtYNLOLbvo NhRwB9aSr8OMf71EZZfmR2RuU3D2USPyB/J7yxSu+nY/EaBEKif2tnSJ1mgCXIzJXN3F BdNw== X-Gm-Message-State: AHQUAuZs+QOPtZZfLl/jhY5mg2ORVG3hs3DIp+91vvm/GN1K51DqiKEA USmsfbiWWpB18Khn99Dq7vKJRmp4YRs= X-Google-Smtp-Source: AHgI3IbSZAagCFDS+2SasuE/VGYGYB4Hz2U6CZIZSngo090tny5hAl0p5pKe6Q8pcm4byFEofKgd0w== X-Received: by 2002:a17:902:1008:: with SMTP id b8mr34155918pla.252.1549847333992; Sun, 10 Feb 2019 17:08:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:20 -0800 Message-Id: <20190211010829.29869-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v2 17/26] target/arm: Implement the access tag cache flushes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Like the regular data cache flushes, these are nops within qemu. Signed-off-by: Richard Henderson --- target/arm/helper.c | 48 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 2d9c070bb3..74bace81e4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5772,6 +5772,54 @@ static const ARMCPRegInfo mte_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 3, .crn =3D 4, .crm =3D 2, .opc2 =3D 7, .type =3D ARM_CP_NO_RAW, .access =3D PL0_RW, .readfn =3D tco_read, .writefn =3D tco_write }, + { .name =3D "IGVAC", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 3, + .type =3D ARM_CP_NOP, .access =3D PL1_W }, + { .name =3D "IGSW", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 4, + .type =3D ARM_CP_NOP, .access =3D PL1_W }, + { .name =3D "CGSW", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 4, + .type =3D ARM_CP_NOP, .access =3D PL1_W }, + { .name =3D "CIGSW", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 4, + .type =3D ARM_CP_NOP, .access =3D PL1_W }, + { .name =3D "CGVAC", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 3, + .type =3D ARM_CP_NOP, .access =3D PL1_W }, + { .name =3D "CGVAP", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 12, .opc2 =3D 3, + .type =3D ARM_CP_NOP, .access =3D PL1_W }, + { .name =3D "CGVADP", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 13, .opc2 =3D 3, + .type =3D ARM_CP_NOP, .access =3D PL1_W }, + { .name =3D "CIGVAC", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 3, + .type =3D ARM_CP_NOP, .access =3D PL1_W }, + { .name =3D "IGDVAC", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL1_W }, + { .name =3D "IGDSW", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 6, + .type =3D ARM_CP_NOP, .access =3D PL1_W }, + { .name =3D "CGDSW", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 6, + .type =3D ARM_CP_NOP, .access =3D PL1_W }, + { .name =3D "CIGDSW", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 6, + .type =3D ARM_CP_NOP, .access =3D PL1_W }, + { .name =3D "CGDVAC", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL1_W }, + { .name =3D "CGDVAP", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 12, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL1_W }, + { .name =3D "CGDVADP", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 13, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL1_W }, + { .name =3D "CIGDVAC", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL1_W }, REGINFO_SENTINEL }; #endif --=20 2.17.2 From nobody Fri May 3 10:47:40 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549848839627730.5131573718159; Sun, 10 Feb 2019 17:33:59 -0800 (PST) Received: from localhost ([127.0.0.1]:42460 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt0Tp-0007x7-Ax for importer@patchew.org; Sun, 10 Feb 2019 20:33:53 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37757) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt05z-000611-DO for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gt05t-0000CE-E9 for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:15 -0500 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:37846) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gt05s-0008KR-Vi for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:09 -0500 Received: by mail-pl1-x643.google.com with SMTP id b5so4516159plr.4 for ; Sun, 10 Feb 2019 17:08:56 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1ThSYlTjjjdful+PEa+IzVjavr7hehgRai0NxwGpzTA=; b=lb8pLBzY99qbbnUezoxVC8+N1IJ7AAi2fNowxzt9sV/FSUWgss64EUFGWgDrW3176P 7AU9xlHugcY9U+JJhBHxw0gL96iVsAmdi+QWAGXIGSdhO29dPUuwcUTTrfQ5a7DPYGLV dPdWLruaK4KfivPHZ35kyGllIEAJhoa8CGGt665Ae9wrnVcJ6MkmjwGokxhEfjaQZrXa cory593DEWqeNGx17URLtv7Ej0nnNwK0d9r02xxyz/gVQyHoEaTdnFHGTmcABGk5bwz1 UzJ+tcfRahzgTzozABie++4bZo0XL8EsGrCKTy4MBTu+2II9sEMd02Unqw1roPAkVY/k deYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1ThSYlTjjjdful+PEa+IzVjavr7hehgRai0NxwGpzTA=; b=kjLXM/Iw1Z3M6jj9/V6ple5F+tLb4Vz1316Pi5OGMFr+rQFIThAGwoeBfYkSJ6h5wU AdFKd69zYBZBmnwpHFU3GyQZ43AMHMcLvSL/Od9fYvmIUadykpZe83Z3+f39a2/TJd1e 8Rtosf36fnf10tQSbxHnuc1BvfZEgnWHz13ng7ptwsWpNjGYx9yubI172tYtX0kQhzvp TjLatW74NOWhV0q6CgKfai0Hi1CeRxrF2PEfYuUxRiQybxJwiCfMOCIAb21qPye+42Yo IRSQTcFQ3fki1whhhVvc7RxFEAgP710btsl7pxJpA5KVMYS0tSjqYkMr7esFPiTJAVIG NZow== X-Gm-Message-State: AHQUAuadS3GwHo0d276AmUqx3/ugK1MjDY61H3Nab+ClVBjlmBiIH7YK IrgvJq3hjvQzR+JmGnOcFHVStUihZOA= X-Google-Smtp-Source: AHgI3IYw1XDACfVbfbwxFwwW/MDf3zBGdIE3lCl9UB8/v4IwwY+G9TWLZfwmYhGwXp3hQOWDKRXDjQ== X-Received: by 2002:a17:902:8bc6:: with SMTP id r6mr34676795plo.67.1549847335170; Sun, 10 Feb 2019 17:08:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:21 -0800 Message-Id: <20190211010829.29869-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v2 18/26] target/arm: Implement data cache set allocation tags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is DC GVA and DC GZVA. Signed-off-by: Richard Henderson --- v2: Use allocation_tag_mem + memset. --- target/arm/cpu.h | 4 +++- target/arm/helper-a64.h | 1 + target/arm/helper.c | 16 ++++++++++++++++ target/arm/mte_helper.c | 26 ++++++++++++++++++++++++++ target/arm/translate-a64.c | 9 +++++++++ 5 files changed, 55 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 74633a7a78..ca32939483 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2160,7 +2160,9 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpreg= id) #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) -#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA +#define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600) +#define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700) +#define ARM_LAST_SPECIAL ARM_CP_DC_GZVA #define ARM_CP_FPU 0x1000 #define ARM_CP_SVE 0x2000 #define ARM_CP_NO_GDB 0x4000 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index a00364fb4c..4ad900d36e 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -113,3 +113,4 @@ DEF_HELPER_FLAGS_2(stg, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_2(st2g, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_2(stg_parallel, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_2(st2g_parallel, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_2(dc_gva, TCG_CALL_NO_RWG, void, env, i64) diff --git a/target/arm/helper.c b/target/arm/helper.c index 74bace81e4..9fac3628e5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5820,6 +5820,22 @@ static const ARMCPRegInfo mte_reginfo[] =3D { { .name =3D "CIGDVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 5, .type =3D ARM_CP_NOP, .access =3D PL1_W }, + { .name =3D "GVA", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 4, .opc2 =3D 3, + .access =3D PL0_W, .type =3D ARM_CP_DC_GVA, +#ifndef CONFIG_USER_ONLY + /* Avoid overhead of an access check that always passes in user-mode= */ + .accessfn =3D aa64_zva_access, +#endif + }, + { .name =3D "GZVA", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 4, .opc2 =3D 4, + .access =3D PL0_W, .type =3D ARM_CP_DC_GZVA, +#ifndef CONFIG_USER_ONLY + /* Avoid overhead of an access check that always passes in user-mode= */ + .accessfn =3D aa64_zva_access, +#endif + }, REGINFO_SENTINEL }; #endif diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 13befdbf86..93f7cccee2 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -386,3 +386,29 @@ uint64_t HELPER(st2g_parallel)(CPUARMState *env, uint6= 4_t ptr) { return do_st2g(env, ptr, GETPC(), store_tag1_parallel); } + +void HELPER(dc_gva)(CPUARMState *env, uint64_t ptr) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + int el =3D arm_current_el(env); + uint64_t sctlr =3D arm_sctlr(env, el); + size_t blocklen =3D 4 << cpu->dcz_blocksize; + uint8_t *mem; + int rtag; + + ptr =3D QEMU_ALIGN_DOWN(ptr, blocklen); + + /* Trap if accessing an invalid page. */ + mem =3D allocation_tag_mem(env, ptr, true, GETPC()); + + /* No action if page does not support tags, or if access is disabled. = */ + if (!mem || !allocation_tag_access_enabled(env, el, sctlr)) { + return; + } + + rtag =3D allocation_tag_from_addr(ptr); + rtag |=3D rtag << 4; + + assert(blocklen % (2 << LOG2_TAG_GRANULE) =3D=3D 0); + memset(mem, rtag, blocklen / (2 << LOG2_TAG_GRANULE)); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9bd68d522c..a3bd2e27ef 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1811,6 +1811,15 @@ static void handle_sys(DisasContext *s, uint32_t ins= n, bool isread, tcg_rt =3D cpu_reg(s, rt); gen_helper_dc_zva(cpu_env, tcg_rt); return; + case ARM_CP_DC_GVA: + tcg_rt =3D cpu_reg(s, rt); + gen_helper_dc_gva(cpu_env, tcg_rt); + return; + case ARM_CP_DC_GZVA: + tcg_rt =3D cpu_reg(s, rt); + gen_helper_dc_zva(cpu_env, tcg_rt); + gen_helper_dc_gva(cpu_env, tcg_rt); + return; default: break; } --=20 2.17.2 From nobody Fri May 3 10:47:40 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wOgP7lobhsemXB3OvFkJ+c0fo71lcU0DJjKscTksgDY=; b=LhHuHHsouSudzJgxA6esj9Dxhq3q4AUyafQvjtnA1+FemlnXj1cNFR+F96mJ+m8yaK nhlaBSV10xPPH+BNG5xgwE+7FnA6K29TAmYMNx2nuuDbFVb/INHJ6weI8CZsWBwbFDal z+wyHOSfyeqcEJ5bS6uZvIJgVrjGmxxN6Qr/vQbYvYppX6iOsl2IRsXghpcuVdHWKaVJ 5PUEfip/ZMCalKWaixJNQQJ4MRQFCE0artppcNiu40fiJZieX7hVBAWStPAyzj85pB54 vebBdocE9S7x8xV4lr84jGS2/aS4xX5NqYnXip2BUOD9VdLOmkEDnn9Kes8tTb71EblZ ooCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wOgP7lobhsemXB3OvFkJ+c0fo71lcU0DJjKscTksgDY=; b=P3d8q6iH9wTvpSgKO1G1aB4U/A3j9/LVQDU3OTR7hZPPqGi7DHOcD8JN27DjsDyfN1 88E5uWaPVuJdIT+jqWLe/s8wSjyggBXaptRvhWG+fubXKPBch+gXLrEAWUlH+ijBHiKE 5AdnzT4bOigeKViGsJo1/QGO+jtGPiKmMWYRilyY7lwZ7quyTL6Ck+VIMyd+3Obf7UDe g4OAD7N6DND544ISJJ5zgVi2WxCLBAJwU32UCjee/yFKc4RTBNdpzW/IJjxfpzFuxTBW gbtwyE8UWpbpF6ZDo88uvfXaNi7KEZ0RVVeFj2zknP3311yv5tad0Cyvs7usx8WIs87V 4I3A== X-Gm-Message-State: AHQUAuYDNrih4a4+4GOBi7fPpVLNKiwlvd1gOGGjTlXRinInH2LuR8Q+ JibSCRkAf8h0KLzC0txtHIk5eTsLM40= X-Google-Smtp-Source: AHgI3IZz74GT70JXn5s/ZbeLkYKuO86SGYDv3fk1PToupcUAbrpL9Cfi3qeaeZvgQ2Afm/gnE0+wPQ== X-Received: by 2002:a17:902:a50e:: with SMTP id s14mr23328196plq.311.1549847336348; Sun, 10 Feb 2019 17:08:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:22 -0800 Message-Id: <20190211010829.29869-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::635 Subject: [Qemu-devel] [PATCH v2 19/26] target/arm: Set PSTATE.TCO on exception entry X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" R0085 specifies that exception handlers begin with tag checks overridden. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Only set if MTE feature present. --- target/arm/helper.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 9fac3628e5..a3ad5bc54e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9455,6 +9455,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) target_ulong addr =3D env->cp15.vbar_el[new_el]; unsigned int new_mode =3D aarch64_pstate_mode(new_el, true); unsigned int cur_el =3D arm_current_el(env); + unsigned int new_pstate; =20 /* * Note that new_el can never be 0. If cur_el is 0, then @@ -9548,7 +9549,11 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *c= s) qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", env->elr_el[new_el]); =20 - pstate_write(env, PSTATE_DAIF | new_mode); + new_pstate =3D new_mode | PSTATE_DAIF; + if (cpu_isar_feature(aa64_mte, cpu)) { + new_pstate |=3D PSTATE_TCO; + } + pstate_write(env, new_pstate); env->aarch64 =3D 1; aarch64_restore_sp(env, new_el); =20 --=20 2.17.2 From nobody Fri May 3 10:47:40 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549848336161732.9436834042665; Sun, 10 Feb 2019 17:25:36 -0800 (PST) Received: from localhost ([127.0.0.1]:42309 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt0Lh-0001Pr-4A for importer@patchew.org; Sun, 10 Feb 2019 20:25:29 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37597) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt05v-0005wL-16 for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gt05s-00007X-3f for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:10 -0500 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:44214) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gt05r-0008O9-Mp for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:07 -0500 Received: by mail-pg1-x542.google.com with SMTP id y1so4188581pgk.11 for ; Sun, 10 Feb 2019 17:08:59 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IYfDmawl379GZgWCUsgON1GHK8BY9wa/LpINsjn/HBc=; b=X+1o0xIlcU4rnnY4YsMSmvoeIktLuTh+vW6ZUxzd5U2pbMbbcbHtdfA/su8IZSsMLT obyPCceQM6zT/G6epiYKvtQguU392xKcwKz6D7lODC/PQLXB8D0mWmzncB1A+Ghu5QqO HTY2FPeAnEKPfQkDvOGRK7pQmcXHAjw7QghbpLjpbFeXBS0RAkCADh1IzIrtCiYG2nrc FQKnXoja/uuqnUnrR5Vubxphdc4qBc6qeWm9SeDHvsJmH/4jZmeR3MSbPT/YCdcUEUHP Vxn/GmGGJzJuY28MQiQhOEDZs5490xMwPymKCThO0S4P+Dae2lklZL3wBHY0j+6mrDi0 o++g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IYfDmawl379GZgWCUsgON1GHK8BY9wa/LpINsjn/HBc=; b=pUiPofkUPXnW7Bm9+xn9dtke4O+u7HWUhWXDgsWN+fC5BoaqAzsnjaCfZf4OZ24Cmj LvALoBP8Sn7mzzI/j140g4Q0EIDtS1jQR4kDp3N+BBpBAFZkFIveYzXlsqjHFkaxz5Re HglbNaASyoTL4382FmRxl1y2OOFjOeFav6dqNdPAjfpQqcbFmx7UQ8+EQakmrv+zFqcr 51I8bEvvtIjZyTY48KPUbDM6ZRfGVnS8BMWNwNA13yklq1UXieYK6JpbC0FptFLn8Iun KLx5JhpQPJB/yYks8JXu7fPeOtJsUVEztRb/ytd7kTbYEsdFx9+jDpemtdPh7+9MXF7u fVLg== X-Gm-Message-State: AHQUAuY4OLUoi7CgzfQVZRgmD7KfCOVbLRYqxc+DcEOZmzjINYf0DoE6 Sw3LFAMUL3V8kKOqFp7SzrtREE82ryI= X-Google-Smtp-Source: AHgI3IY551mKRVgVONKtu8PAe73OeQajWJ1l6jWh7qAStxzYlc6WwE0dgav5Od2ZT5yieJiV8RVfzA== X-Received: by 2002:a62:9917:: with SMTP id d23mr16055952pfe.88.1549847337734; Sun, 10 Feb 2019 17:08:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:23 -0800 Message-Id: <20190211010829.29869-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v2 20/26] tcg: Introduce target-specific page data for user-only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" At the same time, remember MAP_SHARED as PAGE_SHARED. When mapping new pages, make sure that old target-specific page data is removed. Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 10 ++++++++-- accel/tcg/translate-all.c | 28 ++++++++++++++++++++++++++++ linux-user/mmap.c | 10 ++++++++-- linux-user/syscall.c | 4 ++-- 4 files changed, 46 insertions(+), 6 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index b16c9ec513..e88ecad0b3 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -244,10 +244,14 @@ extern intptr_t qemu_host_page_mask; #define PAGE_WRITE_ORG 0x0010 /* Invalidate the TLB entry immediately, helpful for s390x * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs= () */ -#define PAGE_WRITE_INV 0x0040 +#define PAGE_WRITE_INV 0x0020 +/* Page is mapped shared. */ +#define PAGE_SHARED 0x0040 +/* For use with page_set_flags: page is being replaced; target_data cleare= d. */ +#define PAGE_RESET 0x0080 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) /* FIXME: Code that sets/uses this is broken and needs to go away. */ -#define PAGE_RESERVED 0x0020 +#define PAGE_RESERVED 0x0100 #endif =20 #if defined(CONFIG_USER_ONLY) @@ -260,6 +264,8 @@ int walk_memory_regions(void *, walk_memory_regions_fn); int page_get_flags(target_ulong address); void page_set_flags(target_ulong start, target_ulong end, int flags); int page_check_range(target_ulong start, target_ulong len, int flags); +void *page_get_target_data(target_ulong address); +void *page_alloc_target_data(target_ulong address, size_t size); #endif =20 CPUArchState *cpu_copy(CPUArchState *env); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 8f593b926f..6cc266428d 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -107,6 +107,7 @@ typedef struct PageDesc { unsigned int code_write_count; #else unsigned long flags; + void *target_data; #endif #ifndef CONFIG_USER_ONLY QemuSpin lock; @@ -2476,6 +2477,7 @@ int page_get_flags(target_ulong address) void page_set_flags(target_ulong start, target_ulong end, int flags) { target_ulong addr, len; + bool reset_target_data; =20 /* This function should never be called with addresses outside the guest address space. If this assert fires, it probably indicates @@ -2492,6 +2494,8 @@ void page_set_flags(target_ulong start, target_ulong = end, int flags) if (flags & PAGE_WRITE) { flags |=3D PAGE_WRITE_ORG; } + reset_target_data =3D !(flags & PAGE_VALID) || (flags & PAGE_RESET); + flags &=3D ~PAGE_RESET; =20 for (addr =3D start, len =3D end - start; len !=3D 0; @@ -2505,10 +2509,34 @@ void page_set_flags(target_ulong start, target_ulon= g end, int flags) p->first_tb) { tb_invalidate_phys_page(addr, 0); } + if (reset_target_data && p->target_data) { + g_free(p->target_data); + p->target_data =3D NULL; + } p->flags =3D flags; } } =20 +void *page_get_target_data(target_ulong address) +{ + PageDesc *p =3D page_find(address >> TARGET_PAGE_BITS); + return p ? p->target_data : NULL; +} + +void *page_alloc_target_data(target_ulong address, size_t size) +{ + PageDesc *p =3D page_find(address >> TARGET_PAGE_BITS); + void *ret =3D NULL; + + if (p) { + ret =3D p->target_data; + if (!ret && (p->flags & PAGE_VALID)) { + p->target_data =3D ret =3D g_malloc0(size); + } + } + return ret; +} + int page_check_range(target_ulong start, target_ulong len, int flags) { PageDesc *p; diff --git a/linux-user/mmap.c b/linux-user/mmap.c index e0249efe4f..0b786b87a2 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -562,7 +562,11 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, i= nt prot, } } the_end1: - page_set_flags(start, start + len, prot | PAGE_VALID); + if ((flags & MAP_TYPE) =3D=3D MAP_SHARED) { + prot |=3D PAGE_SHARED; + } + prot |=3D PAGE_RESET | PAGE_VALID; + page_set_flags(start, start + len, prot); the_end: #ifdef DEBUG_MMAP printf("ret=3D0x" TARGET_ABI_FMT_lx "\n", start); @@ -754,9 +758,11 @@ abi_long target_mremap(abi_ulong old_addr, abi_ulong o= ld_size, new_addr =3D -1; } else { new_addr =3D h2g(host_addr); + /* FIXME: Move page flags (and target_data?) for each page. */ prot =3D page_get_flags(old_addr); page_set_flags(old_addr, old_addr + old_size, 0); - page_set_flags(new_addr, new_addr + new_size, prot | PAGE_VALID); + page_set_flags(new_addr, new_addr + new_size, + prot | PAGE_VALID | PAGE_RESET); } tb_invalidate_phys_range(new_addr, new_addr + new_size); mmap_unlock(); diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 5bbb72f3d5..9d89b40321 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -3884,8 +3884,8 @@ static inline abi_ulong do_shmat(CPUArchState *cpu_en= v, raddr=3Dh2g((unsigned long)host_raddr); =20 page_set_flags(raddr, raddr + shm_info.shm_segsz, - PAGE_VALID | PAGE_READ | - ((shmflg & SHM_RDONLY)? 0 : PAGE_WRITE)); + PAGE_VALID | PAGE_SHARED | PAGE_RESET | PAGE_READ | + (shmflg & SHM_RDONLY ? 0 : PAGE_WRITE)); =20 for (i =3D 0; i < N_SHM_REGIONS; i++) { if (!shm_regions[i].in_use) { --=20 2.17.2 From nobody Fri May 3 10:47:40 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549848105101739.6506169137464; Sun, 10 Feb 2019 17:21:45 -0800 (PST) Received: from localhost ([127.0.0.1]:42269 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt0I2-00071Z-0W for importer@patchew.org; Sun, 10 Feb 2019 20:21:42 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37710) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt05x-0005yn-5c for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gt05t-0000Bu-Dw for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:13 -0500 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:39980) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gt05s-0008PA-Ua for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:09 -0500 Received: by mail-pg1-x542.google.com with SMTP id z10so4201520pgp.7 for ; Sun, 10 Feb 2019 17:09:00 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0B3omcAJPniMrgzOgR3FjeAcoYmr0yasFqZ8a7CEW3A=; b=UyE5VRudvKIG2bXgcH7310tdsMfST6huQexl0rC0sTLQVDqqNd77C/99AfxsXNiTds 7X5sR72QFwV6W3+oL76OeED16EnUQPLSb/gbW9UtdTUTmNndV1H4TF3hYxrEwpc3ge5Y 4PPULoZLuRYu67GMmZlYDw1At9aihrbz94g73KIpb4QU8VT99euQo0Q/n4fcvRrXDLVY 2pebnuxWFabtRN1hT+xHE1iEIzNDHVCVH1qos922YjEcTu2qNrRNf3VIn1n9BIg8jZY6 gPr5KnG7KoybxiC6NPArTogbplVCINbtcjjAcS3jznPdk+HDBdpdv7yP1AFxVLExPOmn eujQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0B3omcAJPniMrgzOgR3FjeAcoYmr0yasFqZ8a7CEW3A=; b=W1eh3XmhY+MdGF58Z4ASozJc2hMGFJIMT2vCfe/Yma6c0DeqnFKIwg11V0Fied0IKW l8FRyGP0u6FBXhIFdTXK97zDGdUXnpi0zVaRrq0gCFZ7Ef0UKWdyKs2HR/4rXbIm2Tfe 2RcE2vQjJrxnmSiXcxLULztG6LQQZPLnARZ5RJpdOTEfya6TZfhX8Q2TubA5jf2vATgq 4q3yUyaIbRV8F72QqyFwRgekL5vKEEn4mA5U1ZBahMKVa1N9Ts0C5XV8NXqtZ0hcVZxo REes9bBubILkWY29DNmPJxX86z+wHUFeXYba5XCjQx9ToUVkxnMQJDeNdkGKtsjTP15D O9gw== X-Gm-Message-State: AHQUAuaNXZ+JYiTsP3sWzIXjzbNKeM8rrxpLpxIDo+TdOslsQ/ko79to WyU2oyCwUUI03ysN5UG++OSX4ATZUGs= X-Google-Smtp-Source: AHgI3Ibg3eZKdnqxWSLtRWmaqU74U/VNmDbhcBElleMSknLYKFYXy31u49NSaljjHvgFzMpGUsvJwg== X-Received: by 2002:aa7:838b:: with SMTP id u11mr27011617pfm.254.1549847338944; Sun, 10 Feb 2019 17:08:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:24 -0800 Message-Id: <20190211010829.29869-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v2 21/26] target/arm: Cache the Tagged bit for a page in MemTxAttrs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This "bit" is a particular value of the page's MemAttr. Signed-off-by: Richard Henderson --- target/arm/helper.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index a3ad5bc54e..3d7a51f8a2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10719,6 +10719,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, ta= rget_ulong address, uint64_t descaddrmask; bool aarch64 =3D arm_el_is_aa64(env, el); bool guarded =3D false; + uint8_t memattr; =20 /* TODO: * This code does not handle the different format TCR for VTCR_EL2. @@ -10949,17 +10950,21 @@ static bool get_phys_addr_lpae(CPUARMState *env, = target_ulong address, txattrs->target_tlb_bit0 =3D true; } =20 + if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { + memattr =3D convert_stage2_attrs(env, extract32(attrs, 0, 4)); + } else { + /* Index into MAIR registers for cache attributes */ + uint64_t mair =3D env->cp15.mair_el[el]; + memattr =3D extract64(mair, extract32(attrs, 0, 3) * 8, 8); + } + + /* When in aarch64 mode, and MTE is enabled, remember Tagged in IOTLB.= */ + if (aarch64 && memattr =3D=3D 0xf0 && cpu_isar_feature(aa64_mte, cpu))= { + txattrs->target_tlb_bit1 =3D true; + } + if (cacheattrs !=3D NULL) { - if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { - cacheattrs->attrs =3D convert_stage2_attrs(env, - extract32(attrs, 0, 4= )); - } else { - /* Index into MAIR registers for cache attributes */ - uint8_t attrindx =3D extract32(attrs, 0, 3); - uint64_t mair =3D env->cp15.mair_el[regime_el(env, mmu_idx)]; - assert(attrindx <=3D 7); - cacheattrs->attrs =3D extract64(mair, attrindx * 8, 8); - } + cacheattrs->attrs =3D memattr; cacheattrs->shareability =3D extract32(attrs, 6, 2); } =20 --=20 2.17.2 From nobody Fri May 3 10:47:40 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549848488805324.95531718595055; Sun, 10 Feb 2019 17:28:08 -0800 (PST) Received: from localhost ([127.0.0.1]:42370 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt0O8-0003R8-LK for importer@patchew.org; Sun, 10 Feb 2019 20:28:00 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37593) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt05u-0005w4-Ky for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gt05s-00007j-7u for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:10 -0500 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]:46232) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gt05r-0008QC-SH for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:08 -0500 Received: by mail-pl1-x629.google.com with SMTP id o6so4487584pls.13 for ; Sun, 10 Feb 2019 17:09:01 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.08.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:08:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=A8TAMIXN+69/Jk9cvH3CNk1W0843jdUBpea8zUdjfM0=; b=HNZ4pg/PDfGoe5B3SGC/gSoE9xmvAcX6RtnGXeG6dIUZe6/tEi1qhpLbMA05hfW6iI DHi36z73E7gdvDW7rFuTTfBQMzR9iimUzFkhWeid8ajzLHODHxnULMzaaTJi67IzhFJL Tt+5F4iAudruoBEIshwoKRnNBonFOUzpxIo2gys5KFK8PETcx59l3T394MtnVdv2UgH7 k6Xv7AGUhMIS9+ZcS4R70TW7W+WaEfVLrg4ZuxoyAM1RlItaf7ETXVzdOttioLU13Hdv XTC46PSbz60JQN31pMjE0kSAIuYxBebjGlIp7JeYOaMXCy0nn5DpAiiZboEuO3Wog9G5 YCvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=A8TAMIXN+69/Jk9cvH3CNk1W0843jdUBpea8zUdjfM0=; b=B684Ho0znS8jbVTJC8mTygmzUsAs7SVgQ7LYXAep+EpmYItHOcB4E8bXGL0GiCAx0Z vSR1I9rOncR2bt8xHRDNFb6RfmYaLCx6bsDfb9pqzncnyNcFhitlXhoiuBztHICZxhh8 Q4svOgsHWrj87HD8BGpa3BxeUlZq+xa1adv/Mr1BcvZkCylFA6DCAcx3vQnj9Up9qB5v 5p3t8+ySDppUYu7jCSwCs8GD7VnMMsszVOC00bYnhRaKK58RhF+KXIFzz7dSXUb9cnU0 zVqARCEJJJzBBdQeE9ah3W+cC3cFZ0uskOqwemeFNl1XPjSjchWZW5HI7kO0j/IlaoAh 6xNg== X-Gm-Message-State: AHQUAubjazOwCY4/34YBziV+P91DPC/LaQyhMsyezb6fK6jZx1pO4c5v TQT8jzjHMqos9Ndto2B5jnMAvX9vjac= X-Google-Smtp-Source: AHgI3IajHKR4XXUHLrNUBcJGLUQKLdLtaClttC0oDfehRIK0qZK4CSVM/JdvqbEwKCWt41mp3g+FMg== X-Received: by 2002:a17:902:9a84:: with SMTP id w4mr26302882plp.283.1549847340230; Sun, 10 Feb 2019 17:09:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:25 -0800 Message-Id: <20190211010829.29869-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::629 Subject: [Qemu-devel] [PATCH v2 22/26] target/arm: Create tagged ram when MTE is enabled X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/cpu.h | 4 ++++ hw/arm/virt.c | 33 +++++++++++++++++++++++++++++++++ target/arm/cpu.c | 21 ++++++++++++++++++--- 3 files changed, 55 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ca32939483..2626af4a9c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -768,6 +768,9 @@ struct ARMCPU { /* MemoryRegion to use for secure physical accesses */ MemoryRegion *secure_memory; =20 + /* MemoryRegion to use for allocation tag accesses */ + MemoryRegion *tag_memory; + /* For v8M, pointer to the IDAU interface provided by board/SoC */ Object *idau; =20 @@ -2850,6 +2853,7 @@ int cpu_mmu_index(CPUARMState *env, bool ifetch); typedef enum ARMASIdx { ARMASIdx_NS =3D 0, ARMASIdx_S =3D 1, + ARMASIdx_TAG =3D 2, } ARMASIdx; =20 /* Return the Exception Level targeted by debug exceptions. */ diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 99c2b6e60d..dccd1345a1 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1260,6 +1260,21 @@ static void create_secure_ram(VirtMachineState *vms, g_free(nodename); } =20 +static void create_tag_ram(VirtMachineState *vms, MachineState *machine, + MemoryRegion *tag_sysmem) +{ + MemoryRegion *tagram =3D g_new(MemoryRegion, 1); + hwaddr base =3D vms->memmap[VIRT_MEM].base / 32; + hwaddr size =3D machine->ram_size / 32; + + memory_region_init_ram(tagram, NULL, "mach-virt.tag", size, &error_fat= al); + memory_region_add_subregion(tag_sysmem, base, tagram); + + /* ??? Do we really need an fdt entry, or is MemTag enabled sufficient= . */ + /* ??? We appear to need secure tag mem to go with secure mem. */ + /* ??? Does that imply we need a fourth address space? */ +} + static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) { const VirtMachineState *board =3D container_of(binfo, VirtMachineState, @@ -1362,6 +1377,7 @@ static void machvirt_init(MachineState *machine) qemu_irq pic[NUM_IRQS]; MemoryRegion *sysmem =3D get_system_memory(); MemoryRegion *secure_sysmem =3D NULL; + MemoryRegion *tag_sysmem =3D NULL; int n, virt_max_cpus; MemoryRegion *ram =3D g_new(MemoryRegion, 1); bool firmware_loaded =3D bios_name || drive_get(IF_PFLASH, 0, 0); @@ -1518,6 +1534,20 @@ static void machvirt_init(MachineState *machine) "secure-memory", &error_abort); } =20 + /* + * The cpu adds the property iff MemTag is supported. + * If it is, we must allocate the ram to back that up. + */ + if (object_property_find(cpuobj, "tag-memory", NULL)) { + if (!tag_sysmem) { + tag_sysmem =3D g_new(MemoryRegion, 1); + memory_region_init(tag_sysmem, OBJECT(machine), + "tag-memory", UINT64_MAX / 32); + } + object_property_set_link(cpuobj, OBJECT(tag_sysmem), + "tag-memory", &error_abort); + } + object_property_set_bool(cpuobj, true, "realized", &error_fatal); object_unref(cpuobj); } @@ -1540,6 +1570,9 @@ static void machvirt_init(MachineState *machine) create_secure_ram(vms, secure_sysmem); create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hd(1= )); } + if (tag_sysmem) { + create_tag_ram(vms, machine, tag_sysmem); + } =20 vms->highmem_ecam &=3D vms->highmem && (!firmware_loaded || aarch64); =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index edf6e0e1f1..decf95de3e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -851,6 +851,18 @@ void arm_cpu_post_init(Object *obj) =20 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, &error_abort); + +#ifndef CONFIG_USER_ONLY + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && + cpu_isar_feature(aa64_mte, cpu)) { + object_property_add_link(obj, "tag-memory", + TYPE_MEMORY_REGION, + (Object **)&cpu->tag_memory, + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG, + &error_abort); + } +#endif } =20 static void arm_cpu_finalizefn(Object *obj) @@ -1164,16 +1176,19 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) init_cpreg_list(cpu); =20 #ifndef CONFIG_USER_ONLY + cs->num_ases =3D 1; if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { cs->num_ases =3D 2; - if (!cpu->secure_memory) { cpu->secure_memory =3D cs->memory; } cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", cpu->secure_memory); - } else { - cs->num_ases =3D 1; + } + if (cpu->tag_memory !=3D NULL) { + cs->num_ases =3D 3; + cpu_address_space_init(cs, ARMASIdx_TAG, "cpu-tag-memory", + cpu->tag_memory); } cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); =20 --=20 2.17.2 From nobody Fri May 3 10:47:40 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549848758830258.69227057719604; Sun, 10 Feb 2019 17:32:38 -0800 (PST) Received: from localhost ([127.0.0.1]:42446 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt0SZ-00074C-RY for importer@patchew.org; Sun, 10 Feb 2019 20:32:35 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37687) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt05w-0005yF-Ol for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gt05t-0000AQ-3g for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:12 -0500 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:40716) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gt05s-0008SA-Lv for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:08 -0500 Received: by mail-pl1-x644.google.com with SMTP id bj4so1844967plb.7 for ; Sun, 10 Feb 2019 17:09:02 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.09.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:09:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ymaxv9zbXnQNBLMQJfCDWxjmtO7rlV16zaXGdm7o62o=; b=kNaBYver4RNr8omJ21XVp6ZSme5iGL970KWHu2CoT+glEsMAkV6h5hIRVJ7kbVkM3S viIp5DXCvmMY1hIisoEvU7VKw5hYuUtAM14aFV+ws3Fv2C6/3rM0B1GLKSB0wuxEhlrk MEM+fCaDhxmyv/5M2WOE4mNa4H1WlbzXpfOtOWagL3Ya5YiYX2dMNfDUWIJ9HOeCB15L SWiUDgSdvVZ04ZJtaefPTTv7IMRsy75jOL/YFfe/fhziGTuP1/+RVFlf8CAA9pVNXUy7 mtXE9jsqsqkkokDUkEHuTUsqu115+UyC8ZdDIomeWJeseAEv7JtAlp7RZoi+poGdHfde zsPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ymaxv9zbXnQNBLMQJfCDWxjmtO7rlV16zaXGdm7o62o=; b=Z4Is3wndvKa6CMNmQnicxXU7WYsC6kp1h14BdKfJJpQwoVVwFHMzCQl3mlWT2xLctf vWm8DortLFYc4r15/f7wWN/KDbihu2sL38AHamWpGFcX6jlhFrnb23t8lseewJrrxSsM xhRUYoj5tdz1HdGhcTnm981+zb0SP4aeQO+XUqKy7HxhzGR6bOfC/qrpCNnu5TwWEJaM LEsqosqFerULiqtUcst/awVJ2hhpWnHv3WOXlceulOmCIoxCVRGbxGYxhDU0HjFt9h5o Guf769YKUAyZqvPyvtmAnDvIzJmBiuPe8xN2JHGpDALpb8YoGHuWwx/3uso+E4+FsjbD srVQ== X-Gm-Message-State: AHQUAubKMQnockvYj/AGZvknzqFvOnOQbNILvfBfieLlhREe3OFdK4dx PmRi686Mvsl0vCNziBkuZeuVAr0fGm8= X-Google-Smtp-Source: AHgI3IZPugcCnorNj5Ut3k4V/teyRRrbd7QINsP3rGTGU2VR78lMsloKq+5ADSlWRYU0oWJFLhWAOQ== X-Received: by 2002:a17:902:bd0b:: with SMTP id p11mr35123162pls.259.1549847341514; Sun, 10 Feb 2019 17:09:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:26 -0800 Message-Id: <20190211010829.29869-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v2 23/26] target/arm: Add allocation tag storage for user mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Control this with x-tagged-pages, which is off by default. The limitation to non-shared pages is not part of a future kernel API, but a limitation of linux-user not being able to map virtual pages back to physical pages. Signed-off-by: Richard Henderson --- v2: Add the x-tagged-pages cpu property --- target/arm/cpu.h | 1 + target/arm/cpu64.c | 18 ++++++++++++++++++ target/arm/mte_helper.c | 37 +++++++++++++++++++++++++++++++++++++ 3 files changed, 56 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2626af4a9c..ec5ddfbacc 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -910,6 +910,7 @@ struct ARMCPU { =20 #ifdef CONFIG_USER_ONLY bool guarded_pages; + bool tagged_pages; #endif =20 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index c5675fe7d1..53a7d92c95 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -293,6 +293,18 @@ static void aarch64_cpu_set_guarded_pages(Object *obj,= bool val, Error **errp) ARMCPU *cpu =3D ARM_CPU(obj); cpu->guarded_pages =3D val; } + +static bool aarch64_cpu_get_tagged_pages(Object *obj, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + return cpu->tagged_pages; +} + +static void aarch64_cpu_set_tagged_pages(Object *obj, bool val, Error **er= rp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + cpu->tagged_pages =3D val; +} #endif =20 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this ho= st); @@ -380,6 +392,12 @@ static void aarch64_max_initfn(Object *obj) aarch64_cpu_set_guarded_pages, NULL); object_property_set_description(obj, "x-guarded-pages", "Set on/off GuardPage bit for all pages", NULL); + + object_property_add_bool(obj, "x-tagged-pages", + aarch64_cpu_get_tagged_pages, + aarch64_cpu_set_tagged_pages, NULL); + object_property_set_description(obj, "x-tagged-pages", + "Set on/off MemAttr Tagged for all pages", NULL); #endif =20 cpu->sve_max_vq =3D ARM_MAX_VQ; diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 93f7cccee2..ad2902472d 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -53,8 +53,45 @@ static uint64_t strip_tbi(CPUARMState *env, uint64_t ptr) static uint8_t *allocation_tag_mem(CPUARMState *env, uint64_t ptr, bool write, uintptr_t ra) { +#ifdef CONFIG_USER_ONLY + ARMCPU *cpu =3D arm_env_get_cpu(env); + uint64_t clean_ptr =3D strip_tbi(env, ptr); + uint8_t *tags; + uintptr_t index; + int flags; + + flags =3D page_get_flags(clean_ptr); + + if (!(flags & PAGE_VALID) || !(flags & (write ? PAGE_WRITE : PAGE_READ= ))) { + /* SIGSEGV */ + env->exception.vaddress =3D ptr; + cpu_restore_state(CPU(cpu), ra, true); + raise_exception(env, EXCP_DATA_ABORT, 0, 1); + } + + if (!cpu->tagged_pages) { + /* Tag storage is disabled. */ + return NULL; + } + if (flags & PAGE_SHARED) { + /* There may be multiple mappings; pretend not implemented. */ + return NULL; + } + + tags =3D page_get_target_data(clean_ptr); + if (tags =3D=3D NULL) { + size_t alloc_size =3D TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1); + tags =3D page_alloc_target_data(clean_ptr, alloc_size); + assert(tags !=3D NULL); + } + + index =3D extract32(clean_ptr, LOG2_TAG_GRANULE + 1, + TARGET_PAGE_BITS - LOG2_TAG_GRANULE - 1); + return tags + index; +#else /* Tag storage not implemented. */ return NULL; +#endif } =20 static int get_allocation_tag(CPUARMState *env, uint64_t ptr, uintptr_t ra) --=20 2.17.2 From nobody Fri May 3 10:47:40 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549847876614651.8826059507046; Sun, 10 Feb 2019 17:17:56 -0800 (PST) Received: from localhost ([127.0.0.1]:42191 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt0EL-0004B6-IN for importer@patchew.org; Sun, 10 Feb 2019 20:17:53 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37689) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt05w-0005yH-Oo for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gt05s-00008Z-EZ for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:12 -0500 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:38628) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gt05s-0008T0-1d for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:08 -0500 Received: by mail-pl1-x644.google.com with SMTP id e5so4510889plb.5 for ; Sun, 10 Feb 2019 17:09:04 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.09.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:09:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MvaIKsOMPQ7hbRMjemvvtwhP7sBFQA2Gv3Y/7+kAWX0=; b=OeNmJRWYjbAAGxeF8eAGRyomWMZYqMo+HpCnjZC8mVnI1fk6ZT++0jvc1JfCTJtr7M 132XkFBNjBWB8ebtPsHJGt7ZZlua+eH7poE9WcjF16J+I027dpq3TnOYd1m5J02oz7KR zxaKtDgpCdxK9auAw3o6eKA2F/OwKi3n/+0loEh90XOyITjSQ6Z3Qel/8tvNMuCLo1EK 2Ne1JHa2YenYpceDkhH1ynZ4O+MdGLQ6gKbTfI80ym4ZKe+G85YQqqH6jN1gxZd3FH1c KUew5QOI+/nYCPOj4Iyj90udM56Cfs5f3oh3lCkuA6AtwXexzeRq1FDBiVYu2B/OC5Xp lcoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MvaIKsOMPQ7hbRMjemvvtwhP7sBFQA2Gv3Y/7+kAWX0=; b=Sr3Sw5TMdyidxyydsFujINVAJ8NyjzdSb2YcLPrDN7lLr5NKDgk8l2KFzNrUpj7/jY LyED8JImwVaXqbnBKnKC64rH4Vfxod/jdFc6JbdUFcpsJXRE82toOzjnnzXJTee3Y6tV ifSqcmJ7w10C9K4vTiQysAvTRh//5T+Fu+/itBMbJ8mY4vuOXFkygML3wDB/sNenC+fu dEv1tjRG0Wq/8/aa8P7DMG5TsYFyCOpkSwFUfAl4TbghVmVPBA0guk4JW0MNB4+5OKHz e7hua+jnD7hZLE0EVgMXnJXunl1jlM3xx3z5DgeyeExVHOScP2w8pFN8/QC4d/OzGTfb 7GDA== X-Gm-Message-State: AHQUAuaeZpWKTc0GdRyr085s2+RaENp3tA5ea8mhzwv7aOqXZ0G2QHWx V8PqpTeOzuC927XfyEJQei1svBuiVok= X-Google-Smtp-Source: AHgI3Ib/VKFIeXTGy37mTlIPaMVnJcOS2AptLvtyfjpKIZoNA5lzE/nzfMk+WU5OWzFG/WOT74INDQ== X-Received: by 2002:a17:902:7608:: with SMTP id k8mr29078056pll.245.1549847342745; Sun, 10 Feb 2019 17:09:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:27 -0800 Message-Id: <20190211010829.29869-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v2 24/26] target/arm: Add allocation tag storage for system mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 96 +++++++++++++++++++++++++++++++++++++---- 1 file changed, 87 insertions(+), 9 deletions(-) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index ad2902472d..3abed62018 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -53,19 +53,19 @@ static uint64_t strip_tbi(CPUARMState *env, uint64_t pt= r) static uint8_t *allocation_tag_mem(CPUARMState *env, uint64_t ptr, bool write, uintptr_t ra) { -#ifdef CONFIG_USER_ONLY ARMCPU *cpu =3D arm_env_get_cpu(env); + CPUState *cs =3D CPU(cpu); uint64_t clean_ptr =3D strip_tbi(env, ptr); uint8_t *tags; uintptr_t index; - int flags; =20 - flags =3D page_get_flags(clean_ptr); +#ifdef CONFIG_USER_ONLY + int flags =3D page_get_flags(clean_ptr); =20 if (!(flags & PAGE_VALID) || !(flags & (write ? PAGE_WRITE : PAGE_READ= ))) { /* SIGSEGV */ env->exception.vaddress =3D ptr; - cpu_restore_state(CPU(cpu), ra, true); + cpu_restore_state(cs, ra, true); raise_exception(env, EXCP_DATA_ABORT, 0, 1); } =20 @@ -82,16 +82,94 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, ui= nt64_t ptr, if (tags =3D=3D NULL) { size_t alloc_size =3D TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1); tags =3D page_alloc_target_data(clean_ptr, alloc_size); - assert(tags !=3D NULL); + } +#else + int mmu_idx; + AddressSpace *as; + CPUTLBEntry *te; + CPUIOTLBEntry *iotlbentry; + MemoryRegionSection *section; + MemoryRegion *mr; + FlatView *fv; + hwaddr physaddr, tag_physaddr, tag_len, xlat; + + /* + * Find the TLB entry for this access. + * As a side effect, this also raises an exception for invalid access. + */ + mmu_idx =3D cpu_mmu_index(env, false); + index =3D tlb_index(env, mmu_idx, clean_ptr); + te =3D tlb_entry(env, mmu_idx, clean_ptr); + if (!tlb_hit(write ? tlb_addr_write(te) : te->addr_read, clean_ptr)) { + /* ??? Expose VICTIM_TLB_HIT from accel/tcg/cputlb.c. */ + tlb_fill(cs, ptr, 16, write ? MMU_DATA_STORE : MMU_DATA_LOAD, + mmu_idx, ra); + index =3D tlb_index(env, mmu_idx, clean_ptr); + te =3D tlb_entry(env, mmu_idx, clean_ptr); } =20 + /* If the virtual page MemAttr !=3D Tagged, nothing to do. */ + iotlbentry =3D &env->iotlb[mmu_idx][index]; + if (!iotlbentry->attrs.target_tlb_bit1) { + return NULL; + } + + /* If the board did not allocate tag memory, nothing to do. */ + as =3D cpu_get_address_space(cs, ARMASIdx_TAG); + if (!as) { + return NULL; + } + + /* Find the physical address for the virtual access. */ + section =3D iotlb_to_section(cs, iotlbentry->addr, iotlbentry->attrs); + physaddr =3D ((iotlbentry->addr & TARGET_PAGE_MASK) + clean_ptr + + section->offset_within_address_space + - section->offset_within_region); + + /* Convert to the physical address in tag space. */ + tag_physaddr =3D physaddr >> (LOG2_TAG_GRANULE + 1); + tag_len =3D TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1); + + /* + * Find the tag physical address within the tag address space. + * + * ??? Create a new mmu_idx to cache the rest of this. + * + * ??? If we were assured of exactly one block of normal ram, + * and thus exactly one block of tag ram, then we could validate + * section->mr as ram, use the section offset vs cpu->tag_memory, + * and finish with memory_region_get_ram_ptr. + */ + rcu_read_lock(); + fv =3D address_space_to_flatview(as); + mr =3D flatview_translate(fv, tag_physaddr, &xlat, &tag_len, + write, MEMTXATTRS_UNSPECIFIED); + if (!memory_access_is_direct(mr, write)) { + /* + * This would seem to imply that the guest has marked a + * virtual page as Tagged when the physical page is not RAM. + * Should this raise some sort of bus error? + */ + rcu_read_unlock(); + qemu_log_mask(LOG_GUEST_ERROR, "Tagged virtual page 0x%" PRIx64 + " maps to physical page 0x%" PRIx64 " without RAM\n", + clean_ptr, physaddr); + return NULL; + } + rcu_read_unlock(); + + /* The board should have created tag ram sized correctly. */ + assert(tag_len =3D=3D TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1)); + + /* FIXME: Mark the tag page dirty for migration. */ + + tags =3D qemu_map_ram_ptr(mr->ram_block, xlat); +#endif + + assert(tags !=3D NULL); index =3D extract32(clean_ptr, LOG2_TAG_GRANULE + 1, TARGET_PAGE_BITS - LOG2_TAG_GRANULE - 1); return tags + index; -#else - /* Tag storage not implemented. */ - return NULL; -#endif } =20 static int get_allocation_tag(CPUARMState *env, uint64_t ptr, uintptr_t ra) --=20 2.17.2 From nobody Fri May 3 10:47:40 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549848136367269.6770112529632; Sun, 10 Feb 2019 17:22:16 -0800 (PST) Received: from localhost ([127.0.0.1]:42276 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt0IU-0007MP-9D for importer@patchew.org; Sun, 10 Feb 2019 20:22:10 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37620) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt05v-0005ws-Lj for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gt05s-00008k-HK for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:11 -0500 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:38626) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gt05s-0008Ug-74 for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:08 -0500 Received: by mail-pl1-x641.google.com with SMTP id e5so4510915plb.5 for ; Sun, 10 Feb 2019 17:09:05 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id g14sm17177630pfg.27.2019.02.10.17.09.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 10 Feb 2019 17:09:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=g7oNh1d8VWGEQw+YCuZLsLZ9OlLSdLVyb8nPu7OZ0AM=; b=Mou86ucXOZrCzuhlxiH5ZHCEHc+smQK99AsvZlKAD1V3+HoDfRgEI0uCVAftMOKJfq XJROt97HxcPVvCL2EhD/85T6j8PNjwxX9YBQ1t9J2DAY56izUjkQMbRMNypDJH3Ov28u NYBgNQnr8oL/sf9FwRWpSTFsuEd4IhkzoZwV0Q6DbrGAbtnn9zaiNUYkEBaEbp2dnwXk LDgAFZWWibNOToeBbE+lJnIy3tjKq9+Ai6xIPSSekLLSj8E6FeJwf3cfROACssmQk2Pb I2ACk/oRF6R5AYIh1gQ23wYNkfmZaWTqVQfGktPkr8pt4rOkzbKP+S5Xf2AD2nj8/h34 awjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=g7oNh1d8VWGEQw+YCuZLsLZ9OlLSdLVyb8nPu7OZ0AM=; b=SqmX/AeoDJXhTLoBsEY5uvd7sgM/fYXL3HWpeP/nh30QK3UHzmr4Rmno/U5FOWp7rJ Xedbdc4NfEoygSADWFmGFbfkk8mex9BBk6iR9r0Czvrh2jLsklBd2i4gP7cit9FQ2Inl PEyoUhedYnj+HRj636MQkdveAbOXwg3IYnvx2R57gQVxXY/1dXdWFaMsoDdYvOST77IT vfRyh9EyWnPqU/3WyhwNcPCrHmrrWYU8PNr9Z5N5M4zzOv+VA/XOTWxqi6T8u77zECgy HGt4LarHXGWs3rFn8qpWhVpAOBdv+iwnvbdO0zCtg9zY7M51Wws6FZwo5QhPB5BVLmlw eG7A== X-Gm-Message-State: AHQUAuatroFg5toBXCcz/qVVZaQhUYFf8EChClt6ua566Pks8EPVw47V RFjajODWETmVKpkzyAz5fINicbBiPAo= X-Google-Smtp-Source: AHgI3IYD0/hB8ZDUDOPN5h3YW1uuFxYpDZfnfEJlvC0V89KYQAYI0G8N4eKiDNByUqxJVyYcuD/3cQ== X-Received: by 2002:a17:902:280b:: with SMTP id e11mr34975123plb.269.1549847343970; Sun, 10 Feb 2019 17:09:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 17:08:28 -0800 Message-Id: <20190211010829.29869-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v2 25/26] target/arm: Enable MTE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/cpu.c | 10 ++++++++++ target/arm/cpu64.c | 1 + 2 files changed, 11 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index decf95de3e..a5599ae19f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -206,6 +206,16 @@ static void arm_cpu_reset(CPUState *s) * make no difference to the user-level emulation. */ env->cp15.tcr_el[1].raw_tcr =3D (3ULL << 37); + /* Enable MTE allocation tags. */ + env->cp15.hcr_el2 |=3D HCR_ATA; + env->cp15.scr_el3 |=3D SCR_ATA; + env->cp15.sctlr_el[1] |=3D SCTLR_ATA0; + /* Enable synchronous tag check failures. */ + env->cp15.sctlr_el[1] |=3D 1ull << 38; +#ifdef TARGET_AARCH64 + /* Set MTE seed to non-zero value, otherwise RandomTag fails. */ + env->cp15.rgsr_el1 =3D 0x123400; +#endif #else /* Reset into the highest available EL */ if (arm_feature(env, ARM_FEATURE_EL3)) { diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 53a7d92c95..7bd761b8f5 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -352,6 +352,7 @@ static void aarch64_max_initfn(Object *obj) =20 t =3D cpu->isar.id_aa64pfr1; t =3D FIELD_DP64(t, ID_AA64PFR1, BT, 1); + t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 2); cpu->isar.id_aa64pfr1 =3D t; =20 t =3D cpu->isar.id_aa64mmfr1; --=20 2.17.2 From nobody Fri May 3 10:47:40 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549847698618845.933276697895; Sun, 10 Feb 2019 17:14:58 -0800 (PST) Received: from localhost ([127.0.0.1]:42135 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt0BT-0001nJ-IZ for importer@patchew.org; Sun, 10 Feb 2019 20:14:55 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37656) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt05w-0005xT-8k for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gt05t-0000Bj-AV for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:12 -0500 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:42318) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gt05s-0008WK-Tl for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:09 -0500 Received: by mail-pl1-x644.google.com with SMTP id s1so4492707plp.9 for ; Sun, 10 Feb 2019 17:09:06 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v2 26/26] tests/tcg/aarch64: Add mte smoke tests X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tests/tcg/aarch64/mte-1.c | 27 +++++++++++++++++++++ tests/tcg/aarch64/mte-2.c | 39 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 4 ++++ 3 files changed, 70 insertions(+) create mode 100644 tests/tcg/aarch64/mte-1.c create mode 100644 tests/tcg/aarch64/mte-2.c diff --git a/tests/tcg/aarch64/mte-1.c b/tests/tcg/aarch64/mte-1.c new file mode 100644 index 0000000000..740bf506f1 --- /dev/null +++ b/tests/tcg/aarch64/mte-1.c @@ -0,0 +1,27 @@ +/* + * Memory tagging, basic pass cases. + */ + +#include + +asm(".arch armv8.5-a+memtag"); + +int data[16 / sizeof(int)] __attribute__((aligned(16))); + +int main(int ac, char **av) +{ + int *p0 =3D data; + int *p1, *p2; + long c; + + asm("irg %0,%1,%2" : "=3Dr"(p1) : "r"(p0), "r"(1)); + assert(p1 !=3D p0); + asm("subp %0,%1,%2" : "=3Dr"(c) : "r"(p0), "r"(p1)); + assert(c =3D=3D 0); + + asm("stg [%0]" : : "r"(p1)); + asm("ldg %0, [%1]" : "=3Dr"(p2) : "r"(p0)); + assert(p1 =3D=3D p2); + + return 0; +} diff --git a/tests/tcg/aarch64/mte-2.c b/tests/tcg/aarch64/mte-2.c new file mode 100644 index 0000000000..4d2004ab41 --- /dev/null +++ b/tests/tcg/aarch64/mte-2.c @@ -0,0 +1,39 @@ +/* + * Memory tagging, basic fail cases. + */ + +#include +#include +#include + +asm(".arch armv8.5-a+memtag"); + +int data[16 / sizeof(int)] __attribute__((aligned(16))); + +void pass(int sig) +{ + exit(0); +} + +int main(int ac, char **av) +{ + int *p0 =3D data; + int *p1, *p2; + long excl =3D 1; + + /* Create two differently tagged pointers. */ + asm("irg %0,%1,%2" : "=3Dr"(p1) : "r"(p0), "r"(excl)); + asm("gmi %0,%1,%0" : "+r"(excl) : "r" (p1)); + assert(excl !=3D 1); + asm("irg %0,%1,%2" : "=3Dr"(p2) : "r"(p0), "r"(excl)); + assert(p1 !=3D p2); + + /* Store the tag from the first pointer. */ + asm("stg [%0]" : : "r"(p1)); + + *p1 =3D 0; + signal(SIGSEGV, pass); + *p2 =3D 0; + + assert(0); +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile= .target index 55420aeea6..614dfcd14d 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -22,4 +22,8 @@ AARCH64_TESTS +=3D bti-1 bti-1: LDFLAGS +=3D -nostartfiles -nodefaultlibs -nostdlib run-bti-1: QEMU +=3D -cpu max,x-guarded-pages=3Don =20 +AARCH64_TESTS +=3D mte-1 mte-2 +mte-%: CFLAGS +=3D -O -g +run-mte-%: QEMU +=3D -cpu max,x-tagged-pages=3Don + TESTS:=3D$(AARCH64_TESTS) --=20 2.17.2