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[2001:470:27:1fa::2]) by smtp.gmail.com with ESMTPSA id j82sm1945710lfe.13.2019.02.10.16.14.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 10 Feb 2019 16:14:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=UQronJsZ8JEnk4XJzI/d92gpAXv79Lm4s4FOR4ZKtEo=; b=ez+8UhE5dtJ6pakzu5qR6VLjZUrQ295zjgv5Vwehd0ueaPvKrLChig4SuTK/QjDzbV 8GBKzWCwd+JOzbZ4fwHixhNiVS2TE3DkVoRJXEs0He5RGxSyyWJKJvW9Kf6W6iUxvM4C 3dVgSrebjpjet5RB06rO9re8ntEaLWzXU3YSa1lLmuduwDW9/5g+8hysJTh0emqGXhuM wgjNiL92s/GOyioVImjfVA7pogvwBbew3J6JL+H8sFNFjK7BSLBO+HP8GooiOv7cPNnE xx0Y4NLxRv1c9PWGhr8Utk+VpGkkwLNdbhtSCIa3yTQvYAwuGCwMZckV/oKsh3AqTWx+ iRkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=UQronJsZ8JEnk4XJzI/d92gpAXv79Lm4s4FOR4ZKtEo=; b=IdAzc4Zy39kuTcxrJy726i1s9nqVxBjqpAxxpqak1XFKcJbw8twLUIb03pLiJOJyWD wyOmZZ+UnET65mv8103gYVTgbqp2A/d5+4RInJabwOiRshzoLMjZfy+m+4cZ90fA22sr 3FEsMyl1ozxQPy0Wdp2eOSG5050aqs4RToF0ANHRGLx/mb2U4HwikjK/5yiENpn2Aunk yUxHRklhH7EOOB5nUppHnsqb9AFOHQxaDWzXL0UBKJSNx4u5CermgqCDtpzIXqFigDLG mPppDiZh2bQ19Dlt8dx53R+9EELIp1f1Y4VMroBL/aQeUYn6/08l8Ci99fJ7P9V4fe3O SPSQ== X-Gm-Message-State: AHQUAuZY0ecG4DPMI2orjUXfq1/5YPVeT26SwtENwxV5drvJL8YeX2Is jkhbmrPx+mT00hjJUWkRLLnkI2E9 X-Google-Smtp-Source: AHgI3Ia0VgMsJgxXep2GFEBAgbjfgNE8LbE8gh4SxF1ENyk4amviqVOdZQqpKZqa5j/6Gk6gptgI7Q== X-Received: by 2002:a19:4851:: with SMTP id v78mr15795037lfa.98.1549844077093; Sun, 10 Feb 2019 16:14:37 -0800 (PST) From: Max Filippov To: qemu-devel@nongnu.org Date: Sun, 10 Feb 2019 16:14:24 -0800 Message-Id: <20190211001424.18776-1-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.11.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::143 Subject: [Qemu-devel] [PATCH] target/xtensa: don't specify windowed registers manually X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Use libisa to extract whether opcode uses windowed registers and construct mask based on that. This only leaves special case for the 'entry' opcode, as it needs to probe a register dynamically. Signed-off-by: Max Filippov --- target/xtensa/cpu.h | 2 +- target/xtensa/helper.c | 1 + target/xtensa/translate.c | 493 +-----------------------------------------= ---- 3 files changed, 12 insertions(+), 484 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index b665bfc0068a..f1861244720e 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -380,7 +380,6 @@ typedef struct XtensaOpcodeOps { XtensaOpcodeUintTest test_overflow; const uint32_t *par; uint32_t op_flags; - uint32_t windowed_register_op; uint32_t coprocessor; } XtensaOpcodeOps; =20 @@ -438,6 +437,7 @@ struct XtensaConfig { xtensa_isa isa; XtensaOpcodeOps **opcode_ops; const XtensaOpcodeTranslators **opcode_translators; + xtensa_regfile a_regfile; =20 uint32_t clock_freq_khz; =20 diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index bcf2f20d4858..6cf1dbb8a69b 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -88,6 +88,7 @@ static void init_libisa(XtensaConfig *config) #endif config->opcode_ops[i] =3D ops; } + config->a_regfile =3D xtensa_regfile_lookup(config->isa, "AR"); } =20 void xtensa_finalize_config(XtensaConfig *config) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index d1e9f59b31bd..6e4f0ad44c80 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -916,6 +916,16 @@ static void disas_xtensa_insn(CPUXtensaState *env, Dis= asContext *dc) opnds =3D xtensa_opcode_num_operands(isa, opc); =20 for (opnd =3D vopnd =3D 0; opnd < opnds; ++opnd) { + if (xtensa_operand_is_register(isa, opc, opnd) && + xtensa_operand_regfile(isa, opc, opnd) =3D=3D + dc->config->a_regfile) { + uint32_t v; + + xtensa_operand_get_field(isa, opc, opnd, fmt, slot, + dc->slotbuf, &v); + xtensa_operand_decode(isa, opc, opnd, &v); + windowed_register |=3D 1u << v; + } if (xtensa_operand_is_visible(isa, opc, opnd)) { uint32_t v; =20 @@ -952,16 +962,6 @@ static void disas_xtensa_insn(CPUXtensaState *env, Dis= asContext *dc) if (ops->test_overflow) { windowed_register |=3D ops->test_overflow(dc, arg, ops->par); } - if (ops->windowed_register_op) { - uint32_t reg_opnd =3D ops->windowed_register_op; - - while (reg_opnd) { - unsigned i =3D ctz32(reg_opnd); - - windowed_register |=3D 1 << arg[i]; - reg_opnd ^=3D 1 << i; - } - } coprocessor |=3D ops->coprocessor; } =20 @@ -1474,12 +1474,6 @@ static void translate_call0(DisasContext *dc, const = uint32_t arg[], gen_jumpi(dc, arg[0], 0); } =20 -static uint32_t test_overflow_callw(DisasContext *dc, const uint32_t arg[], - const uint32_t par[]) -{ - return 1 << (par[0] * 4); -} - static void translate_callw(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { @@ -2435,42 +2429,33 @@ static const XtensaOpcodeOps core_ops[] =3D { { .name =3D "abs", .translate =3D translate_abs, - .windowed_register_op =3D 0x3, }, { .name =3D "add", .translate =3D translate_add, - .windowed_register_op =3D 0x7, }, { .name =3D "add.n", .translate =3D translate_add, - .windowed_register_op =3D 0x7, }, { .name =3D "addi", .translate =3D translate_addi, - .windowed_register_op =3D 0x3, }, { .name =3D "addi.n", .translate =3D translate_addi, - .windowed_register_op =3D 0x3, }, { .name =3D "addmi", .translate =3D translate_addi, - .windowed_register_op =3D 0x3, }, { .name =3D "addx2", .translate =3D translate_addx, .par =3D (const uint32_t[]){1}, - .windowed_register_op =3D 0x7, }, { .name =3D "addx4", .translate =3D translate_addx, .par =3D (const uint32_t[]){2}, - .windowed_register_op =3D 0x7, }, { .name =3D "addx8", .translate =3D translate_addx, .par =3D (const uint32_t[]){3}, - .windowed_register_op =3D 0x7, }, { .name =3D "all4", .translate =3D translate_all, @@ -2482,7 +2467,6 @@ static const XtensaOpcodeOps core_ops[] =3D { }, { .name =3D "and", .translate =3D translate_and, - .windowed_register_op =3D 0x7, }, { .name =3D "andb", .translate =3D translate_boolean, @@ -2503,52 +2487,42 @@ static const XtensaOpcodeOps core_ops[] =3D { .name =3D "ball", .translate =3D translate_ball, .par =3D (const uint32_t[]){TCG_COND_EQ}, - .windowed_register_op =3D 0x3, }, { .name =3D "bany", .translate =3D translate_bany, .par =3D (const uint32_t[]){TCG_COND_NE}, - .windowed_register_op =3D 0x3, }, { .name =3D "bbc", .translate =3D translate_bb, .par =3D (const uint32_t[]){TCG_COND_EQ}, - .windowed_register_op =3D 0x3, }, { .name =3D "bbci", .translate =3D translate_bbi, .par =3D (const uint32_t[]){TCG_COND_EQ}, - .windowed_register_op =3D 0x1, }, { .name =3D "bbs", .translate =3D translate_bb, .par =3D (const uint32_t[]){TCG_COND_NE}, - .windowed_register_op =3D 0x3, }, { .name =3D "bbsi", .translate =3D translate_bbi, .par =3D (const uint32_t[]){TCG_COND_NE}, - .windowed_register_op =3D 0x1, }, { .name =3D "beq", .translate =3D translate_b, .par =3D (const uint32_t[]){TCG_COND_EQ}, - .windowed_register_op =3D 0x3, }, { .name =3D "beqi", .translate =3D translate_bi, .par =3D (const uint32_t[]){TCG_COND_EQ}, - .windowed_register_op =3D 0x1, }, { .name =3D "beqz", .translate =3D translate_bz, .par =3D (const uint32_t[]){TCG_COND_EQ}, - .windowed_register_op =3D 0x1, }, { .name =3D "beqz.n", .translate =3D translate_bz, .par =3D (const uint32_t[]){TCG_COND_EQ}, - .windowed_register_op =3D 0x1, }, { .name =3D "bf", .translate =3D translate_bp, @@ -2557,82 +2531,66 @@ static const XtensaOpcodeOps core_ops[] =3D { .name =3D "bge", .translate =3D translate_b, .par =3D (const uint32_t[]){TCG_COND_GE}, - .windowed_register_op =3D 0x3, }, { .name =3D "bgei", .translate =3D translate_bi, .par =3D (const uint32_t[]){TCG_COND_GE}, - .windowed_register_op =3D 0x1, }, { .name =3D "bgeu", .translate =3D translate_b, .par =3D (const uint32_t[]){TCG_COND_GEU}, - .windowed_register_op =3D 0x3, }, { .name =3D "bgeui", .translate =3D translate_bi, .par =3D (const uint32_t[]){TCG_COND_GEU}, - .windowed_register_op =3D 0x1, }, { .name =3D "bgez", .translate =3D translate_bz, .par =3D (const uint32_t[]){TCG_COND_GE}, - .windowed_register_op =3D 0x1, }, { .name =3D "blt", .translate =3D translate_b, .par =3D (const uint32_t[]){TCG_COND_LT}, - .windowed_register_op =3D 0x3, }, { .name =3D "blti", .translate =3D translate_bi, .par =3D (const uint32_t[]){TCG_COND_LT}, - .windowed_register_op =3D 0x1, }, { .name =3D "bltu", .translate =3D translate_b, .par =3D (const uint32_t[]){TCG_COND_LTU}, - .windowed_register_op =3D 0x3, }, { .name =3D "bltui", .translate =3D translate_bi, .par =3D (const uint32_t[]){TCG_COND_LTU}, - .windowed_register_op =3D 0x1, }, { .name =3D "bltz", .translate =3D translate_bz, .par =3D (const uint32_t[]){TCG_COND_LT}, - .windowed_register_op =3D 0x1, }, { .name =3D "bnall", .translate =3D translate_ball, .par =3D (const uint32_t[]){TCG_COND_NE}, - .windowed_register_op =3D 0x3, }, { .name =3D "bne", .translate =3D translate_b, .par =3D (const uint32_t[]){TCG_COND_NE}, - .windowed_register_op =3D 0x3, }, { .name =3D "bnei", .translate =3D translate_bi, .par =3D (const uint32_t[]){TCG_COND_NE}, - .windowed_register_op =3D 0x1, }, { .name =3D "bnez", .translate =3D translate_bz, .par =3D (const uint32_t[]){TCG_COND_NE}, - .windowed_register_op =3D 0x1, }, { .name =3D "bnez.n", .translate =3D translate_bz, .par =3D (const uint32_t[]){TCG_COND_NE}, - .windowed_register_op =3D 0x1, }, { .name =3D "bnone", .translate =3D translate_bany, .par =3D (const uint32_t[]){TCG_COND_EQ}, - .windowed_register_op =3D 0x3, }, { .name =3D "break", .translate =3D translate_nop, @@ -2653,114 +2611,88 @@ static const XtensaOpcodeOps core_ops[] =3D { }, { .name =3D "call12", .translate =3D translate_callw, - .test_overflow =3D test_overflow_callw, .par =3D (const uint32_t[]){3}, }, { .name =3D "call4", .translate =3D translate_callw, - .test_overflow =3D test_overflow_callw, .par =3D (const uint32_t[]){1}, }, { .name =3D "call8", .translate =3D translate_callw, - .test_overflow =3D test_overflow_callw, .par =3D (const uint32_t[]){2}, }, { .name =3D "callx0", .translate =3D translate_callx0, - .windowed_register_op =3D 0x1, }, { .name =3D "callx12", .translate =3D translate_callxw, - .test_overflow =3D test_overflow_callw, .par =3D (const uint32_t[]){3}, - .windowed_register_op =3D 0x1, }, { .name =3D "callx4", .translate =3D translate_callxw, - .test_overflow =3D test_overflow_callw, .par =3D (const uint32_t[]){1}, - .windowed_register_op =3D 0x1, }, { .name =3D "callx8", .translate =3D translate_callxw, - .test_overflow =3D test_overflow_callw, .par =3D (const uint32_t[]){2}, - .windowed_register_op =3D 0x1, }, { .name =3D "clamps", .translate =3D translate_clamps, - .windowed_register_op =3D 0x3, }, { .name =3D "clrb_expstate", .translate =3D translate_clrb_expstate, }, { .name =3D "const16", .translate =3D translate_const16, - .windowed_register_op =3D 0x1, }, { .name =3D "depbits", .translate =3D translate_depbits, - .windowed_register_op =3D 0x3, }, { .name =3D "dhi", .translate =3D translate_dcache, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "dhu", .translate =3D translate_dcache, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "dhwb", .translate =3D translate_dcache, - .windowed_register_op =3D 0x1, }, { .name =3D "dhwbi", .translate =3D translate_dcache, - .windowed_register_op =3D 0x1, }, { .name =3D "dii", .translate =3D translate_nop, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "diu", .translate =3D translate_nop, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "diwb", .translate =3D translate_nop, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "diwbi", .translate =3D translate_nop, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "dpfl", .translate =3D translate_dcache, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "dpfr", .translate =3D translate_nop, - .windowed_register_op =3D 0x1, }, { .name =3D "dpfro", .translate =3D translate_nop, - .windowed_register_op =3D 0x1, }, { .name =3D "dpfw", .translate =3D translate_nop, - .windowed_register_op =3D 0x1, }, { .name =3D "dpfwo", .translate =3D translate_nop, - .windowed_register_op =3D 0x1, }, { .name =3D "dsync", .translate =3D translate_nop, @@ -2779,7 +2711,6 @@ static const XtensaOpcodeOps core_ops[] =3D { }, { .name =3D "extui", .translate =3D translate_extui, - .windowed_register_op =3D 0x3, }, { .name =3D "extw", .translate =3D translate_memw, @@ -2794,32 +2725,26 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_itlb, .par =3D (const uint32_t[]){true}, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op =3D 0x1, }, { .name =3D "ihi", .translate =3D translate_icache, - .windowed_register_op =3D 0x1, }, { .name =3D "ihu", .translate =3D translate_icache, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "iii", .translate =3D translate_nop, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "iitlb", .translate =3D translate_itlb, .par =3D (const uint32_t[]){false}, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op =3D 0x1, }, { .name =3D "iiu", .translate =3D translate_nop, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "ill", .op_flags =3D XTENSA_OP_ILL, @@ -2829,12 +2754,10 @@ static const XtensaOpcodeOps core_ops[] =3D { }, { .name =3D "ipf", .translate =3D translate_nop, - .windowed_register_op =3D 0x1, }, { .name =3D "ipfl", .translate =3D translate_icache, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "isync", .translate =3D translate_nop, @@ -2844,56 +2767,45 @@ static const XtensaOpcodeOps core_ops[] =3D { }, { .name =3D "jx", .translate =3D translate_jx, - .windowed_register_op =3D 0x1, }, { .name =3D "l16si", .translate =3D translate_ldst, .par =3D (const uint32_t[]){MO_TESW, false, false}, - .windowed_register_op =3D 0x3, }, { .name =3D "l16ui", .translate =3D translate_ldst, .par =3D (const uint32_t[]){MO_TEUW, false, false}, - .windowed_register_op =3D 0x3, }, { .name =3D "l32ai", .translate =3D translate_ldst, .par =3D (const uint32_t[]){MO_TEUL, true, false}, - .windowed_register_op =3D 0x3, }, { .name =3D "l32e", .translate =3D translate_l32e, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x3, }, { .name =3D "l32i", .translate =3D translate_ldst, .par =3D (const uint32_t[]){MO_TEUL, false, false}, - .windowed_register_op =3D 0x3, }, { .name =3D "l32i.n", .translate =3D translate_ldst, .par =3D (const uint32_t[]){MO_TEUL, false, false}, - .windowed_register_op =3D 0x3, }, { .name =3D "l32r", .translate =3D translate_l32r, - .windowed_register_op =3D 0x1, }, { .name =3D "l8ui", .translate =3D translate_ldst, .par =3D (const uint32_t[]){MO_UB, false, false}, - .windowed_register_op =3D 0x3, }, { .name =3D "lddec", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_NONE, 0, 0, -4}, - .windowed_register_op =3D 0x2, }, { .name =3D "ldinc", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_NONE, 0, 0, 4}, - .windowed_register_op =3D 0x2, }, { .name =3D "ldpte", .op_flags =3D XTENSA_OP_ILL, @@ -2901,147 +2813,117 @@ static const XtensaOpcodeOps core_ops[] =3D { .name =3D "loop", .translate =3D translate_loop, .par =3D (const uint32_t[]){TCG_COND_NEVER}, - .windowed_register_op =3D 0x1, }, { .name =3D "loopgtz", .translate =3D translate_loop, .par =3D (const uint32_t[]){TCG_COND_GT}, - .windowed_register_op =3D 0x1, }, { .name =3D "loopnez", .translate =3D translate_loop, .par =3D (const uint32_t[]){TCG_COND_NE}, - .windowed_register_op =3D 0x1, }, { .name =3D "max", .translate =3D translate_smax, - .windowed_register_op =3D 0x7, }, { .name =3D "maxu", .translate =3D translate_umax, - .windowed_register_op =3D 0x7, }, { .name =3D "memw", .translate =3D translate_memw, }, { .name =3D "min", .translate =3D translate_smin, - .windowed_register_op =3D 0x7, }, { .name =3D "minu", .translate =3D translate_umin, - .windowed_register_op =3D 0x7, }, { .name =3D "mov", .translate =3D translate_mov, - .windowed_register_op =3D 0x3, }, { .name =3D "mov.n", .translate =3D translate_mov, - .windowed_register_op =3D 0x3, }, { .name =3D "moveqz", .translate =3D translate_movcond, .par =3D (const uint32_t[]){TCG_COND_EQ}, - .windowed_register_op =3D 0x7, }, { .name =3D "movf", .translate =3D translate_movp, .par =3D (const uint32_t[]){TCG_COND_EQ}, - .windowed_register_op =3D 0x3, }, { .name =3D "movgez", .translate =3D translate_movcond, .par =3D (const uint32_t[]){TCG_COND_GE}, - .windowed_register_op =3D 0x7, }, { .name =3D "movi", .translate =3D translate_movi, - .windowed_register_op =3D 0x1, }, { .name =3D "movi.n", .translate =3D translate_movi, - .windowed_register_op =3D 0x1, }, { .name =3D "movltz", .translate =3D translate_movcond, .par =3D (const uint32_t[]){TCG_COND_LT}, - .windowed_register_op =3D 0x7, }, { .name =3D "movnez", .translate =3D translate_movcond, .par =3D (const uint32_t[]){TCG_COND_NE}, - .windowed_register_op =3D 0x7, }, { .name =3D "movsp", .translate =3D translate_movsp, - .windowed_register_op =3D 0x3, .op_flags =3D XTENSA_OP_ALLOCA, }, { .name =3D "movt", .translate =3D translate_movp, .par =3D (const uint32_t[]){TCG_COND_NE}, - .windowed_register_op =3D 0x3, }, { .name =3D "mul.aa.hh", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_HH, 0}, - .windowed_register_op =3D 0x3, }, { .name =3D "mul.aa.hl", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_HL, 0}, - .windowed_register_op =3D 0x3, }, { .name =3D "mul.aa.lh", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_LH, 0}, - .windowed_register_op =3D 0x3, }, { .name =3D "mul.aa.ll", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_LL, 0}, - .windowed_register_op =3D 0x3, }, { .name =3D "mul.ad.hh", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_HH, 0}, - .windowed_register_op =3D 0x1, }, { .name =3D "mul.ad.hl", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_HL, 0}, - .windowed_register_op =3D 0x1, }, { .name =3D "mul.ad.lh", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_LH, 0}, - .windowed_register_op =3D 0x1, }, { .name =3D "mul.ad.ll", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_LL, 0}, - .windowed_register_op =3D 0x1, }, { .name =3D "mul.da.hh", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_HH, 0}, - .windowed_register_op =3D 0x2, }, { .name =3D "mul.da.hl", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_HL, 0}, - .windowed_register_op =3D 0x2, }, { .name =3D "mul.da.lh", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_LH, 0}, - .windowed_register_op =3D 0x2, }, { .name =3D "mul.da.ll", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_LL, 0}, - .windowed_register_op =3D 0x2, }, { .name =3D "mul.dd.hh", .translate =3D translate_mac16, @@ -3062,112 +2944,90 @@ static const XtensaOpcodeOps core_ops[] =3D { .name =3D "mul16s", .translate =3D translate_mul16, .par =3D (const uint32_t[]){true}, - .windowed_register_op =3D 0x7, }, { .name =3D "mul16u", .translate =3D translate_mul16, .par =3D (const uint32_t[]){false}, - .windowed_register_op =3D 0x7, }, { .name =3D "mula.aa.hh", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_HH, 0}, - .windowed_register_op =3D 0x3, }, { .name =3D "mula.aa.hl", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_HL, 0}, - .windowed_register_op =3D 0x3, }, { .name =3D "mula.aa.lh", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_LH, 0}, - .windowed_register_op =3D 0x3, }, { .name =3D "mula.aa.ll", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_LL, 0}, - .windowed_register_op =3D 0x3, }, { .name =3D "mula.ad.hh", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_HH, 0}, - .windowed_register_op =3D 0x1, }, { .name =3D "mula.ad.hl", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_HL, 0}, - .windowed_register_op =3D 0x1, }, { .name =3D "mula.ad.lh", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_LH, 0}, - .windowed_register_op =3D 0x1, }, { .name =3D "mula.ad.ll", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_LL, 0}, - .windowed_register_op =3D 0x1, }, { .name =3D "mula.da.hh", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HH, 0}, - .windowed_register_op =3D 0x2, }, { .name =3D "mula.da.hh.lddec", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HH, -4}, - .windowed_register_op =3D 0xa, }, { .name =3D "mula.da.hh.ldinc", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HH, 4}, - .windowed_register_op =3D 0xa, }, { .name =3D "mula.da.hl", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HL, 0}, - .windowed_register_op =3D 0x2, }, { .name =3D "mula.da.hl.lddec", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HL, -4}, - .windowed_register_op =3D 0xa, }, { .name =3D "mula.da.hl.ldinc", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HL, 4}, - .windowed_register_op =3D 0xa, }, { .name =3D "mula.da.lh", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LH, 0}, - .windowed_register_op =3D 0x2, }, { .name =3D "mula.da.lh.lddec", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LH, -4}, - .windowed_register_op =3D 0xa, }, { .name =3D "mula.da.lh.ldinc", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LH, 4}, - .windowed_register_op =3D 0xa, }, { .name =3D "mula.da.ll", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LL, 0}, - .windowed_register_op =3D 0x2, }, { .name =3D "mula.da.ll.lddec", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LL, -4}, - .windowed_register_op =3D 0xa, }, { .name =3D "mula.da.ll.ldinc", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LL, 4}, - .windowed_register_op =3D 0xa, }, { .name =3D "mula.dd.hh", .translate =3D translate_mac16, @@ -3176,12 +3036,10 @@ static const XtensaOpcodeOps core_ops[] =3D { .name =3D "mula.dd.hh.lddec", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HH, -4}, - .windowed_register_op =3D 0x2, }, { .name =3D "mula.dd.hh.ldinc", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HH, 4}, - .windowed_register_op =3D 0x2, }, { .name =3D "mula.dd.hl", .translate =3D translate_mac16, @@ -3190,12 +3048,10 @@ static const XtensaOpcodeOps core_ops[] =3D { .name =3D "mula.dd.hl.lddec", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HL, -4}, - .windowed_register_op =3D 0x2, }, { .name =3D "mula.dd.hl.ldinc", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HL, 4}, - .windowed_register_op =3D 0x2, }, { .name =3D "mula.dd.lh", .translate =3D translate_mac16, @@ -3204,12 +3060,10 @@ static const XtensaOpcodeOps core_ops[] =3D { .name =3D "mula.dd.lh.lddec", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LH, -4}, - .windowed_register_op =3D 0x2, }, { .name =3D "mula.dd.lh.ldinc", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LH, 4}, - .windowed_register_op =3D 0x2, }, { .name =3D "mula.dd.ll", .translate =3D translate_mac16, @@ -3218,76 +3072,61 @@ static const XtensaOpcodeOps core_ops[] =3D { .name =3D "mula.dd.ll.lddec", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LL, -4}, - .windowed_register_op =3D 0x2, }, { .name =3D "mula.dd.ll.ldinc", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LL, 4}, - .windowed_register_op =3D 0x2, }, { .name =3D "mull", .translate =3D translate_mull, - .windowed_register_op =3D 0x7, }, { .name =3D "muls.aa.hh", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_HH, 0}, - .windowed_register_op =3D 0x3, }, { .name =3D "muls.aa.hl", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_HL, 0}, - .windowed_register_op =3D 0x3, }, { .name =3D "muls.aa.lh", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_LH, 0}, - .windowed_register_op =3D 0x3, }, { .name =3D "muls.aa.ll", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_LL, 0}, - .windowed_register_op =3D 0x3, }, { .name =3D "muls.ad.hh", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_HH, 0}, - .windowed_register_op =3D 0x1, }, { .name =3D "muls.ad.hl", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_HL, 0}, - .windowed_register_op =3D 0x1, }, { .name =3D "muls.ad.lh", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_LH, 0}, - .windowed_register_op =3D 0x1, }, { .name =3D "muls.ad.ll", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_LL, 0}, - .windowed_register_op =3D 0x1, }, { .name =3D "muls.da.hh", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_HH, 0}, - .windowed_register_op =3D 0x2, }, { .name =3D "muls.da.hl", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_HL, 0}, - .windowed_register_op =3D 0x2, }, { .name =3D "muls.da.lh", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_LH, 0}, - .windowed_register_op =3D 0x2, }, { .name =3D "muls.da.ll", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_LL, 0}, - .windowed_register_op =3D 0x2, }, { .name =3D "muls.dd.hh", .translate =3D translate_mac16, @@ -3308,16 +3147,13 @@ static const XtensaOpcodeOps core_ops[] =3D { .name =3D "mulsh", .translate =3D translate_mulh, .par =3D (const uint32_t[]){true}, - .windowed_register_op =3D 0x7, }, { .name =3D "muluh", .translate =3D translate_mulh, .par =3D (const uint32_t[]){false}, - .windowed_register_op =3D 0x7, }, { .name =3D "neg", .translate =3D translate_neg, - .windowed_register_op =3D 0x3, }, { .name =3D "nop", .translate =3D translate_nop, @@ -3327,15 +3163,12 @@ static const XtensaOpcodeOps core_ops[] =3D { }, { .name =3D "nsa", .translate =3D translate_nsa, - .windowed_register_op =3D 0x3, }, { .name =3D "nsau", .translate =3D translate_nsau, - .windowed_register_op =3D 0x3, }, { .name =3D "or", .translate =3D translate_or, - .windowed_register_op =3D 0x7, }, { .name =3D "orb", .translate =3D translate_boolean, @@ -3349,56 +3182,46 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_ptlb, .par =3D (const uint32_t[]){true}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x3, }, { .name =3D "pitlb", .translate =3D translate_ptlb, .par =3D (const uint32_t[]){false}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x3, }, { .name =3D "quos", .translate =3D translate_quos, .par =3D (const uint32_t[]){true}, .op_flags =3D XTENSA_OP_DIVIDE_BY_ZERO, - .windowed_register_op =3D 0x7, }, { .name =3D "quou", .translate =3D translate_quou, .op_flags =3D XTENSA_OP_DIVIDE_BY_ZERO, - .windowed_register_op =3D 0x7, }, { .name =3D "rdtlb0", .translate =3D translate_rtlb, .par =3D (const uint32_t[]){true, 0}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x3, }, { .name =3D "rdtlb1", .translate =3D translate_rtlb, .par =3D (const uint32_t[]){true, 1}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x3, }, { .name =3D "read_impwire", .translate =3D translate_read_impwire, - .windowed_register_op =3D 0x1, }, { .name =3D "rems", .translate =3D translate_quos, .par =3D (const uint32_t[]){false}, .op_flags =3D XTENSA_OP_DIVIDE_BY_ZERO, - .windowed_register_op =3D 0x7, }, { .name =3D "remu", .translate =3D translate_remu, .op_flags =3D XTENSA_OP_DIVIDE_BY_ZERO, - .windowed_register_op =3D 0x7, }, { .name =3D "rer", .translate =3D translate_rer, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x3, }, { .name =3D "ret", .translate =3D translate_ret, @@ -3448,13 +3271,11 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_rtlb, .par =3D (const uint32_t[]){false, 0}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x3, }, { .name =3D "ritlb1", .translate =3D translate_rtlb, .par =3D (const uint32_t[]){false, 1}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x3, }, { .name =3D "rotw", .translate =3D translate_rotw, @@ -3466,526 +3287,449 @@ static const XtensaOpcodeOps core_ops[] =3D { XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0 | XTENSA_OP_CHECK_INTERRUPTS, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.176", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){176}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.208", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){208}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.acchi", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){ACCHI}, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.acclo", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){ACCLO}, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.atomctl", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){ATOMCTL}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.br", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){BR}, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.cacheattr", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){CACHEATTR}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.ccompare0", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){CCOMPARE}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.ccompare1", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){CCOMPARE + 1}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.ccompare2", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){CCOMPARE + 2}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.ccount", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){CCOUNT}, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.configid0", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){CONFIGID0}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.configid1", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){CONFIGID1}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.cpenable", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){CPENABLE}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.dbreaka0", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){DBREAKA}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.dbreaka1", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){DBREAKA + 1}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.dbreakc0", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){DBREAKC}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.dbreakc1", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){DBREAKC + 1}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.ddr", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){DDR}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.debugcause", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){DEBUGCAUSE}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.depc", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){DEPC}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.dtlbcfg", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){DTLBCFG}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.epc1", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EPC1}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.epc2", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EPC1 + 1}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.epc3", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EPC1 + 2}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.epc4", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EPC1 + 3}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.epc5", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EPC1 + 4}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.epc6", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EPC1 + 5}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.epc7", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EPC1 + 6}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.eps2", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EPS2}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.eps3", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EPS2 + 1}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.eps4", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EPS2 + 2}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.eps5", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EPS2 + 3}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.eps6", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EPS2 + 4}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.eps7", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EPS2 + 5}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.exccause", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EXCCAUSE}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.excsave1", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EXCSAVE1}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.excsave2", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EXCSAVE1 + 1}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.excsave3", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EXCSAVE1 + 2}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.excsave4", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EXCSAVE1 + 3}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.excsave5", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EXCSAVE1 + 4}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.excsave6", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EXCSAVE1 + 5}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.excsave7", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EXCSAVE1 + 6}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.excvaddr", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){EXCVADDR}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.ibreaka0", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){IBREAKA}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.ibreaka1", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){IBREAKA + 1}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.ibreakenable", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){IBREAKENABLE}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.icount", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){ICOUNT}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.icountlevel", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){ICOUNTLEVEL}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.intclear", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){INTCLEAR}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.intenable", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){INTENABLE}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.interrupt", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){INTSET}, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.intset", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){INTSET}, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.itlbcfg", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){ITLBCFG}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.lbeg", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){LBEG}, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.lcount", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){LCOUNT}, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.lend", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){LEND}, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.litbase", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){LITBASE}, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.m0", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){MR}, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.m1", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){MR + 1}, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.m2", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){MR + 2}, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.m3", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){MR + 3}, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.memctl", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){MEMCTL}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.misc0", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){MISC}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.misc1", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){MISC + 1}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.misc2", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){MISC + 2}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.misc3", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){MISC + 3}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.prid", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){PRID}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.ps", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){PS}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.ptevaddr", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){PTEVADDR}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.rasid", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){RASID}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.sar", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){SAR}, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.scompare1", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){SCOMPARE1}, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.vecbase", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){VECBASE}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.windowbase", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){WINDOW_BASE}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsr.windowstart", .translate =3D translate_rsr, .test_ill =3D test_ill_rsr, .par =3D (const uint32_t[]){WINDOW_START}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "rsync", .translate =3D translate_nop, @@ -3993,80 +3737,65 @@ static const XtensaOpcodeOps core_ops[] =3D { .name =3D "rur.expstate", .translate =3D translate_rur, .par =3D (const uint32_t[]){EXPSTATE}, - .windowed_register_op =3D 0x1, }, { .name =3D "rur.fcr", .translate =3D translate_rur, .par =3D (const uint32_t[]){FCR}, - .windowed_register_op =3D 0x1, .coprocessor =3D 0x1, }, { .name =3D "rur.fsr", .translate =3D translate_rur, .par =3D (const uint32_t[]){FSR}, - .windowed_register_op =3D 0x1, .coprocessor =3D 0x1, }, { .name =3D "rur.threadptr", .translate =3D translate_rur, .par =3D (const uint32_t[]){THREADPTR}, - .windowed_register_op =3D 0x1, }, { .name =3D "s16i", .translate =3D translate_ldst, .par =3D (const uint32_t[]){MO_TEUW, false, true}, - .windowed_register_op =3D 0x3, }, { .name =3D "s32c1i", .translate =3D translate_s32c1i, - .windowed_register_op =3D 0x3, }, { .name =3D "s32e", .translate =3D translate_s32e, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x3, }, { .name =3D "s32i", .translate =3D translate_ldst, .par =3D (const uint32_t[]){MO_TEUL, false, true}, - .windowed_register_op =3D 0x3, }, { .name =3D "s32i.n", .translate =3D translate_ldst, .par =3D (const uint32_t[]){MO_TEUL, false, true}, - .windowed_register_op =3D 0x3, }, { .name =3D "s32nb", .translate =3D translate_ldst, .par =3D (const uint32_t[]){MO_TEUL, false, true}, - .windowed_register_op =3D 0x3, }, { .name =3D "s32ri", .translate =3D translate_ldst, .par =3D (const uint32_t[]){MO_TEUL, true, true}, - .windowed_register_op =3D 0x3, }, { .name =3D "s8i", .translate =3D translate_ldst, .par =3D (const uint32_t[]){MO_UB, false, true}, - .windowed_register_op =3D 0x3, }, { .name =3D "salt", .translate =3D translate_salt, .par =3D (const uint32_t[]){TCG_COND_LT}, - .windowed_register_op =3D 0x7, }, { .name =3D "saltu", .translate =3D translate_salt, .par =3D (const uint32_t[]){TCG_COND_LTU}, - .windowed_register_op =3D 0x7, }, { .name =3D "setb_expstate", .translate =3D translate_setb_expstate, }, { .name =3D "sext", .translate =3D translate_sext, - .windowed_register_op =3D 0x3, }, { .name =3D "simcall", .translate =3D translate_simcall, @@ -4075,69 +3804,54 @@ static const XtensaOpcodeOps core_ops[] =3D { }, { .name =3D "sll", .translate =3D translate_sll, - .windowed_register_op =3D 0x3, }, { .name =3D "slli", .translate =3D translate_slli, - .windowed_register_op =3D 0x3, }, { .name =3D "sra", .translate =3D translate_sra, - .windowed_register_op =3D 0x3, }, { .name =3D "srai", .translate =3D translate_srai, - .windowed_register_op =3D 0x3, }, { .name =3D "src", .translate =3D translate_src, - .windowed_register_op =3D 0x7, }, { .name =3D "srl", .translate =3D translate_srl, - .windowed_register_op =3D 0x3, }, { .name =3D "srli", .translate =3D translate_srli, - .windowed_register_op =3D 0x3, }, { .name =3D "ssa8b", .translate =3D translate_ssa8b, - .windowed_register_op =3D 0x1, }, { .name =3D "ssa8l", .translate =3D translate_ssa8l, - .windowed_register_op =3D 0x1, }, { .name =3D "ssai", .translate =3D translate_ssai, }, { .name =3D "ssl", .translate =3D translate_ssl, - .windowed_register_op =3D 0x1, }, { .name =3D "ssr", .translate =3D translate_ssr, - .windowed_register_op =3D 0x1, }, { .name =3D "sub", .translate =3D translate_sub, - .windowed_register_op =3D 0x7, }, { .name =3D "subx2", .translate =3D translate_subx, .par =3D (const uint32_t[]){1}, - .windowed_register_op =3D 0x7, }, { .name =3D "subx4", .translate =3D translate_subx, .par =3D (const uint32_t[]){2}, - .windowed_register_op =3D 0x7, }, { .name =3D "subx8", .translate =3D translate_subx, .par =3D (const uint32_t[]){3}, - .windowed_register_op =3D 0x7, }, { .name =3D "syscall", .op_flags =3D XTENSA_OP_SYSCALL, @@ -4145,22 +3859,18 @@ static const XtensaOpcodeOps core_ops[] =3D { .name =3D "umul.aa.hh", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_HH, 0}, - .windowed_register_op =3D 0x3, }, { .name =3D "umul.aa.hl", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_HL, 0}, - .windowed_register_op =3D 0x3, }, { .name =3D "umul.aa.lh", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_LH, 0}, - .windowed_register_op =3D 0x3, }, { .name =3D "umul.aa.ll", .translate =3D translate_mac16, .par =3D (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_LL, 0}, - .windowed_register_op =3D 0x3, }, { .name =3D "waiti", .translate =3D translate_waiti, @@ -4170,362 +3880,309 @@ static const XtensaOpcodeOps core_ops[] =3D { .translate =3D translate_wtlb, .par =3D (const uint32_t[]){true}, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op =3D 0x3, }, { .name =3D "wer", .translate =3D translate_wer, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x3, }, { .name =3D "witlb", .translate =3D translate_wtlb, .par =3D (const uint32_t[]){false}, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op =3D 0x3, }, { .name =3D "wrmsk_expstate", .translate =3D translate_wrmsk_expstate, - .windowed_register_op =3D 0x3, }, { .name =3D "wsr.176", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){176}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.208", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){208}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.acchi", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){ACCHI}, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.acclo", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){ACCLO}, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.atomctl", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){ATOMCTL}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.br", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){BR}, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.cacheattr", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){CACHEATTR}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.ccompare0", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){CCOMPARE}, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.ccompare1", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){CCOMPARE + 1}, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.ccompare2", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){CCOMPARE + 2}, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.ccount", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){CCOUNT}, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.configid0", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){CONFIGID0}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.configid1", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){CONFIGID1}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.cpenable", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){CPENABLE}, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.dbreaka0", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){DBREAKA}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.dbreaka1", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){DBREAKA + 1}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.dbreakc0", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){DBREAKC}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.dbreakc1", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){DBREAKC + 1}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.ddr", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){DDR}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.debugcause", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){DEBUGCAUSE}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.depc", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){DEPC}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.dtlbcfg", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){DTLBCFG}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.epc1", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EPC1}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.epc2", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EPC1 + 1}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.epc3", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EPC1 + 2}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.epc4", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EPC1 + 3}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.epc5", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EPC1 + 4}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.epc6", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EPC1 + 5}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.epc7", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EPC1 + 6}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.eps2", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EPS2}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.eps3", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EPS2 + 1}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.eps4", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EPS2 + 2}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.eps5", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EPS2 + 3}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.eps6", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EPS2 + 4}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.eps7", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EPS2 + 5}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.exccause", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EXCCAUSE}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.excsave1", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EXCSAVE1}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.excsave2", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EXCSAVE1 + 1}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.excsave3", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EXCSAVE1 + 2}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.excsave4", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EXCSAVE1 + 3}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.excsave5", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EXCSAVE1 + 4}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.excsave6", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EXCSAVE1 + 5}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.excsave7", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EXCSAVE1 + 6}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.excvaddr", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){EXCVADDR}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.ibreaka0", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){IBREAKA}, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.ibreaka1", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){IBREAKA + 1}, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.ibreakenable", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){IBREAKENABLE}, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.icount", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){ICOUNT}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.icountlevel", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){ICOUNTLEVEL}, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.intclear", .translate =3D translate_wsr, @@ -4535,7 +4192,6 @@ static const XtensaOpcodeOps core_ops[] =3D { XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0 | XTENSA_OP_CHECK_INTERRUPTS, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.intenable", .translate =3D translate_wsr, @@ -4545,7 +4201,6 @@ static const XtensaOpcodeOps core_ops[] =3D { XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0 | XTENSA_OP_CHECK_INTERRUPTS, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.interrupt", .translate =3D translate_wsr, @@ -4555,7 +4210,6 @@ static const XtensaOpcodeOps core_ops[] =3D { XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0 | XTENSA_OP_CHECK_INTERRUPTS, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.intset", .translate =3D translate_wsr, @@ -4565,114 +4219,97 @@ static const XtensaOpcodeOps core_ops[] =3D { XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0 | XTENSA_OP_CHECK_INTERRUPTS, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.itlbcfg", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){ITLBCFG}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.lbeg", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){LBEG}, .op_flags =3D XTENSA_OP_EXIT_TB_M1, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.lcount", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){LCOUNT}, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.lend", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){LEND}, .op_flags =3D XTENSA_OP_EXIT_TB_M1, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.litbase", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){LITBASE}, .op_flags =3D XTENSA_OP_EXIT_TB_M1, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.m0", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){MR}, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.m1", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){MR + 1}, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.m2", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){MR + 2}, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.m3", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){MR + 3}, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.memctl", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){MEMCTL}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.misc0", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){MISC}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.misc1", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){MISC + 1}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.misc2", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){MISC + 2}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.misc3", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){MISC + 3}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.mmid", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){MMID}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.prid", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){PRID}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.ps", .translate =3D translate_wsr, @@ -4682,80 +4319,67 @@ static const XtensaOpcodeOps core_ops[] =3D { XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1 | XTENSA_OP_CHECK_INTERRUPTS, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.ptevaddr", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){PTEVADDR}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.rasid", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){RASID}, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.sar", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){SAR}, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.scompare1", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){SCOMPARE1}, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.vecbase", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){VECBASE}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.windowbase", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){WINDOW_BASE}, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op =3D 0x1, }, { .name =3D "wsr.windowstart", .translate =3D translate_wsr, .test_ill =3D test_ill_wsr, .par =3D (const uint32_t[]){WINDOW_START}, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op =3D 0x1, }, { .name =3D "wur.expstate", .translate =3D translate_wur, .par =3D (const uint32_t[]){EXPSTATE}, - .windowed_register_op =3D 0x1, }, { .name =3D "wur.fcr", .translate =3D translate_wur, .par =3D (const uint32_t[]){FCR}, - .windowed_register_op =3D 0x1, .coprocessor =3D 0x1, }, { .name =3D "wur.fsr", .translate =3D translate_wur, .par =3D (const uint32_t[]){FSR}, - .windowed_register_op =3D 0x1, .coprocessor =3D 0x1, }, { .name =3D "wur.threadptr", .translate =3D translate_wur, .par =3D (const uint32_t[]){THREADPTR}, - .windowed_register_op =3D 0x1, }, { .name =3D "xor", .translate =3D translate_xor, - .windowed_register_op =3D 0x7, }, { .name =3D "xorb", .translate =3D translate_boolean, @@ -4766,340 +4390,291 @@ static const XtensaOpcodeOps core_ops[] =3D { .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){176}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.208", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){208}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.acchi", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){ACCHI}, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.acclo", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){ACCLO}, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.atomctl", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){ATOMCTL}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.br", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){BR}, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.cacheattr", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){CACHEATTR}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.ccompare0", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){CCOMPARE}, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.ccompare1", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){CCOMPARE + 1}, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.ccompare2", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){CCOMPARE + 2}, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.ccount", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){CCOUNT}, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.configid0", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){CONFIGID0}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.configid1", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){CONFIGID1}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.cpenable", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){CPENABLE}, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.dbreaka0", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){DBREAKA}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.dbreaka1", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){DBREAKA + 1}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.dbreakc0", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){DBREAKC}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.dbreakc1", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){DBREAKC + 1}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.ddr", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){DDR}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.debugcause", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){DEBUGCAUSE}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.depc", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){DEPC}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.dtlbcfg", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){DTLBCFG}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.epc1", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EPC1}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.epc2", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EPC1 + 1}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.epc3", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EPC1 + 2}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.epc4", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EPC1 + 3}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.epc5", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EPC1 + 4}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.epc6", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EPC1 + 5}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.epc7", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EPC1 + 6}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.eps2", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EPS2}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.eps3", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EPS2 + 1}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.eps4", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EPS2 + 2}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.eps5", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EPS2 + 3}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.eps6", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EPS2 + 4}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.eps7", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EPS2 + 5}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.exccause", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EXCCAUSE}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.excsave1", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EXCSAVE1}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.excsave2", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EXCSAVE1 + 1}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.excsave3", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EXCSAVE1 + 2}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.excsave4", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EXCSAVE1 + 3}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.excsave5", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EXCSAVE1 + 4}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.excsave6", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EXCSAVE1 + 5}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.excsave7", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EXCSAVE1 + 6}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.excvaddr", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){EXCVADDR}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.ibreaka0", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){IBREAKA}, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.ibreaka1", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){IBREAKA + 1}, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.ibreakenable", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){IBREAKENABLE}, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.icount", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){ICOUNT}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.icountlevel", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){ICOUNTLEVEL}, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.intclear", .translate =3D translate_xsr, @@ -5109,7 +4684,6 @@ static const XtensaOpcodeOps core_ops[] =3D { XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0 | XTENSA_OP_CHECK_INTERRUPTS, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.intenable", .translate =3D translate_xsr, @@ -5119,7 +4693,6 @@ static const XtensaOpcodeOps core_ops[] =3D { XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0 | XTENSA_OP_CHECK_INTERRUPTS, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.interrupt", .translate =3D translate_xsr, @@ -5129,7 +4702,6 @@ static const XtensaOpcodeOps core_ops[] =3D { XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0 | XTENSA_OP_CHECK_INTERRUPTS, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.intset", .translate =3D translate_xsr, @@ -5139,107 +4711,91 @@ static const XtensaOpcodeOps core_ops[] =3D { XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0 | XTENSA_OP_CHECK_INTERRUPTS, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.itlbcfg", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){ITLBCFG}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.lbeg", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){LBEG}, .op_flags =3D XTENSA_OP_EXIT_TB_M1, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.lcount", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){LCOUNT}, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.lend", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){LEND}, .op_flags =3D XTENSA_OP_EXIT_TB_M1, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.litbase", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){LITBASE}, .op_flags =3D XTENSA_OP_EXIT_TB_M1, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.m0", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){MR}, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.m1", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){MR + 1}, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.m2", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){MR + 2}, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.m3", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){MR + 3}, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.memctl", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){MEMCTL}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.misc0", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){MISC}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.misc1", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){MISC + 1}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.misc2", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){MISC + 2}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.misc3", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){MISC + 3}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.prid", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){PRID}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.ps", .translate =3D translate_xsr, @@ -5249,54 +4805,46 @@ static const XtensaOpcodeOps core_ops[] =3D { XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1 | XTENSA_OP_CHECK_INTERRUPTS, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.ptevaddr", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){PTEVADDR}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.rasid", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){RASID}, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.sar", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){SAR}, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.scompare1", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){SCOMPARE1}, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.vecbase", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){VECBASE}, .op_flags =3D XTENSA_OP_PRIVILEGED, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.windowbase", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){WINDOW_BASE}, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op =3D 0x1, }, { .name =3D "xsr.windowstart", .translate =3D translate_xsr, .test_ill =3D test_ill_xsr, .par =3D (const uint32_t[]){WINDOW_START}, .op_flags =3D XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op =3D 0x1, }, }; =20 @@ -5504,43 +5052,36 @@ static const XtensaOpcodeOps fpu2000_ops[] =3D { .name =3D "ceil.s", .translate =3D translate_ftoi_s, .par =3D (const uint32_t[]){float_round_up, false}, - .windowed_register_op =3D 0x1, .coprocessor =3D 0x1, }, { .name =3D "float.s", .translate =3D translate_float_s, .par =3D (const uint32_t[]){false}, - .windowed_register_op =3D 0x2, .coprocessor =3D 0x1, }, { .name =3D "floor.s", .translate =3D translate_ftoi_s, .par =3D (const uint32_t[]){float_round_down, false}, - .windowed_register_op =3D 0x1, .coprocessor =3D 0x1, }, { .name =3D "lsi", .translate =3D translate_ldsti, .par =3D (const uint32_t[]){false, false}, - .windowed_register_op =3D 0x2, .coprocessor =3D 0x1, }, { .name =3D "lsiu", .translate =3D translate_ldsti, .par =3D (const uint32_t[]){false, true}, - .windowed_register_op =3D 0x2, .coprocessor =3D 0x1, }, { .name =3D "lsx", .translate =3D translate_ldstx, .par =3D (const uint32_t[]){false, false}, - .windowed_register_op =3D 0x6, .coprocessor =3D 0x1, }, { .name =3D "lsxu", .translate =3D translate_ldstx, .par =3D (const uint32_t[]){false, true}, - .windowed_register_op =3D 0x6, .coprocessor =3D 0x1, }, { .name =3D "madd.s", @@ -5554,7 +5095,6 @@ static const XtensaOpcodeOps fpu2000_ops[] =3D { .name =3D "moveqz.s", .translate =3D translate_movcond_s, .par =3D (const uint32_t[]){TCG_COND_EQ}, - .windowed_register_op =3D 0x4, .coprocessor =3D 0x1, }, { .name =3D "movf.s", @@ -5565,19 +5105,16 @@ static const XtensaOpcodeOps fpu2000_ops[] =3D { .name =3D "movgez.s", .translate =3D translate_movcond_s, .par =3D (const uint32_t[]){TCG_COND_GE}, - .windowed_register_op =3D 0x4, .coprocessor =3D 0x1, }, { .name =3D "movltz.s", .translate =3D translate_movcond_s, .par =3D (const uint32_t[]){TCG_COND_LT}, - .windowed_register_op =3D 0x4, .coprocessor =3D 0x1, }, { .name =3D "movnez.s", .translate =3D translate_movcond_s, .par =3D (const uint32_t[]){TCG_COND_NE}, - .windowed_register_op =3D 0x4, .coprocessor =3D 0x1, }, { .name =3D "movt.s", @@ -5614,37 +5151,31 @@ static const XtensaOpcodeOps fpu2000_ops[] =3D { }, { .name =3D "rfr", .translate =3D translate_rfr_s, - .windowed_register_op =3D 0x1, .coprocessor =3D 0x1, }, { .name =3D "round.s", .translate =3D translate_ftoi_s, .par =3D (const uint32_t[]){float_round_nearest_even, false}, - .windowed_register_op =3D 0x1, .coprocessor =3D 0x1, }, { .name =3D "ssi", .translate =3D translate_ldsti, .par =3D (const uint32_t[]){true, false}, - .windowed_register_op =3D 0x2, .coprocessor =3D 0x1, }, { .name =3D "ssiu", .translate =3D translate_ldsti, .par =3D (const uint32_t[]){true, true}, - .windowed_register_op =3D 0x2, .coprocessor =3D 0x1, }, { .name =3D "ssx", .translate =3D translate_ldstx, .par =3D (const uint32_t[]){true, false}, - .windowed_register_op =3D 0x6, .coprocessor =3D 0x1, }, { .name =3D "ssxu", .translate =3D translate_ldstx, .par =3D (const uint32_t[]){true, true}, - .windowed_register_op =3D 0x6, .coprocessor =3D 0x1, }, { .name =3D "sub.s", @@ -5654,7 +5185,6 @@ static const XtensaOpcodeOps fpu2000_ops[] =3D { .name =3D "trunc.s", .translate =3D translate_ftoi_s, .par =3D (const uint32_t[]){float_round_to_zero, false}, - .windowed_register_op =3D 0x1, .coprocessor =3D 0x1, }, { .name =3D "ueq.s", @@ -5665,7 +5195,6 @@ static const XtensaOpcodeOps fpu2000_ops[] =3D { .name =3D "ufloat.s", .translate =3D translate_float_s, .par =3D (const uint32_t[]){true}, - .windowed_register_op =3D 0x2, .coprocessor =3D 0x1, }, { .name =3D "ule.s", @@ -5686,12 +5215,10 @@ static const XtensaOpcodeOps fpu2000_ops[] =3D { .name =3D "utrunc.s", .translate =3D translate_ftoi_s, .par =3D (const uint32_t[]){float_round_to_zero, true}, - .windowed_register_op =3D 0x1, .coprocessor =3D 0x1, }, { .name =3D "wfr", .translate =3D translate_wfr_s, - .windowed_register_op =3D 0x2, .coprocessor =3D 0x1, }, }; --=20 2.11.0