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[97.126.115.157]) by smtp.gmail.com with ESMTPSA id s84sm6340737pfi.15.2019.02.08.19.39.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 08 Feb 2019 19:39:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=io0Q8vKcg32ZslzsokBprL4UTtWvNRVBn1H6HUdOh9Q=; b=QvlrwxqpHxMIlTbfeVwY1ExLXe7f7PeexPxZP7h9XqoiYBsqAmmRDya+49OWDH1oIo xWWRU63DyCTbna2LnjPqaUV+31KWXeJkFsGQfdtxYWv0rV5cVqUf4JAjTE//BRfS+zM4 L4zCtlB6XMZoI5q3reoRZLRsjYvyhj1VOJe99ygRuTQP7/fbW+HjLRT7tBM5x1h5CMxp 7Tx1/ryUo5IJkCV1dSMqpbI1tn+AR2Kq7VfgE55kl5Yf6FZDpBxECgChuHS7c52S4rsc R/CR8JAtjMzlS80k+duyMqUeP4wUjzFuliwYX0/zsPTeu0sSWN/cV8aF4uywk9fBAOr2 CJkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=io0Q8vKcg32ZslzsokBprL4UTtWvNRVBn1H6HUdOh9Q=; b=nVXKECcCf6xAfFO3Zlp79gp10zIEjPj/naO/xIC5CAyJj1xnAkFXqFZnazVi1K2otP TLUy5mFD1naPXMMYUtptzSHo2W4eamqe4Z2XOw00Tq7sJq1kwK4RYGDT+2DW+0vkuDE6 +mo+QTtme9Oq+EhkM2jHXUTfhbkAuY1wkEkj2Jc26i+rbeN9j6RYvg8WgIOisJLc2VW/ 237jI/7LbLGc64XEBwfmhWKgXIxTVgJ4jR4jxcwnafbnRE4md0LanHJlWJVoWMNQJSot LpTDpb3G+f9NpaEnO8I5eWE0xydcm1E8treetfWrUCHq8ZgMtaJWKMGG6kZvQJ0UfaY6 RySQ== X-Gm-Message-State: AHQUAubsxORSa4w/lwmaU/LYoU36TBHxVbWsoIPwcpc5AXb7Asyeme4l r2bDgoTSzhmyOchFBU8Ml4RCY/t6nQE= X-Google-Smtp-Source: AHgI3IZ5J4RZ5AXl1uuH7Z1doFc/OUZy6lmEXqazb/7W0pSXnrE/X6HGJcdoI4k4josFTmwrfIoO8A== X-Received: by 2002:a17:902:2969:: with SMTP id g96mr26289085plb.295.1549683544372; Fri, 08 Feb 2019 19:39:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 8 Feb 2019 19:38:44 -0800 Message-Id: <20190209033847.9014-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190209033847.9014-1-richard.henderson@linaro.org> References: <20190209033847.9014-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v3 09/12] target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR] X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Given that we mask bits properly on set, there is no reason to mask them again on get. We failed to clear the exception status bits, 0x9f, which means that the wrong value would be returned on get. Except in the (probably normal) case in which the set clears all of the bits. Simplify the code in set to also clear the RES0 bits. Signed-off-by: Richard Henderson --- target/arm/helper.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 51be3fa16f..af22274bd9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12588,7 +12588,7 @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) int i; uint32_t fpscr; =20 - fpscr =3D (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff) + fpscr =3D env->vfp.xregs[ARM_VFP_FPSCR] | (env->vfp.vec_len << 16) | (env->vfp.vec_stride << 20); =20 @@ -12630,7 +12630,7 @@ static inline int vfp_exceptbits_to_host(int target= _bits) void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) { int i; - uint32_t changed; + uint32_t changed =3D env->vfp.xregs[ARM_VFP_FPSCR]; =20 /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */ if (!cpu_isar_feature(aa64_fp16, arm_env_get_cpu(env))) { @@ -12639,12 +12639,13 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint= 32_t val) =20 /* * We don't implement trapped exception handling, so the - * trap enable bits are all RAZ/WI (not RES0!) + * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!) + * + * If we exclude the exception flags, IOC|DZC|OFC|UFC|IXC|IDC + * (which are stored in fp_status), and the other RES0 bits + * in between, then we clear all of the low 16 bits. */ - val &=3D ~(FPCR_IDE | FPCR_IXE | FPCR_UFE | FPCR_OFE | FPCR_DZE | FPCR= _IOE); - - changed =3D env->vfp.xregs[ARM_VFP_FPSCR]; - env->vfp.xregs[ARM_VFP_FPSCR] =3D (val & 0xffc8ffff); + env->vfp.xregs[ARM_VFP_FPSCR] =3D val & 0xffc80000; env->vfp.vec_len =3D (val >> 16) & 7; env->vfp.vec_stride =3D (val >> 20) & 3; =20 --=20 2.17.2