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X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH v2 1/6] target/arm: relax permission checks for HWCAP_CPUID registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Although technically not visible to userspace the kernel does make them visible via a trap and emulate ABI. We provide a new permission mask (PL0U_R) which maps to PL0_R for CONFIG_USER builds and adjust the minimum permission check accordingly. Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 12 ++++++++++++ target/arm/helper.c | 6 +++++- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a68bcc9fed..1616632dcb 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2211,6 +2211,18 @@ static inline bool cptype_valid(int cptype) #define PL0_R (0x02 | PL1_R) #define PL0_W (0x01 | PL1_W) =20 +/* + * For user-mode some registers are accessible to EL0 via a kernel + * trap-and-emulate ABI. In this case we define the read permissions + * as actually being PL0_R. However some bits of any given register + * may still be masked. + */ +#ifdef CONFIG_USER_ONLY +#define PL0U_R PL0_R +#else +#define PL0U_R PL1_R +#endif + #define PL3_RW (PL3_R | PL3_W) #define PL2_RW (PL2_R | PL2_W) #define PL1_RW (PL1_R | PL1_W) diff --git a/target/arm/helper.c b/target/arm/helper.c index d070879894..5857c0ba96 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6851,7 +6851,11 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, if (r->state !=3D ARM_CP_STATE_AA32) { int mask =3D 0; switch (r->opc1) { - case 0: case 1: case 2: + case 0: + /* min_EL EL1, but some accessible to EL0 via kernel ABI */ + mask =3D PL0U_R | PL1_RW; + break; + case 1: case 2: /* min_EL EL1 */ mask =3D PL1_RW; break; --=20 2.20.1 From nobody Wed May 1 17:03:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 154939665270911.594098475783653; Tue, 5 Feb 2019 11:57:32 -0800 (PST) Received: from localhost ([127.0.0.1]:39426 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr6qX-0001Mc-FO for importer@patchew.org; Tue, 05 Feb 2019 14:57:29 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52957) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr5zc-0007p4-8f for qemu-devel@nongnu.org; Tue, 05 Feb 2019 14:02:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gr5zZ-0004Hq-Qq for qemu-devel@nongnu.org; Tue, 05 Feb 2019 14:02:47 -0500 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:39986) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gr5zZ-00043T-Ir for qemu-devel@nongnu.org; Tue, 05 Feb 2019 14:02:45 -0500 Received: by mail-wm1-x344.google.com with SMTP id q21so38671wmc.5 for ; Tue, 05 Feb 2019 11:02:27 -0800 (PST) Received: from zen.linaroharston ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id v22sm4901871wml.37.2019.02.05.11.02.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 05 Feb 2019 11:02:25 -0800 (PST) Received: from zen.linaroharston. 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X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH v2 2/6] target/arm: expose CPUID registers to userspace X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) A number of CPUID registers are exposed to userspace by modern Linux kernels thanks to the "ARM64 CPU Feature Registers" ABI. For QEMU's user-mode emulation we don't need to emulate the kernels trap but just return the value the trap would have done. To avoid too much #ifdef hackery we process ARMCPRegInfo with a new helper (modify_arm_cp_regs) before defining the registers. The modify routine is driven by a simple data structure which describes which bits are exported and which are fixed. Signed-off-by: Alex Benn=C3=A9e --- v4 - tweak commit message - use PL0U_R instead of PL1U_R to be less confusing - more CONFIG_USER logic for special cases - mask a bunch of bits for some registers v5 - use data driven modify_arm_cp_regs --- target/arm/cpu.h | 21 ++++++++++++++++ target/arm/helper.c | 59 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 80 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1616632dcb..354df22102 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2449,6 +2449,27 @@ static inline void define_one_arm_cp_reg(ARMCPU *cpu= , const ARMCPRegInfo *regs) } const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encode= d_cp); =20 +/* + * Definition of an ARM co-processor register as viewed from + * userspace. This is used for presenting sanitised versions of + * registers to userspace when emulating the Linux AArch64 CPU + * ID/feature ABI (advertised as HWCAP_CPUID). + */ +typedef struct ARMCPRegUserSpaceInfo { + /* Name of register */ + const char *name; + + /* Only some bits are exported to user space */ + uint64_t exported_bits; + + /* Fixed bits are applied after the mask */ + uint64_t fixed_bits; +} ARMCPRegUserSpaceInfo; + +#define REGUSERINFO_SENTINEL { .name =3D NULL } + +void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *m= ods); + /* CPWriteFn that can be used to implement writes-ignored behaviour */ void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value); diff --git a/target/arm/helper.c b/target/arm/helper.c index 5857c0ba96..f90754cc11 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6103,6 +6103,30 @@ void register_cp_regs_for_features(ARMCPU *cpu) .resetvalue =3D cpu->pmceid1 }, REGINFO_SENTINEL }; +#ifdef CONFIG_USER_ONLY + ARMCPRegUserSpaceInfo v8_user_idregs[] =3D { + { .name =3D "ID_AA64PFR0_EL1", + .exported_bits =3D 0x000f000f00ff0000, + .fixed_bits =3D 0x0000000000000011 }, + { .name =3D "ID_AA64PFR1_EL1", + .exported_bits =3D 0x00000000000000f0 }, + { .name =3D "ID_AA64ZFR0_EL1" }, + { .name =3D "ID_AA64MMFR0_EL1", + .fixed_bits =3D 0x00000000ff000000 }, + { .name =3D "ID_AA64MMFR1_EL1" }, + { .name =3D "ID_AA64DFR0_EL1", + .fixed_bits =3D 0x0000000000000006 }, + { .name =3D "ID_AA64DFR1_EL1" }, + { .name =3D "ID_AA64AFR0_EL1" }, + { .name =3D "ID_AA64AFR1_EL1" }, + { .name =3D "ID_AA64ISAR0_EL1", + .exported_bits =3D 0x00fffffff0fffff0 }, + { .name =3D "ID_AA64ISAR1_EL1", + .exported_bits =3D 0x000000f0ffffffff }, + REGUSERINFO_SENTINEL + }; + modify_arm_cp_regs(v8_idregs, v8_user_idregs); +#endif /* RVBAR_EL1 is only implemented if EL1 is the highest EL */ if (!arm_feature(env, ARM_FEATURE_EL3) && !arm_feature(env, ARM_FEATURE_EL2)) { @@ -6379,6 +6403,15 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_W, .type =3D ARM_CP_NOP | ARM_CP_OVERRIDE }; +#ifdef CONFIG_USER_ONLY + ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] =3D { + { .name =3D "MIDR_EL1", + .exported_bits =3D 0x00000000ffffffff }, + { .name =3D "REVIDR_EL1" }, + REGUSERINFO_SENTINEL + }; + modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_regin= fo); +#endif if (arm_feature(env, ARM_FEATURE_OMAPCP) || arm_feature(env, ARM_FEATURE_STRONGARM)) { ARMCPRegInfo *r; @@ -6960,6 +6993,32 @@ void define_arm_cp_regs_with_opaque(ARMCPU *cpu, } } =20 +/* + * Modify ARMCPRegInfo for access from userspace. + * + * This is a data driven modification directed by + * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as + * user-space cannot alter any values and dynamic values pertaining to + * execution state are hidden from user space view anyway. + */ +void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *m= ods) +{ + const ARMCPRegUserSpaceInfo *m; + ARMCPRegInfo *r; + + for (m =3D mods; m->name; m++) { + for (r =3D regs; r->type !=3D ARM_CP_SENTINEL; r++) { + if (strcmp(r->name, m->name) =3D=3D 0) { + r->type =3D ARM_CP_CONST; + r->access =3D PL0U_R; + r->resetvalue &=3D m->exported_bits; + r->resetvalue |=3D m->fixed_bits; + break; + } + } + } +} + const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encode= d_cp) { return g_hash_table_lookup(cpregs, &encoded_cp); --=20 2.20.1 From nobody Wed May 1 17:03:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549396808801287.1024361419063; Tue, 5 Feb 2019 12:00:08 -0800 (PST) Received: from localhost ([127.0.0.1]:39483 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr6t3-0003lo-No for importer@patchew.org; Tue, 05 Feb 2019 15:00:05 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53072) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr5zg-0007vH-9U for qemu-devel@nongnu.org; Tue, 05 Feb 2019 14:02:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gr5ze-0004Nx-7D for qemu-devel@nongnu.org; Tue, 05 Feb 2019 14:02:52 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:39119) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gr5zd-00044k-PZ for qemu-devel@nongnu.org; Tue, 05 Feb 2019 14:02:49 -0500 Received: by mail-wr1-x444.google.com with SMTP id t27so4869875wra.6 for ; Tue, 05 Feb 2019 11:02:28 -0800 (PST) Received: from zen.linaroharston ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id z14sm13469930wrm.48.2019.02.05.11.02.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 05 Feb 2019 11:02:26 -0800 (PST) Received: from zen.linaroharston. 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X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH v2 3/6] target/arm: expose MPIDR_EL1 to userspace X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) As this is a single register we could expose it with a simple ifdef but we use the existing modify_arm_cp_regs mechanism for consistency. Signed-off-by: Alex Benn=C3=A9e --- target/arm/helper.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index f90754cc11..f2f868ff92 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3657,13 +3657,6 @@ static uint64_t mpidr_read(CPUARMState *env, const A= RMCPRegInfo *ri) return mpidr_read_val(env); } =20 -static const ARMCPRegInfo mpidr_cp_reginfo[] =3D { - { .name =3D "MPIDR", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 5, - .access =3D PL1_R, .readfn =3D mpidr_read, .type =3D ARM_CP_NO_RAW }, - REGINFO_SENTINEL -}; - static const ARMCPRegInfo lpae_cp_reginfo[] =3D { /* NOP AMAIR0/1 */ { .name =3D "AMAIR0", .state =3D ARM_CP_STATE_BOTH, @@ -6445,6 +6438,20 @@ void register_cp_regs_for_features(ARMCPU *cpu) } =20 if (arm_feature(env, ARM_FEATURE_MPIDR)) { + ARMCPRegInfo mpidr_cp_reginfo[] =3D { + { .name =3D "MPIDR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D = 5, + .access =3D PL1_R, .readfn =3D mpidr_read, .type =3D ARM_CP_= NO_RAW }, + REGINFO_SENTINEL + }; +#ifdef CONFIG_USER_ONLY + ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] =3D { + { .name =3D "MPIDR_EL1", + .fixed_bits =3D 0x0000000080000000 }, + REGUSERINFO_SENTINEL + }; + modify_arm_cp_regs(mpidr_cp_reginfo, mpidr_user_cp_reginfo); +#endif define_arm_cp_regs(cpu, mpidr_cp_reginfo); } =20 --=20 2.20.1 From nobody Wed May 1 17:03:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549396031963188.4338919921422; Tue, 5 Feb 2019 11:47:11 -0800 (PST) Received: from localhost ([127.0.0.1]:39177 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr6gW-0001K3-Vr for importer@patchew.org; Tue, 05 Feb 2019 14:47:09 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53004) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr5zd-0007sq-V8 for qemu-devel@nongnu.org; Tue, 05 Feb 2019 14:02:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gr5zc-0004KM-8o for qemu-devel@nongnu.org; Tue, 05 Feb 2019 14:02:49 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:46113) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gr5za-0004CJ-Ka for qemu-devel@nongnu.org; Tue, 05 Feb 2019 14:02:47 -0500 Received: by mail-wr1-x441.google.com with SMTP id l9so4813749wrt.13 for ; Tue, 05 Feb 2019 11:02:33 -0800 (PST) Received: from zen.linaroharston ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id l20sm36878159wrb.93.2019.02.05.11.02.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 05 Feb 2019 11:02:30 -0800 (PST) Received: from zen.linaroharston. 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X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH v2 4/6] target/arm: expose remaining CPUID registers as RAZ X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) There are a whole bunch more registers in the CPUID space which are currently not used but are exposed as RAZ. To avoid too much duplication we expand ARMCPRegUserSpaceInfo to understand glob patterns so we only need one entry to tweak whole ranges of registers. Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 3 +++ target/arm/helper.c | 26 +++++++++++++++++++++++--- 2 files changed, 26 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 354df22102..ae8ccc7dec 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2459,6 +2459,9 @@ typedef struct ARMCPRegUserSpaceInfo { /* Name of register */ const char *name; =20 + /* Is the name actually a glob pattern */ + bool is_glob; + /* Only some bits are exported to user space */ uint64_t exported_bits; =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index f2f868ff92..e999da165b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6103,19 +6103,27 @@ void register_cp_regs_for_features(ARMCPU *cpu) .fixed_bits =3D 0x0000000000000011 }, { .name =3D "ID_AA64PFR1_EL1", .exported_bits =3D 0x00000000000000f0 }, + { .name =3D "ID_AA64PFR*_EL1_RESERVED", + .is_glob =3D true }, { .name =3D "ID_AA64ZFR0_EL1" }, { .name =3D "ID_AA64MMFR0_EL1", .fixed_bits =3D 0x00000000ff000000 }, { .name =3D "ID_AA64MMFR1_EL1" }, + { .name =3D "ID_AA64MMFR*_EL1_RESERVED", + .is_glob =3D true }, { .name =3D "ID_AA64DFR0_EL1", .fixed_bits =3D 0x0000000000000006 }, { .name =3D "ID_AA64DFR1_EL1" }, - { .name =3D "ID_AA64AFR0_EL1" }, - { .name =3D "ID_AA64AFR1_EL1" }, + { .name =3D "ID_AA64DFR*_EL1_RESERVED", + .is_glob =3D true }, + { .name =3D "ID_AA64AFR*", + .is_glob =3D true }, { .name =3D "ID_AA64ISAR0_EL1", .exported_bits =3D 0x00fffffff0fffff0 }, { .name =3D "ID_AA64ISAR1_EL1", .exported_bits =3D 0x000000f0ffffffff }, + { .name =3D "ID_AA64ISAR*_EL1_RESERVED", + .is_glob =3D true }, REGUSERINFO_SENTINEL }; modify_arm_cp_regs(v8_idregs, v8_user_idregs); @@ -7014,8 +7022,17 @@ void modify_arm_cp_regs(ARMCPRegInfo *regs, const AR= MCPRegUserSpaceInfo *mods) ARMCPRegInfo *r; =20 for (m =3D mods; m->name; m++) { + GPatternSpec *pat =3D NULL; + if (m->is_glob) { + pat =3D g_pattern_spec_new(m->name); + } for (r =3D regs; r->type !=3D ARM_CP_SENTINEL; r++) { - if (strcmp(r->name, m->name) =3D=3D 0) { + if (pat && g_pattern_match_string(pat, r->name)) { + r->type =3D ARM_CP_CONST; + r->access =3D PL0U_R; + r->resetvalue =3D 0; + /* continue */ + } else if (strcmp(r->name, m->name) =3D=3D 0) { r->type =3D ARM_CP_CONST; r->access =3D PL0U_R; r->resetvalue &=3D m->exported_bits; @@ -7023,6 +7040,9 @@ void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARM= CPRegUserSpaceInfo *mods) break; } } + if (pat) { + g_pattern_spec_free(pat); + } } } =20 --=20 2.20.1 From nobody Wed May 1 17:03:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549397130064615.8052246350738; Tue, 5 Feb 2019 12:05:30 -0800 (PST) Received: from localhost ([127.0.0.1]:39610 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr6y9-0008FT-3j for importer@patchew.org; Tue, 05 Feb 2019 15:05:21 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52998) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr5zd-0007sk-Sw for qemu-devel@nongnu.org; Tue, 05 Feb 2019 14:02:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gr5zb-0004Ju-Ph for qemu-devel@nongnu.org; Tue, 05 Feb 2019 14:02:49 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:42116) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gr5za-0004BI-G4 for qemu-devel@nongnu.org; Tue, 05 Feb 2019 14:02:46 -0500 Received: by mail-wr1-x443.google.com with SMTP id q18so4848740wrx.9 for ; Tue, 05 Feb 2019 11:02:30 -0800 (PST) Received: from zen.linaroharston ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id v22sm4901940wml.37.2019.02.05.11.02.26 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 05 Feb 2019 11:02:28 -0800 (PST) Received: from zen.linaroharston. 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X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH v2 5/6] linux-user/elfload: enable HWCAP_CPUID for AArch64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Userspace programs should (in theory) query the ELF HWCAP before probing these registers. Now we have implemented them all make it public. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- linux-user/elfload.c | 1 + 1 file changed, 1 insertion(+) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 775a36ccdd..3a50d587ff 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -580,6 +580,7 @@ static uint32_t get_elf_hwcap(void) =20 hwcaps |=3D ARM_HWCAP_A64_FP; hwcaps |=3D ARM_HWCAP_A64_ASIMD; + hwcaps |=3D ARM_HWCAP_A64_CPUID; =20 /* probe for the extra features */ #define GET_FEATURE_ID(feat, hwcap) \ --=20 2.20.1 From nobody Wed May 1 17:03:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549396239328944.2010134862127; Tue, 5 Feb 2019 11:50:39 -0800 (PST) Received: from localhost ([127.0.0.1]:39209 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr6jo-0003k6-D6 for importer@patchew.org; Tue, 05 Feb 2019 14:50:32 -0500 Received: from eggs.gnu.org ([209.51.188.92]:52995) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr5zd-0007sh-Rn for qemu-devel@nongnu.org; Tue, 05 Feb 2019 14:02:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gr5zb-0004Iq-41 for qemu-devel@nongnu.org; Tue, 05 Feb 2019 14:02:49 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:36470) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gr5zZ-00047p-Nu for qemu-devel@nongnu.org; Tue, 05 Feb 2019 14:02:46 -0500 Received: by mail-wr1-x444.google.com with SMTP id z3so4897379wrv.3 for ; Tue, 05 Feb 2019 11:02:29 -0800 (PST) Received: from zen.linaroharston ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id h135sm19647406wmd.21.2019.02.05.11.02.26 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 05 Feb 2019 11:02:26 -0800 (PST) Received: from zen.linaroharston. (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id C4F1C1FF86; Tue, 5 Feb 2019 19:02:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BNzh66bB0nnDDrV+CbNUUVwPZKwG8xcxSjnQQStKqsw=; b=BPSbXE2xLCn/CLUyxP81IaTGrwC8vfwknc6vEJhd0OoVBTz0ZphrrJMKW7TGSuslbh bbio1Mzy7ak8VW6VdneHvBDZVnb25zD7+Rgou0xF6lS0/jCxwewQP5UC+kD7+FSNb6NA 8gwlLESOOFHwHvjP/wpORGnjX2yKZY9h1tL220N1ISQsUsNyINHgHuDHhBGiFTcs7f+0 WGaTinFVVahvfziXC5txwUcHfF/fjr8TXOGntHZnBAoPt8mI6N8iKcxuFaSzECToBQZ+ /w6QGrwOysd07LfLMurGDGV5i371E8lvXiERrj8VKH78aI3iLfqX+qDXNZ0JbpwDE0Mt 1klA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BNzh66bB0nnDDrV+CbNUUVwPZKwG8xcxSjnQQStKqsw=; b=AEqQ0C5XL/tRdnvhvZjoCWYQs3EoQIotVagI9E6XLAZfwbCBYKTtJCpYt7dR2mfXpU R0SaMI3jhn9JnpAbGbrhoQ/vbfhRKQXc1kxirrH1DdZzZPO4hFU2qGOkl1+laPHYovA5 qLM+emTBL48xeS3sGm5+17meC2k6GrX76nR+NFfQa9BQH7eyWbpRGTZfv68SkKrVc/34 VSxK1nZ6UQ6pHfoIWufJEvO5DlAnK07lgJcHTdB9ZNkqe3OqOoRO81SSwA4IOyS4kOt1 y5/NpBr5af1NdHqk+ci6sUXO+N6CnAy6KeVxw9TzjRaxrGwrwQW1zPnII38nM7GmpQuy P5ZQ== X-Gm-Message-State: AHQUAuaGPmvaEn4l8TN4Kx+GeF4vNgNEzR3rzEeECzIrGbMSOgXicvMX xk9vo/fbZ2npC2MChK9cx5c+Xg== X-Google-Smtp-Source: AHgI3IZC+r+/j2we20mpsx9WQT3qKAJdgMHHSM4qH2ihVqdJJjGN94fceZLZhUonPcdBABlvs2qeeQ== X-Received: by 2002:adf:f8cf:: with SMTP id f15mr4758120wrq.265.1549393348937; Tue, 05 Feb 2019 11:02:28 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Tue, 5 Feb 2019 19:02:24 +0000 Message-Id: <20190205190224.2198-7-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190205190224.2198-1-alex.bennee@linaro.org> References: <20190205190224.2198-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH v2 6/6] tests/tcg/aarch64: userspace system register test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) This tests a bunch of registers that the kernel allows userspace to read including the CPUID registers. Signed-off-by: Alex Benn=C3=A9e --- v4 - also test for extra bits that shouldn't be exposed v5 - work around missing HWCAP_CPUID on older compilers - add more registers to test and some aarch32 regs - add more details commentary - fix up the masks (add a helper to help keep track) - add copyright header --- tests/tcg/aarch64/Makefile.target | 4 +- tests/tcg/aarch64/sysregs.c | 172 ++++++++++++++++++++++++++++++ 2 files changed, 175 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/aarch64/sysregs.c diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile= .target index 08c45b8470..fb40896e7b 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -7,11 +7,13 @@ VPATH +=3D $(AARCH64_SRC) =20 # we don't build any of the ARM tests AARCH64_TESTS=3D$(filter-out $(ARM_TESTS), $(TESTS)) -AARCH64_TESTS+=3Dfcvt +AARCH64_TESTS+=3Dfcvt sysregs TESTS:=3D$(AARCH64_TESTS) =20 fcvt: LDFLAGS+=3D-lm =20 +sysregs: CFLAGS+=3D-march=3Darmv8.1-a+sve + run-fcvt: fcvt $(call run-test,$<,$(QEMU) $<, "$< on $(TARGET_NAME)") $(call diff-out,$<,$(AARCH64_SRC)/fcvt.ref) diff --git a/tests/tcg/aarch64/sysregs.c b/tests/tcg/aarch64/sysregs.c new file mode 100644 index 0000000000..40cf8d2877 --- /dev/null +++ b/tests/tcg/aarch64/sysregs.c @@ -0,0 +1,172 @@ +/* + * Check emulated system register access for linux-user mode. + * + * See: https://www.kernel.org/doc/Documentation/arm64/cpu-feature-registe= rs.txt + * + * Copyright (c) 2019 Linaro + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include +#include +#include + +#ifndef HWCAP_CPUID +#define HWCAP_CPUID (1 << 11) +#endif + +int failed_bit_count; + +/* Read and print system register `id' value */ +#define get_cpu_reg(id) ({ \ + unsigned long __val =3D 0xdeadbeef; \ + asm("mrs %0, "#id : "=3Dr" (__val)); \ + printf("%-20s: 0x%016lx\n", #id, __val); \ + __val; \ + }) + +/* As above but also check no bits outside of `mask' are set*/ +#define get_cpu_reg_check_mask(id, mask) ({ \ + unsigned long __cval =3D get_cpu_reg(id); \ + unsigned long __extra =3D __cval & ~mask; \ + if (__extra) { \ + printf("%-20s: 0x%016lx\n", " !!extra bits!!", __extra); = \ + failed_bit_count++; \ + } \ +}) + +/* As above but check RAZ */ +#define get_cpu_reg_check_zero(id) ({ \ + unsigned long __val =3D 0xdeadbeef; \ + asm("mrs %0, "#id : "=3Dr" (__val)); \ + if (__val) { \ + printf("%-20s: 0x%016lx (not RAZ!)\n", #id, __val); = \ + failed_bit_count++; \ + } \ +}) + +/* Chunk up mask into 63:48, 47:32, 31:16, 15:0 to ease counting */ +#define _m(a, b, c, d) (0x ## a ## b ## c ## d ##ULL) + +bool should_fail; +int should_fail_count; +int should_not_fail_count; +uintptr_t failed_pc[10]; + +void sigill_handler(int signo, siginfo_t *si, void *data) +{ + ucontext_t *uc =3D (ucontext_t *)data; + + if (should_fail) { + should_fail_count++; + } else { + uintptr_t pc =3D (uintptr_t) uc->uc_mcontext.pc; + failed_pc[should_not_fail_count++] =3D pc; + } + uc->uc_mcontext.pc +=3D 4; +} + +int main(void) +{ + struct sigaction sa; + + /* Hook in a SIGILL handler */ + memset(&sa, 0, sizeof(struct sigaction)); + sa.sa_flags =3D SA_SIGINFO; + sa.sa_sigaction =3D &sigill_handler; + sigemptyset(&sa.sa_mask); + + if (sigaction(SIGILL, &sa, 0) !=3D 0) { + perror("sigaction"); + return 1; + } + + /* Counter values have been exposed since Linux 4.12 */ + printf("Checking Counter registers\n"); + + get_cpu_reg(ctr_el0); + get_cpu_reg(cntvct_el0); + get_cpu_reg(cntfrq_el0); + + /* HWCAP_CPUID indicates we can read feature registers, since Linux 4.= 11 */ + if (!(getauxval(AT_HWCAP) & HWCAP_CPUID)) { + printf("CPUID registers unavailable\n"); + return 1; + } else { + printf("Checking CPUID registers\n"); + } + + /* + * Some registers only expose some bits to user-space. Anything + * that is IMPDEF is exported as 0 to user-space. The _mask checks + * assert no extra bits are set. + * + * This check is *not* comprehensive as some fields are set to + * minimum valid fields - for the purposes of this check allowed + * to have non-zero values. + */ + get_cpu_reg_check_mask(id_aa64isar0_el1, _m(00ff,ffff,f0ff,fff0)); + get_cpu_reg_check_mask(id_aa64isar1_el1, _m(0000,00f0,ffff,ffff)); + /* TGran4 & TGran64 as pegged to -1 */ + get_cpu_reg_check_mask(id_aa64mmfr0_el1, _m(0000,0000,ff00,0000)); + get_cpu_reg_check_zero(id_aa64mmfr1_el1); + /* EL1/EL0 reported as AA64 only */ + get_cpu_reg_check_mask(id_aa64pfr0_el1, _m(000f,000f,00ff,0011)); + get_cpu_reg_check_mask(id_aa64pfr1_el1, _m(0000,0000,0000,00f0)); + /* all hidden, DebugVer fixed to 0x6 (ARMv8 debug architecture) */ + get_cpu_reg_check_mask(id_aa64dfr0_el1, _m(0000,0000,0000,0006)); + get_cpu_reg_check_zero(id_aa64dfr1_el1); + get_cpu_reg_check_zero(id_aa64zfr0_el1); + + get_cpu_reg_check_zero(id_aa64afr0_el1); + get_cpu_reg_check_zero(id_aa64afr1_el1); + + get_cpu_reg_check_mask(midr_el1, _m(0000,0000,ffff,ffff)); + /* mpidr sets bit 31, everything else hidden */ + get_cpu_reg_check_mask(mpidr_el1, _m(0000,0000,8000,0000)); + /* REVIDR is all IMPDEF so should be all zeros to user-space */ + get_cpu_reg_check_zero(revidr_el1); + + /* + * There are a block of more registers that are RAZ in the rest of + * the Op0=3D3, Op1=3D0, CRn=3D0, CRm=3D0,4,5,6,7 space. However for + * brevity we don't check stuff that is currently un-allocated + * here. Feel free to add them ;-) + */ + + printf("Remaining registers should fail\n"); + should_fail =3D true; + + /* Unexposed register access causes SIGILL */ + get_cpu_reg(id_mmfr0_el1); + get_cpu_reg(id_mmfr1_el1); + get_cpu_reg(id_mmfr2_el1); + get_cpu_reg(id_mmfr3_el1); + + get_cpu_reg(mvfr0_el1); + get_cpu_reg(mvfr1_el1); + + if (should_not_fail_count > 0) { + int i; + for (i =3D 0; i < should_not_fail_count; i++) { + uintptr_t pc =3D failed_pc[i]; + uint32_t insn =3D *(uint32_t *) pc; + printf("insn %#x @ %#lx unexpected FAIL\n", insn, pc); + } + return 1; + } + + if (failed_bit_count > 0) { + printf("Extra information leaked to user-space!\n"); + return 1; + } + + return should_fail_count =3D=3D 6 ? 0 : 1; +} --=20 2.20.1