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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id 129sm26662086wmd.18.2019.02.05.10.12.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Feb 2019 10:12:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=M98p1uZhiAqbZbizsbvMNJKrarrSLsz1eMgBMbbzlI4=; b=ifmSOh3axv0hFEA807/rZPTgmj8qz8kbQpvEHX1HaeeWtmc6Rd//ONjltjyLVCjgTS 2G1UjXrBfvAla0JjxS30OG6VD1DgS0u+h1IXFP7t0X12pdGNRNAfi+x6L5vd39HTJxia klbRoUT6a0gvpF9eHk8w1coG2Cr/x9aptfzOdhR7+CIRu1xgakYYgUaNctKNCZEfMHYw sLoohNmJseUEAU+975kqY/Imzb9YqIFsSVNPFxfgOV+poYAKctG+8YBMQA+Z0xGZzlmx TymB6r+rnyWtVbfx7FL8Qc4pNkF4DORqXQaUrmMbZs5v/Z/8TPfrie/jkmxEMhV8ibtz C1aQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=M98p1uZhiAqbZbizsbvMNJKrarrSLsz1eMgBMbbzlI4=; b=J/1eTp063ddjCZNVYI7r4wa4Ezb6bCMqzS1lDpJ8Ruc/COpduS5pM9bIvqH7Bdr4yb oTZ3rUdWUgsZSO0QuzpChM5v5SO8fsmnVJAGgnevUywjn8EHV78md8hb6lgHXjlFu66u Sfn9qGnH18TLjvIUKeUDtL8GVNm3oPiSSL9N17z3FaeMwoCWPTOiLOYI3LsRlaTrhIFY HFThwkC/1gTGGjgAUgxifc3jmS6bcxxMk016YtMIPMzIMLHYUkaYJ2+l6jf3NN/zr4Hf pDMx+oQUH5PRT3hUcn+1F0ZRPFRtmYepYKMj/v1C8FJDA97Q99+adHy/f/Z7PjJ1aA4y 4OZQ== X-Gm-Message-State: AHQUAuZqJcmVyAKORAHe/OnbO+1wzVdTLTbFK6gZWEVgT1NSpj1EMh39 SH/u+sE35SbI/tOCidqBNxqWGw== X-Google-Smtp-Source: AHgI3IZ11QO+hzcvhAKq2xk8SySTzUytQ6gXaJu8lQIa26+M13MtsO9ye3QnyDZNXe2gh3HtUQJiCg== X-Received: by 2002:a1c:4b0b:: with SMTP id y11mr4903009wma.137.1549390341018; Tue, 05 Feb 2019 10:12:21 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 5 Feb 2019 18:12:18 +0000 Message-Id: <20190205181218.8995-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH] target/arm: Implement HACR_EL2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" HACR_EL2 is a register with IMPDEF behaviour, which allows implementation specific trapping to EL2. Implement it as RAZ/WI, since QEMU's implementation has no extra traps. This also matches what h/w implementations like Cortex-A53 and A57 do. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index d070879894c..f09f815578e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4434,6 +4434,9 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] =3D= { .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "HACR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 7, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "ESR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 2, .opc2 =3D 0, .access =3D PL2_RW, @@ -4666,6 +4669,9 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.hcr_= el2), .writefn =3D hcr_writelow }, + { .name =3D "HACR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 7, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "ELR_EL2", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_ALIAS, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 0, .opc2 =3D 1, --=20 2.20.1