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X-Received-From: 2a00:1450:4864:20::42c Subject: [Qemu-devel] [PULL 03/22] target/arm: Add BT and BTYPE to tb->flags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20190128223118.5255-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 ++ target/arm/translate.h | 4 ++++ target/arm/helper.c | 22 +++++++++++++++------- target/arm/translate-a64.c | 2 ++ 4 files changed, 23 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 58f99985c24..1ff7197efd5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3052,6 +3052,8 @@ FIELD(TBFLAG_A64, TBII, 0, 2) FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) +FIELD(TBFLAG_A64, BT, 9, 1) +FIELD(TBFLAG_A64, BTYPE, 10, 2) =20 static inline bool bswap_code(bool sctlr_b) { diff --git a/target/arm/translate.h b/target/arm/translate.h index bb37d35741c..3d5e8bacacb 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -69,6 +69,10 @@ typedef struct DisasContext { bool ss_same_el; /* True if v8.3-PAuth is active. */ bool pauth_active; + /* True with v8.5-BTI and SCTLR_ELx.BT* set. */ + bool bt; + /* A copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. */ + uint8_t btype; /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ int c15_cpar; /* TCG op of the current insn_start. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index d070879894c..45ba678a7df 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13735,6 +13735,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, =20 if (is_a64(env)) { ARMCPU *cpu =3D arm_env_get_cpu(env); + uint64_t sctlr; =20 *pc =3D env->pc; flags =3D FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); @@ -13779,6 +13780,12 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target= _ulong *pc, flags =3D FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); } =20 + if (current_el =3D=3D 0) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + sctlr =3D env->cp15.sctlr_el[1]; + } else { + sctlr =3D env->cp15.sctlr_el[current_el]; + } if (cpu_isar_feature(aa64_pauth, cpu)) { /* * In order to save space in flags, we record only whether @@ -13786,17 +13793,18 @@ void cpu_get_tb_cpu_state(CPUARMState *env, targe= t_ulong *pc, * a nop, or "active" when some action must be performed. * The decision of which action to take is left to a helper. */ - uint64_t sctlr; - if (current_el =3D=3D 0) { - /* FIXME: ARMv8.1-VHE S2 translation regime. */ - sctlr =3D env->cp15.sctlr_el[1]; - } else { - sctlr =3D env->cp15.sctlr_el[current_el]; - } if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB= )) { flags =3D FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1); } } + + if (cpu_isar_feature(aa64_bti, cpu)) { + /* Note that SCTLR_EL[23].BT =3D=3D SCTLR_BT1. */ + if (sctlr & (current_el =3D=3D 0 ? SCTLR_BT0 : SCTLR_BT1)) { + flags =3D FIELD_DP32(flags, TBFLAG_A64, BT, 1); + } + flags =3D FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); + } } else { *pc =3D env->regs[15]; flags =3D FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 0b94d9455b7..a92fd433783 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -13840,6 +13840,8 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->sve_excp_el =3D FIELD_EX32(tb_flags, TBFLAG_A64, SVEEXC_EL); dc->sve_len =3D (FIELD_EX32(tb_flags, TBFLAG_A64, ZCR_LEN) + 1) * 16; dc->pauth_active =3D FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE); + dc->bt =3D FIELD_EX32(tb_flags, TBFLAG_A64, BT); + dc->btype =3D FIELD_EX32(tb_flags, TBFLAG_A64, BTYPE); dc->vec_len =3D 0; dc->vec_stride =3D 0; dc->cp_regs =3D arm_cpu->cp_regs; --=20 2.20.1