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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm5583164wmf.5.2019.02.05.09.05.14 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Feb 2019 09:05:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=MSVX//ZRO07YmKtsr58HHkkX8CWwgbGiDqk5EHr94gg=; b=fOEiUBhV0HiqLELVUSxrucaODbHiwPiiE//jjsK6xEU05/q4A1PuMVTglrfQOqxO/F CIQnz+jP3z9ct9aH2RVtDl+o+5QjVntQ1wUZIRzFyHtPgWvesq/DeFaWOac27J6bDhTX /4MT/SsEMCKNvbj/nDVNenVHaPoIfA0DTdzHPf5f4jVIEVCTbUJ34IeIJbmcU7fsA+BA fZWjH+L5LehpZBtrB4mZsCerl96whzIfgkLwR9dSA3v6W0jyFN/qiaavNbDbY/uFQ1ET zEjTEKU9RUYQ+8tIsqKeEFSnZW0mwjppH0ltDCkS+U6XXrsN0uvGv5WvkcSdTKJUuLdk nQ9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MSVX//ZRO07YmKtsr58HHkkX8CWwgbGiDqk5EHr94gg=; b=IcgDN+7/YVLPlGUPGq4K3AjqV4WCbSnuzaGb9Sopz89/+3KZSk1Xq8UPMIjygxpHwH 0Hbk01EhaJQUqEL7nv+bxc1WqjHCSOmEbuUGtmSNaR6P96V4nfmidVrmIOUJHUxwZM7V wFigRpv+gJQjxaNjk4teZ1szd/0oXxrkFomI78HVcIOCAVuO2FdJj3HoltKl1lQp+fO9 0otTn0rd0SiF3rEFsM2AqeEeLlem6Hx9qm/UIFrBKjldqqb/ozkSDko4s7O0xb1Zv8L0 G/HYPeXkW6blY8BtgI0ASudR9gSVU9KEsRb+jMLBtT9PXT5MiCuLWy5YY1ID80y+fR7V OAuw== X-Gm-Message-State: AHQUAuYV4/2J0YGGN7JJqlNBtaDCZSPcpECgtyIBt6hw1pCKkFiSrgF/ x+Byc2j8nvDy6tL7hUBTG5ABcC6pOtVAVg== X-Google-Smtp-Source: AHgI3IZWFw7B6KKWDz8L0sqGD8IN3jD6ZfF5Qkaue1PNcqRJhQuZ1ycTlllo8Hr0HPPt0zkeVKntmQ== X-Received: by 2002:adf:8b4d:: with SMTP id v13mr4298883wra.282.1549386316163; Tue, 05 Feb 2019 09:05:16 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 5 Feb 2019 17:04:50 +0000 Message-Id: <20190205170510.21984-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190205170510.21984-1-peter.maydell@linaro.org> References: <20190205170510.21984-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PULL 02/22] target/arm: Add PSTATE.BTYPE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Place this in its own field within ENV, as that will make it easier to reset from within TCG generated code. With the change to pstate_read/write, exception entry and return are automatically handled. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20190128223118.5255-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 8 ++++++-- target/arm/translate-a64.c | 3 +++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0c7ea39f1ae..58f99985c24 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -234,6 +234,7 @@ typedef struct CPUARMState { * semantics as for AArch32, as described in the comments on each f= ield) * nRW (also known as M[4]) is kept, inverted, in env->aarch64 * DAIF (exception masks) are kept in env->daif + * BTYPE is kept in env->btype * all other bits are stored in their correct places in env->pstate */ uint32_t pstate; @@ -263,6 +264,7 @@ typedef struct CPUARMState { uint32_t GE; /* cpsr[19:16] */ uint32_t thumb; /* cpsr[5]. 0 =3D arm mode, 1 =3D thumb mode. */ uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ + uint32_t btype; /* BTI branch type. spsr[11:10]. */ uint64_t daif; /* exception masks, in the bits they are in PSTATE */ =20 uint64_t elr_el[4]; /* AArch64 exception link regs */ @@ -1206,6 +1208,7 @@ void pmu_init(ARMCPU *cpu); #define PSTATE_I (1U << 7) #define PSTATE_A (1U << 8) #define PSTATE_D (1U << 9) +#define PSTATE_BTYPE (3U << 10) #define PSTATE_IL (1U << 20) #define PSTATE_SS (1U << 21) #define PSTATE_V (1U << 28) @@ -1214,7 +1217,7 @@ void pmu_init(ARMCPU *cpu); #define PSTATE_N (1U << 31) #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) -#define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF) +#define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) /* Mode values for AArch64 */ #define PSTATE_MODE_EL3h 13 #define PSTATE_MODE_EL3t 12 @@ -1246,7 +1249,7 @@ static inline uint32_t pstate_read(CPUARMState *env) ZF =3D (env->ZF =3D=3D 0); return (env->NF & 0x80000000) | (ZF << 30) | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) - | env->pstate | env->daif; + | env->pstate | env->daif | (env->btype << 10); } =20 static inline void pstate_write(CPUARMState *env, uint32_t val) @@ -1256,6 +1259,7 @@ static inline void pstate_write(CPUARMState *env, uin= t32_t val) env->CF =3D (val >> 29) & 1; env->VF =3D (val << 3) & 0x80000000; env->daif =3D val & PSTATE_DAIF; + env->btype =3D (val >> 10) & 3; env->pstate =3D val & ~CACHED_PSTATE_BITS; } =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a1997e3ae28..0b94d9455b7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -163,6 +163,9 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, el, psr & PSTATE_SP ? 'h' : 't'); =20 + if (cpu_isar_feature(aa64_bti, cpu)) { + cpu_fprintf(f, " BTYPE=3D%d", (psr & PSTATE_BTYPE) >> 10); + } if (!(flags & CPU_DUMP_FPU)) { cpu_fprintf(f, "\n"); return; --=20 2.20.1