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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm5583164wmf.5.2019.02.05.09.05.32 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Feb 2019 09:05:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=qT5ac9Xbqwc5p5e64FE+VEBcJomIxNAlRbw65oVsF2E=; b=kYR3qKeEWq7473tqPvfNiW1HwiZ3G43kIUAo/WRU2w8KhhCQv8nu2SaZfGC5vsoF+C QeQOytQZO0kOtI20Fj4/ph4Hdf0AUcE9YWG5UEEpPLTsmjq+T2YFp4ndfpFrvRRRfP+a vBn4Bw9ofw8xN8FfZmOZPugnUQiCjQNkbSD3MVdIVRLbqvH5PKRnlSIzSLVpkp4QzDIc 4Q5ZohI81wNvZQekC/iUzciKOh22tTrQJ0jtoXXia9PX5dP4tQbpT5H2gpN2E9EnR4zZ qAnDhUJTLzCVFzY8i4GYnnRIGTzLd87wLy6L2FYYO0S5nH5CJ/JYdf5IH5/jhJrlBTXF GPyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qT5ac9Xbqwc5p5e64FE+VEBcJomIxNAlRbw65oVsF2E=; b=YnedbKPcG4qpnJxJWpQWnll818jhk7Hq3TmRhyZODMq2/xFdqyOY9hYunDRDvbRxnF AmBKxm6jYKjxiAvOHSmVCl1f4PLm+23CmWqX7vklZ2QrwRJiqNgQyXuzZyIoNwo8kx5c XPRqNsHseIOLQlA6Xgn2NXROLrzd+8uJMCbhv1NpdF7YilK4ejrhbwQSnBTwXIxj7mQy 7ehEVm1azvvjBZlLkw+bwuWCpcoqbxu8W6gSnBQEybeMxN+0d1XkMkFZFelS+3vAeqpc 871s6VLODKJamyT/IoH2ofXl5jAjxx//YtgFx3H3Ykj0o9DRoO4RxWR0MYDWxiwozeud 2P7g== X-Gm-Message-State: AHQUAubgucso+maLr1At0gOgTYLehdYkX42oemp0HpaDYiqRUzrbcSIp fiDwTZc5wGs9EhzUBdcK9SRh5+SlSkZGCA== X-Google-Smtp-Source: AHgI3Ib3uIKUtqOfZrOfZXArHh7f2GDe39bsme3va5c++TpmzbRWoesd2wUpfKqq4CBJSFZQ2W16ZA== X-Received: by 2002:adf:f009:: with SMTP id j9mr4385494wro.170.1549386334350; Tue, 05 Feb 2019 09:05:34 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 5 Feb 2019 17:05:02 +0000 Message-Id: <20190205170510.21984-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190205170510.21984-1-peter.maydell@linaro.org> References: <20190205170510.21984-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42c Subject: [Qemu-devel] [PULL 14/22] target/arm: Compute TB_FLAGS for TBI for user-only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Enables, but does not turn on, TBI for CONFIG_USER_ONLY. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20190204132126.3255-4-richard.henderson@linaro.org [PMM: adjusted #ifdeffery to placate clang, which otherwise complains about static functions that are unused in the CONFIG_USER_ONLY build] Signed-off-by: Peter Maydell --- target/arm/internals.h | 21 -------------------- target/arm/helper.c | 45 ++++++++++++++++++++++-------------------- 2 files changed, 24 insertions(+), 42 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index d01a3f9f44b..a4bd1becb75 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -963,30 +963,9 @@ typedef struct ARMVAParameters { bool using64k : 1; } ARMVAParameters; =20 -#ifdef CONFIG_USER_ONLY -static inline ARMVAParameters aa64_va_parameters_both(CPUARMState *env, - uint64_t va, - ARMMMUIdx mmu_idx) -{ - return (ARMVAParameters) { - /* 48-bit address space */ - .tsz =3D 16, - /* We can't handle tagged addresses properly in user-only mode */ - .tbi =3D false, - }; -} - -static inline ARMVAParameters aa64_va_parameters(CPUARMState *env, - uint64_t va, - ARMMMUIdx mmu_idx, bool d= ata) -{ - return aa64_va_parameters_both(env, va, mmu_idx); -} -#else ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx); ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data); -#endif =20 #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index 25d8ec38f8e..aaf5b0cd7ab 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7197,7 +7197,7 @@ uint32_t HELPER(rbit)(uint32_t x) return revbit32(x); } =20 -#if defined(CONFIG_USER_ONLY) +#ifdef CONFIG_USER_ONLY =20 /* These should probably raise undefined insn exceptions. */ void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) @@ -9571,6 +9571,7 @@ void arm_cpu_do_interrupt(CPUState *cs) cs->interrupt_request |=3D CPU_INTERRUPT_EXITTB; } } +#endif /* !CONFIG_USER_ONLY */ =20 /* Return the exception level which controls this address translation regi= me */ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) @@ -9600,6 +9601,8 @@ static inline uint32_t regime_el(CPUARMState *env, AR= MMMUIdx mmu_idx) } } =20 +#ifndef CONFIG_USER_ONLY + /* Return the SCTLR value which controls this address translation regime */ static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) { @@ -9655,6 +9658,22 @@ static inline bool regime_translation_big_endian(CPU= ARMState *env, return (regime_sctlr(env, mmu_idx) & SCTLR_EE) !=3D 0; } =20 +/* Return the TTBR associated with this translation regime */ +static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, + int ttbrn) +{ + if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { + return env->cp15.vttbr_el2; + } + if (ttbrn =3D=3D 0) { + return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; + } else { + return env->cp15.ttbr1_el[regime_el(env, mmu_idx)]; + } +} + +#endif /* !CONFIG_USER_ONLY */ + /* Return the TCR controlling this translation regime */ static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) { @@ -9675,20 +9694,6 @@ static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mm= u_idx) return mmu_idx; } =20 -/* Return the TTBR associated with this translation regime */ -static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, - int ttbrn) -{ - if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { - return env->cp15.vttbr_el2; - } - if (ttbrn =3D=3D 0) { - return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; - } else { - return env->cp15.ttbr1_el[regime_el(env, mmu_idx)]; - } -} - /* Return true if the translation regime is using LPAE format page tables = */ static inline bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) @@ -9714,6 +9719,7 @@ bool arm_s1_regime_using_lpae_format(CPUARMState *env= , ARMMMUIdx mmu_idx) return regime_using_lpae_format(env, mmu_idx); } =20 +#ifndef CONFIG_USER_ONLY static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { @@ -10419,6 +10425,7 @@ static uint8_t convert_stage2_attrs(CPUARMState *en= v, uint8_t s2attrs) =20 return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint; } +#endif /* !CONFIG_USER_ONLY */ =20 ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx) @@ -10490,6 +10497,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env= , uint64_t va, return ret; } =20 +#ifndef CONFIG_USER_ONLY static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, ARMMMUIdx mmu_idx) { @@ -13746,11 +13754,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target= _ulong *pc, *pc =3D env->pc; flags =3D FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); =20 -#ifndef CONFIG_USER_ONLY - /* - * Get control bits for tagged addresses. Note that the - * translator only uses this for instruction addresses. - */ + /* Get control bits for tagged addresses. */ { ARMMMUIdx stage1 =3D stage_1_mmu_idx(mmu_idx); ARMVAParameters p0 =3D aa64_va_parameters_both(env, 0, stage1); @@ -13769,7 +13773,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, flags =3D FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); flags =3D FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); } -#endif =20 if (cpu_isar_feature(aa64_sve, cpu)) { int sve_el =3D sve_exception_el(env, current_el); --=20 2.20.1