From nobody Sun May 5 05:05:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549387370218736.009604831306; Tue, 5 Feb 2019 09:22:50 -0800 (PST) Received: from localhost ([127.0.0.1]:35381 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4Qm-0007PB-50 for importer@patchew.org; Tue, 05 Feb 2019 12:22:44 -0500 Received: from eggs.gnu.org ([209.51.188.92]:35887) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4AR-0001tt-W6 for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gr4AQ-0000YB-RG for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:51 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:39145) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gr4AL-0000JD-9d for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:48 -0500 Received: by mail-wm1-x334.google.com with SMTP id y8so4480033wmi.4 for ; Tue, 05 Feb 2019 09:05:16 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm5583164wmf.5.2019.02.05.09.05.13 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Feb 2019 09:05:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Phfuh8h4FZ1vAFL/MN93RvHaAK2E1TvTgJVPc6hRE50=; b=ap/qLUdof+d2leNY3RznmnbuSYfu+wcqiqL/TEa2Q+eBpnD3leU3fikiinch2eYeTF iwGLledNsD7XmDiJnyaKKEdPZtzF8ckUW6BmF++W7DWnAFhv8brXPVftk4JzjiWl0eUC 0mI9OxT8aVUhL1hhdrLBN+FaIPudEYkSWHfuhncrSnbHJuJ1P5U3ke1J2f4xyrDozICO 8G2/WpzVF6jlMtG6K1AGad54j+/1j7pFX71qGkrzNN5Xs4YJOM3cafk76CE71GcOvSkF nQOiJGeRfX0QTsznNBEaXujW3M+vpH7HV+C6tNrJn4T0CCzJMeklMe35QTXZkEmxNSFz hLAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Phfuh8h4FZ1vAFL/MN93RvHaAK2E1TvTgJVPc6hRE50=; b=XXMGDm7KAG/gMjfkgaS53iJZr57IXTZBuK3igEZojaRoa6AzklcReXZEr0GQ1xeFng oKcDnLEAenFehRjG5CdJ1qzcXxG0X7bQnX0wm1nygAHNuoFtmkM2ulkW2fqVmeZHeyes R/OuVgsHzddC0+P7GsZmLdbC6yN4XUJqeP0mKY6KdVT+M+biI8X3OrXFlF0OFzXgxJYP I0oCOyYVaPQw6BfcORNcTW6OcldlxKSXpK94qbkCbH906yH1/nCfKVmld+ZG+CPIkbro fZ5ima9kWL1oXNO1Lg3gSvHCNNvXD1iQ6HE5ScPAvp6wZZxj5toX4VmVxbt6pF+yV/LY PoTw== X-Gm-Message-State: AHQUAub/AkcmHj7AY29AEn7gPUHmyLyto0FwVXWiwep1WchAG/e6uTFw SpDJNL97DPgUodaXNflV7EVQXjn2jyObOg== X-Google-Smtp-Source: AHgI3IZLofgi4b9tOl71/wxHILhppgo0kookDBisfG1sg5XR7KueknFx2FZYhrpyy3/PQw5R7v5B6A== X-Received: by 2002:a1c:414:: with SMTP id 20mr4590262wme.67.1549386314825; Tue, 05 Feb 2019 09:05:14 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 5 Feb 2019 17:04:49 +0000 Message-Id: <20190205170510.21984-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190205170510.21984-1-peter.maydell@linaro.org> References: <20190205170510.21984-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::334 Subject: [Qemu-devel] [PULL 01/22] target/arm: Introduce isar_feature_aa64_bti X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Also create field definitions for id_aa64pfr1 from ARMv8.5. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20190128223118.5255-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a68bcc9fedb..0c7ea39f1ae 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1681,6 +1681,11 @@ FIELD(ID_AA64PFR0, GIC, 24, 4) FIELD(ID_AA64PFR0, RAS, 28, 4) FIELD(ID_AA64PFR0, SVE, 32, 4) =20 +FIELD(ID_AA64PFR1, BT, 0, 4) +FIELD(ID_AA64PFR1, SBSS, 4, 4) +FIELD(ID_AA64PFR1, MTE, 8, 4) +FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) + FIELD(ID_AA64MMFR0, PARANGE, 0, 4) FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) FIELD(ID_AA64MMFR0, BIGEND, 8, 4) @@ -3328,6 +3333,11 @@ static inline bool isar_feature_aa64_lor(const ARMIS= ARegisters *id) return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) !=3D 0; } =20 +static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) !=3D 0; +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ --=20 2.20.1 From nobody Sun May 5 05:05:30 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 15493889376211018.0599082650637; Tue, 5 Feb 2019 09:48:57 -0800 (PST) Received: from localhost ([127.0.0.1]:35894 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4py-0003uH-Ap for importer@patchew.org; Tue, 05 Feb 2019 12:48:46 -0500 Received: from eggs.gnu.org ([209.51.188.92]:35793) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4AK-0001nk-If for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gr4AC-0000RQ-HG for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:40 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:39435) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gr4A8-0000JU-DR for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:34 -0500 Received: by mail-wr1-x444.google.com with SMTP id t27so4455709wra.6 for ; Tue, 05 Feb 2019 09:05:17 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm5583164wmf.5.2019.02.05.09.05.14 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Feb 2019 09:05:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=MSVX//ZRO07YmKtsr58HHkkX8CWwgbGiDqk5EHr94gg=; b=fOEiUBhV0HiqLELVUSxrucaODbHiwPiiE//jjsK6xEU05/q4A1PuMVTglrfQOqxO/F CIQnz+jP3z9ct9aH2RVtDl+o+5QjVntQ1wUZIRzFyHtPgWvesq/DeFaWOac27J6bDhTX /4MT/SsEMCKNvbj/nDVNenVHaPoIfA0DTdzHPf5f4jVIEVCTbUJ34IeIJbmcU7fsA+BA fZWjH+L5LehpZBtrB4mZsCerl96whzIfgkLwR9dSA3v6W0jyFN/qiaavNbDbY/uFQ1ET zEjTEKU9RUYQ+8tIsqKeEFSnZW0mwjppH0ltDCkS+U6XXrsN0uvGv5WvkcSdTKJUuLdk nQ9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MSVX//ZRO07YmKtsr58HHkkX8CWwgbGiDqk5EHr94gg=; b=IcgDN+7/YVLPlGUPGq4K3AjqV4WCbSnuzaGb9Sopz89/+3KZSk1Xq8UPMIjygxpHwH 0Hbk01EhaJQUqEL7nv+bxc1WqjHCSOmEbuUGtmSNaR6P96V4nfmidVrmIOUJHUxwZM7V wFigRpv+gJQjxaNjk4teZ1szd/0oXxrkFomI78HVcIOCAVuO2FdJj3HoltKl1lQp+fO9 0otTn0rd0SiF3rEFsM2AqeEeLlem6Hx9qm/UIFrBKjldqqb/ozkSDko4s7O0xb1Zv8L0 G/HYPeXkW6blY8BtgI0ASudR9gSVU9KEsRb+jMLBtT9PXT5MiCuLWy5YY1ID80y+fR7V OAuw== X-Gm-Message-State: AHQUAuYV4/2J0YGGN7JJqlNBtaDCZSPcpECgtyIBt6hw1pCKkFiSrgF/ x+Byc2j8nvDy6tL7hUBTG5ABcC6pOtVAVg== X-Google-Smtp-Source: AHgI3IZWFw7B6KKWDz8L0sqGD8IN3jD6ZfF5Qkaue1PNcqRJhQuZ1ycTlllo8Hr0HPPt0zkeVKntmQ== X-Received: by 2002:adf:8b4d:: with SMTP id v13mr4298883wra.282.1549386316163; Tue, 05 Feb 2019 09:05:16 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 5 Feb 2019 17:04:50 +0000 Message-Id: <20190205170510.21984-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190205170510.21984-1-peter.maydell@linaro.org> References: <20190205170510.21984-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PULL 02/22] target/arm: Add PSTATE.BTYPE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Place this in its own field within ENV, as that will make it easier to reset from within TCG generated code. With the change to pstate_read/write, exception entry and return are automatically handled. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20190128223118.5255-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 8 ++++++-- target/arm/translate-a64.c | 3 +++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0c7ea39f1ae..58f99985c24 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -234,6 +234,7 @@ typedef struct CPUARMState { * semantics as for AArch32, as described in the comments on each f= ield) * nRW (also known as M[4]) is kept, inverted, in env->aarch64 * DAIF (exception masks) are kept in env->daif + * BTYPE is kept in env->btype * all other bits are stored in their correct places in env->pstate */ uint32_t pstate; @@ -263,6 +264,7 @@ typedef struct CPUARMState { uint32_t GE; /* cpsr[19:16] */ uint32_t thumb; /* cpsr[5]. 0 =3D arm mode, 1 =3D thumb mode. */ uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ + uint32_t btype; /* BTI branch type. spsr[11:10]. */ uint64_t daif; /* exception masks, in the bits they are in PSTATE */ =20 uint64_t elr_el[4]; /* AArch64 exception link regs */ @@ -1206,6 +1208,7 @@ void pmu_init(ARMCPU *cpu); #define PSTATE_I (1U << 7) #define PSTATE_A (1U << 8) #define PSTATE_D (1U << 9) +#define PSTATE_BTYPE (3U << 10) #define PSTATE_IL (1U << 20) #define PSTATE_SS (1U << 21) #define PSTATE_V (1U << 28) @@ -1214,7 +1217,7 @@ void pmu_init(ARMCPU *cpu); #define PSTATE_N (1U << 31) #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) -#define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF) +#define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) /* Mode values for AArch64 */ #define PSTATE_MODE_EL3h 13 #define PSTATE_MODE_EL3t 12 @@ -1246,7 +1249,7 @@ static inline uint32_t pstate_read(CPUARMState *env) ZF =3D (env->ZF =3D=3D 0); return (env->NF & 0x80000000) | (ZF << 30) | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) - | env->pstate | env->daif; + | env->pstate | env->daif | (env->btype << 10); } =20 static inline void pstate_write(CPUARMState *env, uint32_t val) @@ -1256,6 +1259,7 @@ static inline void pstate_write(CPUARMState *env, uin= t32_t val) env->CF =3D (val >> 29) & 1; env->VF =3D (val << 3) & 0x80000000; env->daif =3D val & PSTATE_DAIF; + env->btype =3D (val >> 10) & 3; env->pstate =3D val & ~CACHED_PSTATE_BITS; } =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a1997e3ae28..0b94d9455b7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -163,6 +163,9 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, el, psr & PSTATE_SP ? 'h' : 't'); =20 + if (cpu_isar_feature(aa64_bti, cpu)) { + cpu_fprintf(f, " BTYPE=3D%d", (psr & PSTATE_BTYPE) >> 10); + } if (!(flags & CPU_DUMP_FPU)) { cpu_fprintf(f, "\n"); return; --=20 2.20.1 From nobody Sun May 5 05:05:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549387870755141.09529978717876; Tue, 5 Feb 2019 09:31:10 -0800 (PST) Received: from localhost ([127.0.0.1]:35576 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4Yq-0005uE-Ip for importer@patchew.org; Tue, 05 Feb 2019 12:31:04 -0500 Received: from eggs.gnu.org ([209.51.188.92]:35827) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4AQ-0001ri-PQ for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gr4AJ-0000Us-Pz for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:46 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:37614) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gr4AC-0000Jf-Se for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:38 -0500 Received: by mail-wr1-x42c.google.com with SMTP id s12so4472323wrt.4 for ; Tue, 05 Feb 2019 09:05:18 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm5583164wmf.5.2019.02.05.09.05.16 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Feb 2019 09:05:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=FcfktwGIKzvljgXghV3TBAMt18UNQ69teiGvYk4ytAM=; b=VTcfM8tbUl69WcaHdXot6oTv9BXD6oSwFXL8NsOmyilpy6g0aVAAuonlh6EVhif/EK +QX6EUy9cjI6oYhaRb1R7LZDgXoB2Hm+rRiGXGb0ps7zq5HuqB0RRt5d+v2Q1YMbs/Pw qtnf8/sMLzkpMUPTXThwuGKaCJxdjj2Q4917vBbh/Bv1xunnNwpgQL7ppoQHeEpkY7sS qo1OYrRCvpvjS2pKoFAphixDCamCNoC0WCNmESi45QDlCcJLwmeUHP42gGGmN3SlKE5d Oa9Ir+gzu8QLSt8HXS56FEDnuzzi9lz2ZQq0UKaBgYRndGv2eUuHFqzLbMH+n5WmOPhL W5qQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FcfktwGIKzvljgXghV3TBAMt18UNQ69teiGvYk4ytAM=; b=JUpL34dGMsHwhpGhi5VyExoN7uGTQ+RTFtu9hJDDYzypD/6o4kHhSrHCrDYGyPtG/H ZthL4Dw9WtFokw/5wEcEpdS4bCsiSambEdrZ7lU9vWwwCu4IcuJ13auPdGBHX0mLNuzo UMsIl6bOViBcRoNb6pNjxnl/NPzQcP2qj2Dg7X5ncILX4rMU5V/BWEDQI6A6zWTMMh34 wyzP8vFvQ7cmQE3/ZOO1NBUgKfUuJIs2b77RqsLW/Ob+giUIj4+D+j2WF+zbJqmR9FkZ 3oS5PzOoxWM85l5fnPpwFZW8xibPJoLYnQQK1XgP6j2t/PXQCybvlFFDa9O14noo0A02 eUjg== X-Gm-Message-State: AHQUAuYJqqR7bkEji+SV4cRWxfKRy5aUJ1/qZ34+KLFMprfnPAiWXMTF plZu+p5yocP92dxTQVbCruscdT9X3rCUbQ== X-Google-Smtp-Source: AHgI3IZoXdsytCKhxKGzsATMz1ZL5+lUn4KLSx0iO+IyMX8y9Mw6AjzHQJAj8UOxSsME9y5HYjcn7Q== X-Received: by 2002:adf:e284:: with SMTP id v4mr4359380wri.26.1549386317431; Tue, 05 Feb 2019 09:05:17 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 5 Feb 2019 17:04:51 +0000 Message-Id: <20190205170510.21984-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190205170510.21984-1-peter.maydell@linaro.org> References: <20190205170510.21984-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42c Subject: [Qemu-devel] [PULL 03/22] target/arm: Add BT and BTYPE to tb->flags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20190128223118.5255-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 ++ target/arm/translate.h | 4 ++++ target/arm/helper.c | 22 +++++++++++++++------- target/arm/translate-a64.c | 2 ++ 4 files changed, 23 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 58f99985c24..1ff7197efd5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3052,6 +3052,8 @@ FIELD(TBFLAG_A64, TBII, 0, 2) FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) +FIELD(TBFLAG_A64, BT, 9, 1) +FIELD(TBFLAG_A64, BTYPE, 10, 2) =20 static inline bool bswap_code(bool sctlr_b) { diff --git a/target/arm/translate.h b/target/arm/translate.h index bb37d35741c..3d5e8bacacb 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -69,6 +69,10 @@ typedef struct DisasContext { bool ss_same_el; /* True if v8.3-PAuth is active. */ bool pauth_active; + /* True with v8.5-BTI and SCTLR_ELx.BT* set. */ + bool bt; + /* A copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. */ + uint8_t btype; /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ int c15_cpar; /* TCG op of the current insn_start. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index d070879894c..45ba678a7df 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13735,6 +13735,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, =20 if (is_a64(env)) { ARMCPU *cpu =3D arm_env_get_cpu(env); + uint64_t sctlr; =20 *pc =3D env->pc; flags =3D FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); @@ -13779,6 +13780,12 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target= _ulong *pc, flags =3D FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); } =20 + if (current_el =3D=3D 0) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + sctlr =3D env->cp15.sctlr_el[1]; + } else { + sctlr =3D env->cp15.sctlr_el[current_el]; + } if (cpu_isar_feature(aa64_pauth, cpu)) { /* * In order to save space in flags, we record only whether @@ -13786,17 +13793,18 @@ void cpu_get_tb_cpu_state(CPUARMState *env, targe= t_ulong *pc, * a nop, or "active" when some action must be performed. * The decision of which action to take is left to a helper. */ - uint64_t sctlr; - if (current_el =3D=3D 0) { - /* FIXME: ARMv8.1-VHE S2 translation regime. */ - sctlr =3D env->cp15.sctlr_el[1]; - } else { - sctlr =3D env->cp15.sctlr_el[current_el]; - } if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB= )) { flags =3D FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1); } } + + if (cpu_isar_feature(aa64_bti, cpu)) { + /* Note that SCTLR_EL[23].BT =3D=3D SCTLR_BT1. */ + if (sctlr & (current_el =3D=3D 0 ? SCTLR_BT0 : SCTLR_BT1)) { + flags =3D FIELD_DP32(flags, TBFLAG_A64, BT, 1); + } + flags =3D FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); + } } else { *pc =3D env->regs[15]; flags =3D FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 0b94d9455b7..a92fd433783 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -13840,6 +13840,8 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->sve_excp_el =3D FIELD_EX32(tb_flags, TBFLAG_A64, SVEEXC_EL); dc->sve_len =3D (FIELD_EX32(tb_flags, TBFLAG_A64, ZCR_LEN) + 1) * 16; dc->pauth_active =3D FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE); + dc->bt =3D FIELD_EX32(tb_flags, TBFLAG_A64, BT); + dc->btype =3D FIELD_EX32(tb_flags, TBFLAG_A64, BTYPE); dc->vec_len =3D 0; dc->vec_stride =3D 0; dc->cp_regs =3D arm_cpu->cp_regs; --=20 2.20.1 From nobody Sun May 5 05:05:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549388159662778.1827981950559; Tue, 5 Feb 2019 09:35:59 -0800 (PST) Received: from localhost ([127.0.0.1]:35650 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4dV-0001NT-J8 for importer@patchew.org; Tue, 05 Feb 2019 12:35:53 -0500 Received: from eggs.gnu.org ([209.51.188.92]:36146) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4AX-0001yK-UP for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:06:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gr4AT-0000dT-Jg for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:57 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:52438) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gr4AT-0000KF-7x for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:53 -0500 Received: by mail-wm1-x341.google.com with SMTP id m1so4459293wml.2 for ; Tue, 05 Feb 2019 09:05:20 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm5583164wmf.5.2019.02.05.09.05.17 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Feb 2019 09:05:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=bPSZOA3Qy8veYj4NGrUkj0OH/WOSyAGJ8VIKAw9ZTg4=; b=R3BvNi5yvD/SS9DM7ehrU/CwG/2JTBF0ipb1K7BSQ0CxYfXpeVDmYUwCfRXV69+REr YcKbyaxMMt53Xsszw1l0GuABHQWba6oKn9rvESnSgl62FVJYVo6ZfdC7I+fhCVbtU5eV QJ7QCSP6dX4gR7PnxpLy8OQbpqHVpvEyOQ8gJcFEh6pZOAaoqNEnuqcvRYtN9kwCepgu jRCpIgrSg6EeGz53Lljz7+XDFcmiFdyebsSJe1x+J13MxPlt4/xOtLWgsPSmp1Dveq3D SKi2eXzw6oiKP80CWZTGvTPtOQNl4CPuUYvSXQKuRlf7JOyYYrW2yYn4QNhZiXnogIPK sMLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bPSZOA3Qy8veYj4NGrUkj0OH/WOSyAGJ8VIKAw9ZTg4=; b=bhxTL/juzwNkRWrnYGiFUZSfq4JCOu+dNAEc3Sd6y1VZCOzwZlSe2bEZv9UsGROK/g c00pafm1RzKpV6PD/klU8NZfuEq7oE0dmqgtQz077sMQZaXnRupxgR3Kae/r4/oS6pEC b/vpTyFLnNFz4lfjFg5CoLa6WMjyqGTLY232a26kR/XeczMZvow8tUKTaXJyP8LGp1lG o1n4mBZz75QEv/2La/4p3JBhWsZZvNuFBozfeIAprkbYPvcncbqaheoPapMOMdoO9l4V QHFoxUw8ymPW0U8k5fiav4MIwTXKyBQkL2/HUI1G8W3lz+Fj4Y48jdx/QHdyZjrvb0Qk /vFA== X-Gm-Message-State: AHQUAuZdpV6J5jlaHwzrKrL3UA8j88r2AWS37DktQWCxET/6787QjAt7 zh1XEVsY8JRj+GyzxPeJiU2JHn87U0aOgQ== X-Google-Smtp-Source: AHgI3IaOi3abuZGmUThyEkTDHXtf/t2LNZZ7jf2iq3RCHz2fwOArOPvg1JQk0k95HL7YOnfV0J8y2Q== X-Received: by 2002:a1c:5984:: with SMTP id n126mr4369998wmb.62.1549386318950; Tue, 05 Feb 2019 09:05:18 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 5 Feb 2019 17:04:52 +0000 Message-Id: <20190205170510.21984-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190205170510.21984-1-peter.maydell@linaro.org> References: <20190205170510.21984-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PULL 04/22] exec: Add target-specific tlb bits to MemTxAttrs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Richard Henderson These bits can be used to cache target-specific data in cputlb read from the page tables. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20190128223118.5255-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- include/exec/memattrs.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index d4a16420984..d4a3477d71d 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -37,6 +37,16 @@ typedef struct MemTxAttrs { unsigned int user:1; /* Requester ID (for MSI for example) */ unsigned int requester_id:16; + /* + * The following are target-specific page-table bits. These are not + * related to actual memory transactions at all. However, this struct= ure + * is part of the tlb_fill interface, cached in the cputlb structure, + * and has unused bits. These fields will be read by target-specific + * helpers using env->iotlb[mmu_idx][tlb_index()].attrs.target_tlb_bit= N. + */ + unsigned int target_tlb_bit0 : 1; + unsigned int target_tlb_bit1 : 1; + unsigned int target_tlb_bit2 : 1; } MemTxAttrs; =20 /* Bus masters which don't specify any attributes will get this, --=20 2.20.1 From nobody Sun May 5 05:05:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549388448154664.6598089211157; Tue, 5 Feb 2019 09:40:48 -0800 (PST) Received: from localhost ([127.0.0.1]:35716 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4iA-0005KU-32 for importer@patchew.org; Tue, 05 Feb 2019 12:40:42 -0500 Received: from eggs.gnu.org ([209.51.188.92]:35987) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4AT-0001ua-TH for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:06:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gr4AR-0000Yp-Bd for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:53 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:46429) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gr4AR-0000KW-32 for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:51 -0500 Received: by mail-wr1-x441.google.com with SMTP id l9so4402816wrt.13 for ; Tue, 05 Feb 2019 09:05:21 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm5583164wmf.5.2019.02.05.09.05.19 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Feb 2019 09:05:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=H88QF3tD3acCANsnTz/zX9Jk/GgtG49XYl3KKrNDbuU=; b=WBHgh3t45YMGmdtvXmMH9THaQ3NKbSXSi9mnvGOJMR1I9Iqq9ROFJSuFfKylB+J04K 3Ou7jS1LPtR0/YXvSE62RWqtspUU9/xkzHt9bj/wBacHRjHu1JmLtZluIPgHbwXJ2ODg xErw3Yzm6N7eZAPuZE7SHgT7CrR3e1X/yUBHFDdlLsMUe7dEx9scy6G2+Vu8UOA9iMZP jVFYoy1cXsRfPN0EozqZdC1CEj+MqX7XedJEoxZXkzpRBcUMr4YbxLyZkBR3rYKqiI6g hmUqwvW1Jd56ypPOy9mz9Qn3dLCqwv+QlbDhXtFcX+pE14O1LduKVk1pv1i+2HupWyXj bevg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=H88QF3tD3acCANsnTz/zX9Jk/GgtG49XYl3KKrNDbuU=; b=GakDhKBHZ5r1ZP4MDM1aQYNWpnVPlM4uQXuwG15Cak1hHfKLxjM0EzeFapsVRCboZg Oxpfg6pAyW6IAO6+5yAAWDroKdvj/RR/uS5j1mCox5xk0fZFiAshs4WC8WuXSJdi8nBz QfUHkld4OHING4l21LHh6f4o25WL9rhMgzar1VHnERXwBTyAAbga0zZhtDWOEE6N0Hto dZYgwyowV5Z0zslFK2EOyfQyuqnQ726p3QYyPTW71dkV41Bv3kIZOb6PpSQzsNKsK3Tb p7ZZiuq8xDlcDPOrY1P4FJybuyAgez9RDdbp9fbhYhP5tfOevXswIuelI3ZCeEpZlwlM ZfDQ== X-Gm-Message-State: AHQUAuYDswJ8ccOGPhA/ya9F51PRRxmyBhl/uvpi8xYqi5tQs3vTgrca eVnrmzrIYP+M7mCsv/aJHUCdLuI7bwXlBw== X-Google-Smtp-Source: AHgI3IYhpyV8Vj6+JgyA2ms/Jh3UnMhVbKNC3OH1UH4U967Zt5GekZT7E3MesgFNMdzrX6xSdAP5ng== X-Received: by 2002:adf:f009:: with SMTP id j9mr4384605wro.170.1549386320198; Tue, 05 Feb 2019 09:05:20 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 5 Feb 2019 17:04:53 +0000 Message-Id: <20190205170510.21984-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190205170510.21984-1-peter.maydell@linaro.org> References: <20190205170510.21984-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PULL 05/22] target/arm: Cache the GP bit for a page in MemTxAttrs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Caching the bit means that we will not have to re-walk the page tables to look up the bit during translation. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20190128223118.5255-6-richard.henderson@linaro.org [PMM: no need to OR in guarded bit status] Signed-off-by: Peter Maydell --- target/arm/helper.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 45ba678a7df..be0ec7de2a4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10577,6 +10577,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, ta= rget_ulong address, bool ttbr1_valid; uint64_t descaddrmask; bool aarch64 =3D arm_el_is_aa64(env, el); + bool guarded =3D false; =20 /* TODO: * This code does not handle the different format TCR for VTCR_EL2. @@ -10756,6 +10757,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, ta= rget_ulong address, } /* Merge in attributes from table descriptors */ attrs |=3D nstable << 3; /* NS */ + guarded =3D extract64(descriptor, 50, 1); /* GP */ if (param.hpd) { /* HPD disables all the table attributes except NSTable. */ break; @@ -10801,6 +10803,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, t= arget_ulong address, */ txattrs->secure =3D false; } + /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB.= */ + if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) { + txattrs->target_tlb_bit0 =3D true; + } =20 if (cacheattrs !=3D NULL) { if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { --=20 2.20.1 From nobody Sun May 5 05:05:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549387952043239.94164553704059; Tue, 5 Feb 2019 09:32:32 -0800 (PST) Received: from localhost ([127.0.0.1]:35582 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4a9-0006tX-SH for importer@patchew.org; Tue, 05 Feb 2019 12:32:25 -0500 Received: from eggs.gnu.org ([209.51.188.92]:35925) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4AS-0001uW-Q9 for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gr4AQ-0000Y3-Qp for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:52 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:45382) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gr4AM-0000Kk-AR for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:48 -0500 Received: by mail-wr1-x443.google.com with SMTP id q15so4407403wro.12 for ; Tue, 05 Feb 2019 09:05:23 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm5583164wmf.5.2019.02.05.09.05.20 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Feb 2019 09:05:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=PVirn6BLcAXppSndYzC07n8dGqp6nt4fa98BODjPqNw=; b=zPpfI9ZfBjEXx6N/xscOmHCYgoM6dMFtslLWKQpcI45fWQY+ebVvsZgONZ1ndE3FTj /p4bLmavPFLCF+2Fafc43TOneYykuAHf3t4YjUIhjWmziYne4SMcmU9zr6MGnlOTxDiy 4RqRMZ08jvdzEGv1XDOhBsHgd1WTq9VtugcrAxC68M4AexRmo5Q6ihcKaaEWrg829Iww vkKsSPssCztNyBIVTgo6SG864YlM5JG9JkLpTocfVb37FPk6Cd9xObTaIZJXyCpAhoL9 L7O5TrJigW65LFjltbVExqUSDRCLAM+n14pXx9scx2Y/PINSTWP5iE9iFZwgPPOd8pI/ vtOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PVirn6BLcAXppSndYzC07n8dGqp6nt4fa98BODjPqNw=; b=BZruO219F/R9YDOmL6iOOjjcdl4n0S8xd2Lo1Q5bXm8AP+Mz1KN1B4+9vUQLjyiTyr BBRImmL0CKQpwZ5A1uQ/xz2OUIFv+IkSUi0/y6pn/Fl8a7Zz7LRa9CuhzNqFuN0kzfJx SLqKlQkc6X++7LXD9NC6hyC4ED6tpZ6bQTDnI9pL7XSKZ09ov/9PC+jqVVS30xxUcsX8 rYmcEZFO+5cOWW0zbNrru1DADDa7az0UBKi4G7DPl8uAtdfNdmpwYyNcLL/K4/SEg2eD xJSzbCuPHGT8xunaZBlhIaZ1EQapdqi6ur/kEs3lFBDB2KoFiHDthKVj8MS181UqsGfU s8HQ== X-Gm-Message-State: AHQUAuYtV1SPi9tjSOVQSebBK4PUW5rZyLUinj+ISkxAyumNk2whRltV Pmxrn/+hD+kKXOrEM2faDdjLT7go9MAsdA== X-Google-Smtp-Source: AHgI3IbyYYLp2IeRasZ68QUzDpIpYuXPdWR5J6tmYpIbMRihy1crGNdZIODlH37j7BZVAajkQY3zFQ== X-Received: by 2002:adf:ba94:: with SMTP id p20mr4462946wrg.62.1549386321596; Tue, 05 Feb 2019 09:05:21 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 5 Feb 2019 17:04:54 +0000 Message-Id: <20190205170510.21984-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190205170510.21984-1-peter.maydell@linaro.org> References: <20190205170510.21984-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PULL 06/22] target/arm: Default handling of BTYPE during translation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Richard Henderson The branch target exception for guarded pages has high priority, and only 8 instructions are valid for that case. Perform this check before doing any other decode. Clear BTYPE after all insns that neither set BTYPE nor exit via exception (DISAS_NORETURN). Not yet handled are insns that exit via DISAS_NORETURN for some other reason, like direct branches. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20190128223118.5255-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 6 ++ target/arm/translate.h | 9 ++- target/arm/translate-a64.c | 139 +++++++++++++++++++++++++++++++++++++ 3 files changed, 152 insertions(+), 2 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index a6fd4582b2b..d01a3f9f44b 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -268,6 +268,7 @@ enum arm_exception_class { EC_FPIDTRAP =3D 0x08, EC_PACTRAP =3D 0x09, EC_CP14RRTTRAP =3D 0x0c, + EC_BTITRAP =3D 0x0d, EC_ILLEGALSTATE =3D 0x0e, EC_AA32_SVC =3D 0x11, EC_AA32_HVC =3D 0x12, @@ -439,6 +440,11 @@ static inline uint32_t syn_pactrap(void) return EC_PACTRAP << ARM_EL_EC_SHIFT; } =20 +static inline uint32_t syn_btitrap(int btype) +{ + return (EC_BTITRAP << ARM_EL_EC_SHIFT) | btype; +} + static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int = fsc) { return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) diff --git a/target/arm/translate.h b/target/arm/translate.h index 3d5e8bacacb..f73939d7b4f 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -71,8 +71,13 @@ typedef struct DisasContext { bool pauth_active; /* True with v8.5-BTI and SCTLR_ELx.BT* set. */ bool bt; - /* A copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. */ - uint8_t btype; + /* + * >=3D 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. + * < 0, set by the current instruction. + */ + int8_t btype; + /* True if this page is guarded. */ + bool guarded_page; /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ int c15_cpar; /* TCG op of the current insn_start. */ diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a92fd433783..7034fb3d129 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -128,6 +128,16 @@ static inline int get_a64_user_mem_index(DisasContext = *s) return arm_to_core_mmu_idx(useridx); } =20 +static void reset_btype(DisasContext *s) +{ + if (s->btype !=3D 0) { + TCGv_i32 zero =3D tcg_const_i32(0); + tcg_gen_st_i32(zero, cpu_env, offsetof(CPUARMState, btype)); + tcg_temp_free_i32(zero); + s->btype =3D 0; + } +} + void aarch64_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags) { @@ -13756,6 +13766,90 @@ static void disas_data_proc_simd_fp(DisasContext *= s, uint32_t insn) } } =20 +/** + * is_guarded_page: + * @env: The cpu environment + * @s: The DisasContext + * + * Return true if the page is guarded. + */ +static bool is_guarded_page(CPUARMState *env, DisasContext *s) +{ +#ifdef CONFIG_USER_ONLY + return false; /* FIXME */ +#else + uint64_t addr =3D s->base.pc_first; + int mmu_idx =3D arm_to_core_mmu_idx(s->mmu_idx); + unsigned int index =3D tlb_index(env, mmu_idx, addr); + CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); + + /* + * We test this immediately after reading an insn, which means + * that any normal page must be in the TLB. The only exception + * would be for executing from flash or device memory, which + * does not retain the TLB entry. + * + * FIXME: Assume false for those, for now. We could use + * arm_cpu_get_phys_page_attrs_debug to re-read the page + * table entry even for that case. + */ + return (tlb_hit(entry->addr_code, addr) && + env->iotlb[mmu_idx][index].attrs.target_tlb_bit0); +#endif +} + +/** + * btype_destination_ok: + * @insn: The instruction at the branch destination + * @bt: SCTLR_ELx.BT + * @btype: PSTATE.BTYPE, and is non-zero + * + * On a guarded page, there are a limited number of insns + * that may be present at the branch target: + * - branch target identifiers, + * - paciasp, pacibsp, + * - BRK insn + * - HLT insn + * Anything else causes a Branch Target Exception. + * + * Return true if the branch is compatible, false to raise BTITRAP. + */ +static bool btype_destination_ok(uint32_t insn, bool bt, int btype) +{ + if ((insn & 0xfffff01fu) =3D=3D 0xd503201fu) { + /* HINT space */ + switch (extract32(insn, 5, 7)) { + case 0b011001: /* PACIASP */ + case 0b011011: /* PACIBSP */ + /* + * If SCTLR_ELx.BT, then PACI*SP are not compatible + * with btype =3D=3D 3. Otherwise all btype are ok. + */ + return !bt || btype !=3D 3; + case 0b100000: /* BTI */ + /* Not compatible with any btype. */ + return false; + case 0b100010: /* BTI c */ + /* Not compatible with btype =3D=3D 3 */ + return btype !=3D 3; + case 0b100100: /* BTI j */ + /* Not compatible with btype =3D=3D 2 */ + return btype !=3D 2; + case 0b100110: /* BTI jc */ + /* Compatible with any btype. */ + return true; + } + } else { + switch (insn & 0xffe0001fu) { + case 0xd4200000u: /* BRK */ + case 0xd4400000u: /* HLT */ + /* Give priority to the breakpoint exception. */ + return true; + } + } + return false; +} + /* C3.1 A64 instruction index by encoding */ static void disas_a64_insn(CPUARMState *env, DisasContext *s) { @@ -13767,6 +13861,43 @@ static void disas_a64_insn(CPUARMState *env, Disas= Context *s) =20 s->fp_access_checked =3D false; =20 + if (dc_isar_feature(aa64_bti, s)) { + if (s->base.num_insns =3D=3D 1) { + /* + * At the first insn of the TB, compute s->guarded_page. + * We delayed computing this until successfully reading + * the first insn of the TB, above. This (mostly) ensures + * that the softmmu tlb entry has been populated, and the + * page table GP bit is available. + * + * Note that we need to compute this even if btype =3D=3D 0, + * because this value is used for BR instructions later + * where ENV is not available. + */ + s->guarded_page =3D is_guarded_page(env, s); + + /* First insn can have btype set to non-zero. */ + tcg_debug_assert(s->btype >=3D 0); + + /* + * Note that the Branch Target Exception has fairly high + * priority -- below debugging exceptions but above most + * everything else. This allows us to handle this now + * instead of waiting until the insn is otherwise decoded. + */ + if (s->btype !=3D 0 + && s->guarded_page + && !btype_destination_ok(insn, s->bt, s->btype)) { + gen_exception_insn(s, 4, EXCP_UDEF, syn_btitrap(s->btype), + default_exception_el(s)); + return; + } + } else { + /* Not the first insn: btype must be 0. */ + tcg_debug_assert(s->btype =3D=3D 0); + } + } + switch (extract32(insn, 25, 4)) { case 0x0: case 0x1: case 0x3: /* UNALLOCATED */ unallocated_encoding(s); @@ -13803,6 +13934,14 @@ static void disas_a64_insn(CPUARMState *env, Disas= Context *s) =20 /* if we allocated any temporaries, free them here */ free_tmp_a64(s); + + /* + * After execution of most insns, btype is reset to 0. + * Note that we set btype =3D=3D -1 when the insn sets btype. + */ + if (s->btype > 0 && s->base.is_jmp !=3D DISAS_NORETURN) { + reset_btype(s); + } } =20 static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, --=20 2.20.1 From nobody Sun May 5 05:05:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549387546693867.2483862781934; Tue, 5 Feb 2019 09:25:46 -0800 (PST) Received: from localhost ([127.0.0.1]:35444 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4Tf-0001QI-Js for importer@patchew.org; Tue, 05 Feb 2019 12:25:43 -0500 Received: from eggs.gnu.org ([209.51.188.92]:36021) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4AU-0001uf-HE for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:06:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gr4AS-0000Zn-0H for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:54 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:51397) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gr4AR-0000Kr-Lr for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:51 -0500 Received: by mail-wm1-x32c.google.com with SMTP id b11so4469656wmj.1 for ; Tue, 05 Feb 2019 09:05:24 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm5583164wmf.5.2019.02.05.09.05.21 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Feb 2019 09:05:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=9X8i6rJyojdujGPcmE2h9DlEiaHjqsSnLuQBqIb/J/k=; b=hDCcyf/hVrHi+L/zP3JVis0fb6wbXugEezkYyGGqALuqBpoWSaXOlc6RcZBblywubg TP0ekgjl2Ba6Q3ovxgRkokf2SwqUIHwRkyE+YV3MR4stfMtvcWNA2DE4Io2cG2TjhYG0 a5SddyGkKpRtZMRrGa/qRmjEAImeDznyPGUc7LKX7RxjE0rfBiPztcXbzJL2rUVcAd3t Gg8QjgoBlLlopo2N8h31BkXHvat6SZa8T+crlfSsRQJzjgMvm9RHcrmHqnsK7MIblKlw 6XvvQSO49OuHd6PhDP0BNRCSP46wAWezjY1gZpj+JnOzP7Ip3feZnSl/3znalYy9y/ub lOPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9X8i6rJyojdujGPcmE2h9DlEiaHjqsSnLuQBqIb/J/k=; b=d1J+yDy+o83oMqdAxX1Np2XuivYgD7bJKbyo7NAcF0Vqgd/culAiUHe3Jimlhd9iPJ U4rcdmwDLITAjrOeu+YxDdPoGjFwwjY3vX1ttQx4wGbHi9pQ+Gi4iKTfyN0MqB8NrdbB atWTNR6Wo6yTp02UN2TFlusILk7/rkXsuE6znDncSvb+0omny0CZG2TD6Qzd/IGwnwEG RypIJvueIxMeGGZZMcsCO5fJSrfSqzc3PMlfyALvv7PmL1oeKUCpsEtWnalJbk+TElYD lw65xBOIEEpdaLntwbQ2HFe8G6AemFCJbLY/7F6padsH1La+T7dvecbv6cSqv6uMNkov yC8Q== X-Gm-Message-State: AHQUAuZoH2X8bYyw+4XH6FwlT/2wpUFJQGD2ofe41s9ZxYi/IrWqiXDo SkjVZPW7NCa0a/VcGvBfLfPiqJgGCo2AdA== X-Google-Smtp-Source: AHgI3Ia1jCT/S2E2pRw/t0IplaxrqOYRMSYPffMflSL/xnQf/IYSYfwUBoMC/EIaVGvXCW8Lt5B2Qg== X-Received: by 2002:a1c:c181:: with SMTP id r123mr4563571wmf.8.1549386322926; Tue, 05 Feb 2019 09:05:22 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 5 Feb 2019 17:04:55 +0000 Message-Id: <20190205170510.21984-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190205170510.21984-1-peter.maydell@linaro.org> References: <20190205170510.21984-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32c Subject: [Qemu-devel] [PULL 07/22] target/arm: Reset btype for direct branches X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Richard Henderson This is all of the non-exception cases of DISAS_NORETURN. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20190128223118.5255-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 7034fb3d129..5d0341a6953 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1362,6 +1362,7 @@ static void disas_uncond_b_imm(DisasContext *s, uint3= 2_t insn) } =20 /* B Branch / BL Branch with link */ + reset_btype(s); gen_goto_tb(s, 0, addr); } =20 @@ -1386,6 +1387,7 @@ static void disas_comp_b_imm(DisasContext *s, uint32_= t insn) tcg_cmp =3D read_cpu_reg(s, rt, sf); label_match =3D gen_new_label(); =20 + reset_btype(s); tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, tcg_cmp, 0, label_match); =20 @@ -1415,6 +1417,8 @@ static void disas_test_b_imm(DisasContext *s, uint32_= t insn) tcg_cmp =3D tcg_temp_new_i64(); tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, rt), (1ULL << bit_pos)); label_match =3D gen_new_label(); + + reset_btype(s); tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, tcg_cmp, 0, label_match); tcg_temp_free_i64(tcg_cmp); @@ -1441,6 +1445,7 @@ static void disas_cond_b_imm(DisasContext *s, uint32_= t insn) addr =3D s->pc + sextract32(insn, 5, 19) * 4 - 4; cond =3D extract32(insn, 0, 4); =20 + reset_btype(s); if (cond < 0x0e) { /* genuinely conditional branches */ TCGLabel *label_match =3D gen_new_label(); @@ -1605,6 +1610,7 @@ static void handle_sync(DisasContext *s, uint32_t ins= n, * a self-modified code correctly and also to take * any pending interrupts immediately. */ + reset_btype(s); gen_goto_tb(s, 0, s->pc); return; default: --=20 2.20.1 From nobody Sun May 5 05:05:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 154938879696070.22236579175069; Tue, 5 Feb 2019 09:46:36 -0800 (PST) Received: from localhost ([127.0.0.1]:35844 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4nn-00027U-0f for importer@patchew.org; Tue, 05 Feb 2019 12:46:31 -0500 Received: from eggs.gnu.org ([209.51.188.92]:36189) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4AZ-0001ze-Ee for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:06:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gr4AS-0000as-Im for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:59 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:43045) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gr4AS-0000L0-4u for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:52 -0500 Received: by mail-wr1-x434.google.com with SMTP id r2so4429756wrv.10 for ; Tue, 05 Feb 2019 09:05:25 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm5583164wmf.5.2019.02.05.09.05.22 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Feb 2019 09:05:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=zIvqPkcd1J27+rEslNQqRjGnmbyQZngk0nHBZjbztXI=; b=B+awP9dJUD0SoLFP0mK/rOdDimQNGYd9OtK7AAsN1OZiHVgLBayysldf62dHnMEy4L 8SGhKoGtsn2J0s2fhfXsFpErKeXy8Jz4jOhHKicXo65dIdErPA81e8dx5F/PAphFShv4 jJj4jJ8DT1Wt4+1IoePrVRPBmWIs1ksoTwsjTq1mLr+R0D3eT4tF9aAc2+HRhWfu+eBp 7uJKK4QphP8/b2ahb7hVgsiBXsMJPasxVWJW0pY1Vu8DX1Vhmlnk+DJrIMmEk6tRT1cu wqEVV5B1UmBTpBEYBovTplhwMtQyujgt3gIWPc2QKR7C0xon0xL+qV4+iT9hEJTY8xDF Tg4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zIvqPkcd1J27+rEslNQqRjGnmbyQZngk0nHBZjbztXI=; b=SHBmlya7jeyI5zQhsD9SPnb/aVi9E2fE0jDh2nEq6IfrlTkUX828nk2s6/21MQIiwr 0JpMIrf1GdH9Mh1uHxr1U6MsKsr/OT1OevuzQco+Maw6+qeEX1x/lrfy8Vz0GxW8vvgl 2Jw7RSEs89BZlJ6x/rnkWdqdCgK5zKO1AbRh02jeGFnstuSyLmzFo2hRqd22BVp5bp4J Krvki8CnW9hwGlQ5j2QHNW9HfR8BlkmVCsG1tRQyjtXBVHaf4p10zv3BHFlhFFeOy0bG 6a6lkKlePCeOSq5JB6ah1AKwxUTGA9qfkX66ttFt6qTJnQ9NWNKf+2X5ES8l5rU6JWuf ecXA== X-Gm-Message-State: AHQUAuZd0TAnIYPkcKqFTDOHnfkz4DB+I9bijsTzR5XWUsrcRVOoYSUL kyzXYBGqg1BNyIOk134FtuhJIRcB8PuoEw== X-Google-Smtp-Source: AHgI3IZpjIfErJkDqnPfgb5URALVjxHd0/5AHUHDOAJ+U1BN1f1eiCSIIDW+CA/mD71icsSdqPqQJg== X-Received: by 2002:adf:f9ca:: with SMTP id w10mr4442242wrr.189.1549386324320; Tue, 05 Feb 2019 09:05:24 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 5 Feb 2019 17:04:56 +0000 Message-Id: <20190205170510.21984-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190205170510.21984-1-peter.maydell@linaro.org> References: <20190205170510.21984-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::434 Subject: [Qemu-devel] [PULL 08/22] target/arm: Set btype for indirect branches X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20190128223118.5255-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 37 ++++++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 5d0341a6953..7375ebf7a9e 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -138,6 +138,19 @@ static void reset_btype(DisasContext *s) } } =20 +static void set_btype(DisasContext *s, int val) +{ + TCGv_i32 tcg_val; + + /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */ + tcg_debug_assert(val >=3D 1 && val <=3D 3); + + tcg_val =3D tcg_const_i32(val); + tcg_gen_st_i32(tcg_val, cpu_env, offsetof(CPUARMState, btype)); + tcg_temp_free_i32(tcg_val); + s->btype =3D -1; +} + void aarch64_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags) { @@ -1982,6 +1995,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) { unsigned int opc, op2, op3, rn, op4; + unsigned btype_mod =3D 2; /* 0: BR, 1: BLR, 2: other */ TCGv_i64 dst; TCGv_i64 modifier; =20 @@ -1999,6 +2013,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint3= 2_t insn) case 0: /* BR */ case 1: /* BLR */ case 2: /* RET */ + btype_mod =3D opc; switch (op3) { case 0: /* BR, BLR, RET */ @@ -2042,7 +2057,6 @@ static void disas_uncond_b_reg(DisasContext *s, uint3= 2_t insn) default: goto do_unallocated; } - gen_a64_set_pc(s, dst); /* BLR also needs to load return address */ if (opc =3D=3D 1) { @@ -2058,6 +2072,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint3= 2_t insn) if ((op3 & ~1) !=3D 2) { goto do_unallocated; } + btype_mod =3D opc & 1; if (s->pauth_active) { dst =3D new_tmp_a64(s); modifier =3D cpu_reg_sp(s, op4); @@ -2141,6 +2156,26 @@ static void disas_uncond_b_reg(DisasContext *s, uint= 32_t insn) return; } =20 + switch (btype_mod) { + case 0: /* BR */ + if (dc_isar_feature(aa64_bti, s)) { + /* BR to {x16,x17} or !guard -> 1, else 3. */ + set_btype(s, rn =3D=3D 16 || rn =3D=3D 17 || !s->guarded_page = ? 1 : 3); + } + break; + + case 1: /* BLR */ + if (dc_isar_feature(aa64_bti, s)) { + /* BLR sets BTYPE to 2, regardless of source guarded page. */ + set_btype(s, 2); + } + break; + + default: /* RET or none of the above. */ + /* BTYPE will be set to 0 by normal end-of-insn processing. */ + break; + } + s->base.is_jmp =3D DISAS_JUMP; } =20 --=20 2.20.1 From nobody Sun May 5 05:05:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549389496892317.5006152177343; Tue, 5 Feb 2019 09:58:16 -0800 (PST) Received: from localhost ([127.0.0.1]:36054 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4z4-0002zP-Qv for importer@patchew.org; Tue, 05 Feb 2019 12:58:10 -0500 Received: from eggs.gnu.org ([209.51.188.92]:36009) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4AU-0001ud-Ca for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:06:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gr4AS-0000Zy-1b for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:54 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:33617) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gr4AR-0000L4-PB for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:51 -0500 Received: by mail-wm1-x32f.google.com with SMTP id r24so20610wmh.0 for ; Tue, 05 Feb 2019 09:05:27 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm5583164wmf.5.2019.02.05.09.05.24 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Feb 2019 09:05:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=4wOyxC8OKE4W2Hr9efqaNWagq9154K/8NbobdfIhYAs=; b=WuqhVMjgPLQRg5rQVYicuWbz0UwhqFVtycHmiVL+TXki3mMMSFO+ypfwXoC/P2/QtF KdwW5+SROmOS5lKB1Q3JBmCawuCo2ZXzjhtyzzf1E5jHBxOeyrEj4wTQumKSWU81Xd8Q wRqsu9fPx2Yir+ljLuaBH6219+AMzu2V9PwAkaKvBu1U8u4Ln/yrhCBr4ssUfZcb3v7f hZhV2nVxYslwz9rpVSg3IwP4gBjQyLnGIW/EmI4tNuXtKKhyGWkRx+JHlZH+cG51+E0W FmSZ44Bf1STxdp0PfN3nXFihoWeIqvSex37B84zdeU/JErQLlqPzcgumhiJ8xOh6rBtq KWLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4wOyxC8OKE4W2Hr9efqaNWagq9154K/8NbobdfIhYAs=; b=EYIB//197yLfnyrG//G7hpyBD9stVjLzY0H1qn8Lxlal7kEL1dGFP80TS63YLwkPEd ROOXQ3lymtSVz6vW2t4/vsVYNCYoyDdwqFPCLzwg8Gpw5P6bue2mnzpXktSQofyrOD+n gTUyDeEGArTDeQPhfHf9KwBFKRKxSdhgQwkKrdRZRXUCCHcaB6ct+jFobhsp0Xug8DkZ F73QbB/0D5Hneub6kdUGpcGD/rLi4ja9lrUQw7n5iVO8yWQRcSGbycctHE/K9Zw7frw+ sjHA6RKckcNSnPV2ox2Kh8i7Hb4fkIGwRaxV+idCUupzjn8LKOOVAyh0ZWHyPDGte2wO XGcA== X-Gm-Message-State: AHQUAuaAHU4j2dAGnyXp3N6jYG/3pi0U33D4hDXo9dRY0MBNk7U2C8Kb AdKbDXPxUQ2Nf7XvL5ASj4iBZ8RsSjfSEw== X-Google-Smtp-Source: AHgI3Ib3bPF4xG2fiDeLbEB1PZRbNPPnSYcvTRPQL3h8D8dVZH4ffPKwl+EBxi6g51159HiNDnhyeg== X-Received: by 2002:a1c:c1c9:: with SMTP id r192mr4439157wmf.146.1549386325833; Tue, 05 Feb 2019 09:05:25 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 5 Feb 2019 17:04:57 +0000 Message-Id: <20190205170510.21984-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190205170510.21984-1-peter.maydell@linaro.org> References: <20190205170510.21984-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32f Subject: [Qemu-devel] [PULL 09/22] target/arm: Enable BTI for -cpu max X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20190128223118.5255-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu64.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 7107ec8d7eb..eff0f164dd0 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -324,6 +324,10 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); cpu->isar.id_aa64pfr0 =3D t; =20 + t =3D cpu->isar.id_aa64pfr1; + t =3D FIELD_DP64(t, ID_AA64PFR1, BT, 1); + cpu->isar.id_aa64pfr1 =3D t; + t =3D cpu->isar.id_aa64mmfr1; t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); --=20 2.20.1 From nobody Sun May 5 05:05:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549387592753993.834007360053; Tue, 5 Feb 2019 09:26:32 -0800 (PST) Received: from localhost ([127.0.0.1]:35483 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4UM-00024M-M6 for importer@patchew.org; Tue, 05 Feb 2019 12:26:26 -0500 Received: from eggs.gnu.org ([209.51.188.92]:35829) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4AQ-0001rl-QI for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gr4AK-0000VF-J7 for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:48 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:36749) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gr4AC-0000Nv-Sv for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:40 -0500 Received: by mail-wr1-x42b.google.com with SMTP id z3so4483221wrv.3 for ; Tue, 05 Feb 2019 09:05:29 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm5583164wmf.5.2019.02.05.09.05.25 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Feb 2019 09:05:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=oqimmOxhlnAPzvnVXysC1gLndndgMG4dqjEyqUjEd04=; b=UBHNBEmMuKosrrDJnqktaKKjvMH5ZX79+6tL25oI7/J+Qa70mH1fRhCpPrvfyYILg0 rS5t/wImAIlUQy7bTvJsIQ7QSPy/GH/8LxAio3/wAUnlq6QpV/JpLLxqeOPfO632K/n3 UzD9ZbSIXXzkqoAVttK9sLLWXpOqDr5bbH7vRJ7kFNnrM2upKTWgrK3ziZT4TBOOOMgW f4tS/1N3j3XzBWjVKY05J0qKDrQTwVUa0ak03ElLND6WQ5DOpBa1NNSpXZepaEWp83yw ve6Ip3NSTE/F96T8iNHSYz7g4zhx/feZLKKcsN+n+B2FAvit9AHBXjBlPKVV7OEs1Y0T w5Og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oqimmOxhlnAPzvnVXysC1gLndndgMG4dqjEyqUjEd04=; b=iJsrsVqTN0ON24EqZzTG7gVJzlN9rKfs3VU3LBS2OQ47v+ZUKC2m/r/lIyoDfnZ2O+ 5KIpLQf8Xi3eu522vuwyzHd5kE8y5c2CT2XLiqAsfOoIo4Kwbc6SUDgNEBW4Prd6PT+i NEF80LcseUtWl6Oj0labJvbf29MrkWuDfLLrhBcTdM4QVwBfTzdZGyZ+fTR7m43SFfus pG+RSPG7k1AkRa/25gxu/VQjR4Vg1hIbxtlu7d0iXFBZMnKnjHVZMzocWeCec7PwX1fV ZThrGMCjeBqMuDb8sasPgFg5+wT+VEoNqiHmrmxjmsGsHkzWTAYoxbSBNt6TRoqVEQcP 89BA== X-Gm-Message-State: AHQUAuat4SdmOOsa+EBDjb/UiWK8IKidFlzvgLhYgdEKxFhn3UIwRI0p D8FfdIwbsPNSUCoxmGV4UgDupBzEk7lJhQ== X-Google-Smtp-Source: AHgI3IaFrBlEzfuxIN5mh9FxoSiKuG9chwTVTVu7+ZQpPxO8OiGHF8uxQMIlCp5ZQy/2kvbeSzFaIQ== X-Received: by 2002:a5d:43cd:: with SMTP id v13mr4586815wrr.194.1549386327796; Tue, 05 Feb 2019 09:05:27 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 5 Feb 2019 17:04:58 +0000 Message-Id: <20190205170510.21984-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190205170510.21984-1-peter.maydell@linaro.org> References: <20190205170510.21984-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42b Subject: [Qemu-devel] [PULL 10/22] linux-user: Implement PR_PAC_RESET_KEYS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20190201195404.30486-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- linux-user/aarch64/target_syscall.h | 7 ++++++ linux-user/syscall.c | 36 +++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/linux-user/aarch64/target_syscall.h b/linux-user/aarch64/targe= t_syscall.h index 937fd7989e7..b595e5da820 100644 --- a/linux-user/aarch64/target_syscall.h +++ b/linux-user/aarch64/target_syscall.h @@ -22,6 +22,13 @@ struct target_pt_regs { #define TARGET_PR_SVE_SET_VL 50 #define TARGET_PR_SVE_GET_VL 51 =20 +#define TARGET_PR_PAC_RESET_KEYS 54 +# define TARGET_PR_PAC_APIAKEY (1 << 0) +# define TARGET_PR_PAC_APIBKEY (1 << 1) +# define TARGET_PR_PAC_APDAKEY (1 << 2) +# define TARGET_PR_PAC_APDBKEY (1 << 3) +# define TARGET_PR_PAC_APGAKEY (1 << 4) + void arm_init_pauth_key(ARMPACKey *key); =20 #endif /* AARCH64_TARGET_SYSCALL_H */ diff --git a/linux-user/syscall.c b/linux-user/syscall.c index b5786d4fc1f..bf076cbf8c4 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -9691,6 +9691,42 @@ static abi_long do_syscall1(void *cpu_env, int num, = abi_long arg1, } } return ret; + case TARGET_PR_PAC_RESET_KEYS: + { + CPUARMState *env =3D cpu_env; + ARMCPU *cpu =3D arm_env_get_cpu(env); + + if (arg3 || arg4 || arg5) { + return -TARGET_EINVAL; + } + if (cpu_isar_feature(aa64_pauth, cpu)) { + int all =3D (TARGET_PR_PAC_APIAKEY | TARGET_PR_PAC_API= BKEY | + TARGET_PR_PAC_APDAKEY | TARGET_PR_PAC_APDBK= EY | + TARGET_PR_PAC_APGAKEY); + if (arg2 =3D=3D 0) { + arg2 =3D all; + } else if (arg2 & ~all) { + return -TARGET_EINVAL; + } + if (arg2 & TARGET_PR_PAC_APIAKEY) { + arm_init_pauth_key(&env->apia_key); + } + if (arg2 & TARGET_PR_PAC_APIBKEY) { + arm_init_pauth_key(&env->apib_key); + } + if (arg2 & TARGET_PR_PAC_APDAKEY) { + arm_init_pauth_key(&env->apda_key); + } + if (arg2 & TARGET_PR_PAC_APDBKEY) { + arm_init_pauth_key(&env->apdb_key); + } + if (arg2 & TARGET_PR_PAC_APGAKEY) { + arm_init_pauth_key(&env->apga_key); + } + return 0; + } + } + return -TARGET_EINVAL; #endif /* AARCH64 */ case PR_GET_SECCOMP: case PR_SET_SECCOMP: --=20 2.20.1 From nobody Sun May 5 05:05:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549387719214608.2683688754709; Tue, 5 Feb 2019 09:28:39 -0800 (PST) Received: from localhost ([127.0.0.1]:35509 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4WP-0003qP-5j for importer@patchew.org; Tue, 05 Feb 2019 12:28:33 -0500 Received: from eggs.gnu.org ([209.51.188.92]:36005) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4AU-0001uc-Bv for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:06:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gr4AS-0000bH-MT for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:54 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:51133) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gr4AS-0000P1-CO for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:52 -0500 Received: by mail-wm1-x329.google.com with SMTP id z5so4445339wmf.0 for ; Tue, 05 Feb 2019 09:05:30 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm5583164wmf.5.2019.02.05.09.05.27 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Feb 2019 09:05:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=sYpzqW64aXSNRJq6u4FiSJm1FMuZGApzbaGf9IfHhTE=; b=KS3eHxHX8wpVAGSEiNel6ZhbuGmNbbS/lxNgJ43xaAaRRTX+CqCCeTtlyfDfg26EmE 8TgBB/4ekX9hL7Tg1QlH4rHVOPozkCjqKXLQeH7mmtBfvxqBIuWnM8gyovCzI4/l1opY 6+yJWiTQqhcpYczpXSZCqww+Mbw6KmBxz2pgx/k4EyErvfgdet1Zlo4rCXdACF8FWqUX uzYai115JUOlwN2yQ8nJs2Z4GiFfPioSSC2QOuZVR+Hr2SrIDBeI6pYtSAjmLihMC6IJ pND7fSdqL6YYXatyAMVJERvzwqR16jYV/r9y1+RqQAyFt+YpUcm0bLAg7vDNYRbHUXru UY7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sYpzqW64aXSNRJq6u4FiSJm1FMuZGApzbaGf9IfHhTE=; b=oJ7gHmJOdl5uZDsbrZ4NK58MIg+5maiDjzptv+zYdTTLz660cOUnM9YTZ5/euBtRMr xrXdQExHArl8WiiP5Ow0svUQzrLasZ7yIZ7O2vmiZFR6EJSq6qJKIR2C9m8iJpaQOSr4 Oao6vamTy/P5W5u1vgBYGxpw0zL5XXxDpjWRFLdAGa22emsmyksmVu5D9LUl+mf9VB2q R+mcLY+CR3NRPk+n8qhtDYdFxgUC9t5GmCgWF2mhxXDCOuCiS+DhXpAGXqa3yarh96Uo UCoqIzxzqlaBtsseOBetblZ8+b4+R0I/DfSHQpWW9Cb0x3/Qz3K5W3HWYKb+Wnt6bZYz 89vw== X-Gm-Message-State: AHQUAuZZOjRktZfETD3KzRw7GXFrugHrarIXBb2YJaGEmouU6ZirVlPv 6reh1OADVhCLkasgvNZLPBG+07UkNQXwgw== X-Google-Smtp-Source: AHgI3IbmDSTn+5hd6RkYQUX+R+NTdiBPWY82d80CULm0CO8UZMOOF0pS66OuHF9IEkZKcvhzJb7QyA== X-Received: by 2002:a1c:23cc:: with SMTP id j195mr4392256wmj.124.1549386329147; Tue, 05 Feb 2019 09:05:29 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 5 Feb 2019 17:04:59 +0000 Message-Id: <20190205170510.21984-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190205170510.21984-1-peter.maydell@linaro.org> References: <20190205170510.21984-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::329 Subject: [Qemu-devel] [PULL 11/22] tests/tcg/aarch64: Add pauth smoke test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Message-id: 20190201195404.30486-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- tests/tcg/aarch64/Makefile.target | 6 +++++- tests/tcg/aarch64/pauth-1.c | 23 +++++++++++++++++++++++ 2 files changed, 28 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/aarch64/pauth-1.c diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile= .target index 08c45b8470c..2bb914975be 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -8,10 +8,14 @@ VPATH +=3D $(AARCH64_SRC) # we don't build any of the ARM tests AARCH64_TESTS=3D$(filter-out $(ARM_TESTS), $(TESTS)) AARCH64_TESTS+=3Dfcvt -TESTS:=3D$(AARCH64_TESTS) =20 fcvt: LDFLAGS+=3D-lm =20 run-fcvt: fcvt $(call run-test,$<,$(QEMU) $<, "$< on $(TARGET_NAME)") $(call diff-out,$<,$(AARCH64_SRC)/fcvt.ref) + +AARCH64_TESTS +=3D pauth-1 +run-pauth-%: QEMU +=3D -cpu max + +TESTS:=3D$(AARCH64_TESTS) diff --git a/tests/tcg/aarch64/pauth-1.c b/tests/tcg/aarch64/pauth-1.c new file mode 100644 index 00000000000..ae6dc05c2b1 --- /dev/null +++ b/tests/tcg/aarch64/pauth-1.c @@ -0,0 +1,23 @@ +#include +#include + +asm(".arch armv8.4-a"); + +#ifndef PR_PAC_RESET_KEYS +#define PR_PAC_RESET_KEYS 54 +#define PR_PAC_APDAKEY (1 << 2) +#endif + +int main() +{ + int x; + void *p0 =3D &x, *p1, *p2; + + asm volatile("pacdza %0" : "=3Dr"(p1) : "0"(p0)); + prctl(PR_PAC_RESET_KEYS, PR_PAC_APDAKEY, 0, 0, 0); + asm volatile("pacdza %0" : "=3Dr"(p2) : "0"(p0)); + + assert(p1 !=3D p0); + assert(p1 !=3D p2); + return 0; +} --=20 2.20.1 From nobody Sun May 5 05:05:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549389142995244.53799014987055; Tue, 5 Feb 2019 09:52:22 -0800 (PST) Received: from localhost ([127.0.0.1]:35963 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4tM-0006Oy-Mt for importer@patchew.org; Tue, 05 Feb 2019 12:52:16 -0500 Received: from eggs.gnu.org ([209.51.188.92]:35831) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4AQ-0001rm-QT for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gr4AK-0000VC-J7 for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:48 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:34527) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gr4AC-0000Ps-TF for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:40 -0500 Received: by mail-wr1-x42a.google.com with SMTP id z15so2418576wrn.1 for ; Tue, 05 Feb 2019 09:05:31 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm5583164wmf.5.2019.02.05.09.05.29 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Feb 2019 09:05:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=iPLxEGipxJ4KR564OMDlLTK24VXJ0dyuC+paz7/Krc4=; b=kNQepgz+x4/tLOHogCnORXlB3rLSL4IBUC4jc+t4Im+CDbvVOypihVdbX5FtUpB3Zi Qi4rUU8vBwh5Bk2Xv7riC8+vdvyLRJjoPzNu6vQjxKPFXxr/lu2J74RdIgrRRn2C4lzR ULfqd+/JK4l5F00Pk6vCkVrYeNktRu9HsG0R12cMD616sVK5O5BgS2MpODD5WZIhql4j Vj+pRZS0Ni5RI/ea+qfVDlhhLswDfBXGd3xaHvGgJVfz+oBhvANCRxpwebmDmnZ6V6Rt 6zbjbxIsCSmmXqHTRsvOrUt+6PyInMPVD58I4VR9ARB7fY21JwLvd22BOrP19qSPomlO /DBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iPLxEGipxJ4KR564OMDlLTK24VXJ0dyuC+paz7/Krc4=; b=EjiHSND6dK6i74RqqyQgB848cjkMYH4Bj/6HP8jdShAvyfaiaOPPmE4D2K45/qtrqo XrG7We1rpY0duAYK2tQUs1qCefr8pqrYUHjkckIezZTvh6u7bHqYpCbUydvyfIm1vNGh PpWoE/+g03f7Px8T6zjyLwxhHHujsQJaSgkeZMDnbYWriST30MpcpKQBclCIO1cmK9b5 G9y26NRVD61DJVU5jh7XcrLdwJQwE3Tnl8LLaCZ4FlxWI1TWRXXU4QI+k/1HiX/UlzZ0 zmWdEY9ocagitzrtKUIlwiKJEv2yTGjea/DwCswvCqMB62ljFh5ZStVPLubGqiRPrid5 IPSQ== X-Gm-Message-State: AHQUAuaBJe+W/aBuRPZ14dz4h9tTBZnSki+8pD0jCHQKRwdYiq8ocswq 1mY2t1KdU8jBfOAyUJWYomXOpAf7t5fqQg== X-Google-Smtp-Source: AHgI3Ib/GtMgXN4G9cptzhgRtnahV0+AlrB7HJitDE+D16g/NZ11ScsH3O6hHQf3opk5rFVnua4+Og== X-Received: by 2002:adf:8b4d:: with SMTP id v13mr4299766wra.282.1549386330377; Tue, 05 Feb 2019 09:05:30 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 5 Feb 2019 17:05:00 +0000 Message-Id: <20190205170510.21984-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190205170510.21984-1-peter.maydell@linaro.org> References: <20190205170510.21984-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42a Subject: [Qemu-devel] [PULL 12/22] target/arm: Add TBFLAG_A64_TBID, split out gen_top_byte_ignore X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Split out gen_top_byte_ignore in preparation of handling these data accesses; the new tbflags field is not yet honored. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20190204132126.3255-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 1 + target/arm/translate.h | 3 +- target/arm/helper.c | 1 + target/arm/translate-a64.c | 72 +++++++++++++++++++------------------- 4 files changed, 40 insertions(+), 37 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1ff7197efd5..ec14d3e228d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3054,6 +3054,7 @@ FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) FIELD(TBFLAG_A64, BT, 9, 1) FIELD(TBFLAG_A64, BTYPE, 10, 2) +FIELD(TBFLAG_A64, TBID, 12, 2) =20 static inline bool bswap_code(bool sctlr_b) { diff --git a/target/arm/translate.h b/target/arm/translate.h index f73939d7b4f..17748ddfb9d 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -26,7 +26,8 @@ typedef struct DisasContext { int user; #endif ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */ - uint8_t tbii; /* TBI1|TBI0 for EL0/1 or TBI for EL2/3 */ + uint8_t tbii; /* TBI1|TBI0 for insns */ + uint8_t tbid; /* TBI1|TBI0 for data */ bool ns; /* Use non-secure CPREG bank on access */ int fp_excp_el; /* FP exception EL or 0 if enabled */ int sve_excp_el; /* SVE exception EL or 0 if enabled */ diff --git a/target/arm/helper.c b/target/arm/helper.c index be0ec7de2a4..25d8ec38f8e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13767,6 +13767,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, } =20 flags =3D FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); + flags =3D FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); } #endif =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 7375ebf7a9e..d24a083a194 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -284,10 +284,10 @@ void gen_a64_set_pc_im(uint64_t val) tcg_gen_movi_i64(cpu_pc, val); } =20 -/* Load the PC from a generic TCG variable. +/* + * Handle Top Byte Ignore (TBI) bits. * - * If address tagging is enabled via the TCR TBI bits, then loading - * an address into the PC will clear out any tag in it: + * If address tagging is enabled via the TCR TBI bits: * + for EL2 and EL3 there is only one TBI bit, and if it is set * then the address is zero-extended, clearing bits [63:56] * + for EL0 and EL1, TBI0 controls addresses with bit 55 =3D=3D 0 @@ -295,45 +295,44 @@ void gen_a64_set_pc_im(uint64_t val) * If the appropriate TBI bit is set for the address then * the address is sign-extended from bit 55 into bits [63:56] * - * We can avoid doing this for relative-branches, because the - * PC + offset can never overflow into the tag bits (assuming - * that virtual addresses are less than 56 bits wide, as they - * are currently), but we must handle it for branch-to-register. + * Here We have concatenated TBI{1,0} into tbi. */ -static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) +static void gen_top_byte_ignore(DisasContext *s, TCGv_i64 dst, + TCGv_i64 src, int tbi) { - /* Note that TBII is TBI1:TBI0. */ - int tbi =3D s->tbii; - - if (s->current_el <=3D 1) { - if (tbi !=3D 0) { - /* Sign-extend from bit 55. */ - tcg_gen_sextract_i64(cpu_pc, src, 0, 56); - - if (tbi !=3D 3) { - TCGv_i64 tcg_zero =3D tcg_const_i64(0); - - /* - * The two TBI bits differ. - * If tbi0, then !tbi1: only use the extension if positive. - * if !tbi0, then tbi1: only use the extension if negative. - */ - tcg_gen_movcond_i64(tbi =3D=3D 1 ? TCG_COND_GE : TCG_COND_= LT, - cpu_pc, cpu_pc, tcg_zero, cpu_pc, src); - tcg_temp_free_i64(tcg_zero); - } - return; - } + if (tbi =3D=3D 0) { + /* Load unmodified address */ + tcg_gen_mov_i64(dst, src); + } else if (s->current_el >=3D 2) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + /* Force tag byte to all zero */ + tcg_gen_extract_i64(dst, src, 0, 56); } else { - if (tbi !=3D 0) { - /* Force tag byte to all zero */ - tcg_gen_extract_i64(cpu_pc, src, 0, 56); - return; + /* Sign-extend from bit 55. */ + tcg_gen_sextract_i64(dst, src, 0, 56); + + if (tbi !=3D 3) { + TCGv_i64 tcg_zero =3D tcg_const_i64(0); + + /* + * The two TBI bits differ. + * If tbi0, then !tbi1: only use the extension if positive. + * if !tbi0, then tbi1: only use the extension if negative. + */ + tcg_gen_movcond_i64(tbi =3D=3D 1 ? TCG_COND_GE : TCG_COND_LT, + dst, dst, tcg_zero, dst, src); + tcg_temp_free_i64(tcg_zero); } } +} =20 - /* Load unmodified address */ - tcg_gen_mov_i64(cpu_pc, src); +static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) +{ + /* + * If address tagging is enabled for instructions via the TCR TBI bits, + * then loading an address into the PC will clear out any tag. + */ + gen_top_byte_ignore(s, cpu_pc, src, s->tbii); } =20 typedef struct DisasCompare64 { @@ -14012,6 +14011,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, core_mmu_idx =3D FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX); dc->mmu_idx =3D core_to_arm_mmu_idx(env, core_mmu_idx); dc->tbii =3D FIELD_EX32(tb_flags, TBFLAG_A64, TBII); + dc->tbid =3D FIELD_EX32(tb_flags, TBFLAG_A64, TBID); dc->current_el =3D arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user =3D (dc->current_el =3D=3D 0); --=20 2.20.1 From nobody Sun May 5 05:05:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549388472421178.3789851094242; Tue, 5 Feb 2019 09:41:12 -0800 (PST) Received: from localhost ([127.0.0.1]:35760 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4iY-0005mq-5b for importer@patchew.org; Tue, 05 Feb 2019 12:41:06 -0500 Received: from eggs.gnu.org ([209.51.188.92]:36363) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4Ah-000255-EJ for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:06:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gr4AT-0000d0-Dv for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:06:07 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:37622) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gr4AS-0000QI-Td for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:53 -0500 Received: by mail-wr1-x433.google.com with SMTP id s12so4473283wrt.4 for ; Tue, 05 Feb 2019 09:05:33 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm5583164wmf.5.2019.02.05.09.05.30 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Feb 2019 09:05:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=LCfLonOE7KgFGWHQRBF606Bz7FW9Av6jw+jMlTKdglU=; b=wFzjEm2UByHh0vqZ+wQy+sBx+UpHPL1aecbCGwoMleTY35fjloIfgmyqjWAG+RG2IS /LW5zjnt+cgkgAZJ2tuQ05gpqMozuP5eUY20pkmEtsZdZMGnztpqden2hZ00ynxJOU3s ohN/hPwbTmy1EJHrbzftTr0iuWMQLXG/aWdttYXQXKNW0LMmtZlA8OQg3sr3KXXH9F8G 6pCYlxRDpDkgcjp4rIG3ON4hE3/QpebEa2gjGtMByB+r3AoaeySzHUSTP1uoGKGlHBaC 49pVUKfh397yXYTChgr43y2UY5DhgL/qzB6zipc8lZjVLxUqn3NatNwLlRuFOYSEhZBf n/7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LCfLonOE7KgFGWHQRBF606Bz7FW9Av6jw+jMlTKdglU=; b=rEQxtaKrmcor/C2f6Ccx7UAy79UbTZy5ZP92SHHpi7dBByQ+ASOP+WnRtpMLJtcqT4 gvdHIGTbxjVHbkaxr9lY6Mk0vYxtFsje+ku4FDcvMmEakrVdG+RSOEQTusNqlBTOlWpE Knwx5s8IHOherLoc5IAK2ZXAG7ou18RqQipD+ZvvBl2QbOz/cfpBxmbNa5HD7TWfEIMn 9AiMMu5Z8VsMOy0OH9gfoltwXZityb7gNknRleex0HFEYv/mA3TiZrt5KFE0hFs4cuUJ UWvz7+I6QLeCIJn+PDvPU4L3N+/g2nKP4D7UrJzBsCnNBTiLD2sZLRVI5QiFHV++abNf vkOg== X-Gm-Message-State: AHQUAubHOrXOVMbWM7Rr6R+TlQHoELJPm8V6IW5slqDI3Yi7+LbY3Zq6 6nWKXxDohf5uL17vKvOr70NDNzmOfRbO7g== X-Google-Smtp-Source: AHgI3IZ5qnFvaykvZSpMDzxCHty2ke50loqiir6Rv+Z+27TB4MGBgeal0uvvFQA47b0tHeT8YQ8GKA== X-Received: by 2002:a5d:5111:: with SMTP id s17mr4318522wrt.43.1549386332221; Tue, 05 Feb 2019 09:05:32 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 5 Feb 2019 17:05:01 +0000 Message-Id: <20190205170510.21984-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190205170510.21984-1-peter.maydell@linaro.org> References: <20190205170510.21984-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::433 Subject: [Qemu-devel] [PULL 13/22] target/arm: Clean TBI for data operations in the translator X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Richard Henderson This will allow TBI to be used in user-only mode, as well as avoid ping-ponging the softmmu TLB when TBI is in use. It will also enable other armv8 extensions. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20190204132126.3255-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 217 ++++++++++++++++++++----------------- 1 file changed, 116 insertions(+), 101 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d24a083a194..e002251ac6f 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -335,6 +335,18 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 s= rc) gen_top_byte_ignore(s, cpu_pc, src, s->tbii); } =20 +/* + * Return a "clean" address for ADDR according to TBID. + * This is always a fresh temporary, as we need to be able to + * increment this independently of a dirty write-back address. + */ +static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) +{ + TCGv_i64 clean =3D new_tmp_a64(s); + gen_top_byte_ignore(s, clean, addr, s->tbid); + return clean; +} + typedef struct DisasCompare64 { TCGCond cond; TCGv_i64 value; @@ -2347,12 +2359,13 @@ static void gen_compare_and_swap(DisasContext *s, i= nt rs, int rt, TCGv_i64 tcg_rs =3D cpu_reg(s, rs); TCGv_i64 tcg_rt =3D cpu_reg(s, rt); int memidx =3D get_mem_index(s); - TCGv_i64 addr =3D cpu_reg_sp(s, rn); + TCGv_i64 clean_addr; =20 if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - tcg_gen_atomic_cmpxchg_i64(tcg_rs, addr, tcg_rs, tcg_rt, memidx, + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + tcg_gen_atomic_cmpxchg_i64(tcg_rs, clean_addr, tcg_rs, tcg_rt, memidx, size | MO_ALIGN | s->be_data); } =20 @@ -2363,12 +2376,13 @@ static void gen_compare_and_swap_pair(DisasContext = *s, int rs, int rt, TCGv_i64 s2 =3D cpu_reg(s, rs + 1); TCGv_i64 t1 =3D cpu_reg(s, rt); TCGv_i64 t2 =3D cpu_reg(s, rt + 1); - TCGv_i64 addr =3D cpu_reg_sp(s, rn); + TCGv_i64 clean_addr; int memidx =3D get_mem_index(s); =20 if (rn =3D=3D 31) { gen_check_sp_alignment(s); } + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); =20 if (size =3D=3D 2) { TCGv_i64 cmp =3D tcg_temp_new_i64(); @@ -2382,7 +2396,7 @@ static void gen_compare_and_swap_pair(DisasContext *s= , int rs, int rt, tcg_gen_concat32_i64(cmp, s2, s1); } =20 - tcg_gen_atomic_cmpxchg_i64(cmp, addr, cmp, val, memidx, + tcg_gen_atomic_cmpxchg_i64(cmp, clean_addr, cmp, val, memidx, MO_64 | MO_ALIGN | s->be_data); tcg_temp_free_i64(val); =20 @@ -2396,9 +2410,11 @@ static void gen_compare_and_swap_pair(DisasContext *= s, int rs, int rt, if (HAVE_CMPXCHG128) { TCGv_i32 tcg_rs =3D tcg_const_i32(rs); if (s->be_data =3D=3D MO_LE) { - gen_helper_casp_le_parallel(cpu_env, tcg_rs, addr, t1, t2); + gen_helper_casp_le_parallel(cpu_env, tcg_rs, + clean_addr, t1, t2); } else { - gen_helper_casp_be_parallel(cpu_env, tcg_rs, addr, t1, t2); + gen_helper_casp_be_parallel(cpu_env, tcg_rs, + clean_addr, t1, t2); } tcg_temp_free_i32(tcg_rs); } else { @@ -2414,10 +2430,10 @@ static void gen_compare_and_swap_pair(DisasContext = *s, int rs, int rt, TCGv_i64 zero =3D tcg_const_i64(0); =20 /* Load the two words, in memory order. */ - tcg_gen_qemu_ld_i64(d1, addr, memidx, + tcg_gen_qemu_ld_i64(d1, clean_addr, memidx, MO_64 | MO_ALIGN_16 | s->be_data); - tcg_gen_addi_i64(a2, addr, 8); - tcg_gen_qemu_ld_i64(d2, addr, memidx, MO_64 | s->be_data); + tcg_gen_addi_i64(a2, clean_addr, 8); + tcg_gen_qemu_ld_i64(d2, clean_addr, memidx, MO_64 | s->be_data); =20 /* Compare the two words, also in memory order. */ tcg_gen_setcond_i64(TCG_COND_EQ, c1, d1, s1); @@ -2427,7 +2443,7 @@ static void gen_compare_and_swap_pair(DisasContext *s= , int rs, int rt, /* If compare equal, write back new data, else write back old data= . */ tcg_gen_movcond_i64(TCG_COND_NE, c1, c2, zero, t1, d1); tcg_gen_movcond_i64(TCG_COND_NE, c2, c2, zero, t2, d2); - tcg_gen_qemu_st_i64(c1, addr, memidx, MO_64 | s->be_data); + tcg_gen_qemu_st_i64(c1, clean_addr, memidx, MO_64 | s->be_data); tcg_gen_qemu_st_i64(c2, a2, memidx, MO_64 | s->be_data); tcg_temp_free_i64(a2); tcg_temp_free_i64(c1); @@ -2480,7 +2496,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) int is_lasr =3D extract32(insn, 15, 1); int o2_L_o1_o0 =3D extract32(insn, 21, 3) * 2 | is_lasr; int size =3D extract32(insn, 30, 2); - TCGv_i64 tcg_addr; + TCGv_i64 clean_addr; =20 switch (o2_L_o1_o0) { case 0x0: /* STXR */ @@ -2491,8 +2507,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } - tcg_addr =3D read_cpu_reg_sp(s, rn, 1); - gen_store_exclusive(s, rs, rt, rt2, tcg_addr, size, false); + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, false); return; =20 case 0x4: /* LDXR */ @@ -2500,9 +2516,9 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - tcg_addr =3D read_cpu_reg_sp(s, rn, 1); + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); s->is_ldex =3D true; - gen_load_exclusive(s, rt, rt2, tcg_addr, size, false); + gen_load_exclusive(s, rt, rt2, clean_addr, size, false); if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); } @@ -2520,8 +2536,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) gen_check_sp_alignment(s); } tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - tcg_addr =3D read_cpu_reg_sp(s, rn, 1); - do_gpr_st(s, cpu_reg(s, rt), tcg_addr, size, true, rt, + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); return; =20 @@ -2536,8 +2552,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - tcg_addr =3D read_cpu_reg_sp(s, rn, 1); - do_gpr_ld(s, cpu_reg(s, rt), tcg_addr, size, false, false, true, r= t, + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, true,= rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); return; @@ -2550,8 +2566,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } - tcg_addr =3D read_cpu_reg_sp(s, rn, 1); - gen_store_exclusive(s, rs, rt, rt2, tcg_addr, size, true); + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, true); return; } if (rt2 =3D=3D 31 @@ -2568,9 +2584,9 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - tcg_addr =3D read_cpu_reg_sp(s, rn, 1); + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); s->is_ldex =3D true; - gen_load_exclusive(s, rt, rt2, tcg_addr, size, true); + gen_load_exclusive(s, rt, rt2, clean_addr, size, true); if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); } @@ -2619,7 +2635,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t in= sn) int opc =3D extract32(insn, 30, 2); bool is_signed =3D false; int size =3D 2; - TCGv_i64 tcg_rt, tcg_addr; + TCGv_i64 tcg_rt, clean_addr; =20 if (is_vector) { if (opc =3D=3D 3) { @@ -2641,17 +2657,17 @@ static void disas_ld_lit(DisasContext *s, uint32_t = insn) =20 tcg_rt =3D cpu_reg(s, rt); =20 - tcg_addr =3D tcg_const_i64((s->pc - 4) + imm); + clean_addr =3D tcg_const_i64((s->pc - 4) + imm); if (is_vector) { - do_fp_ld(s, rt, tcg_addr, size); + do_fp_ld(s, rt, clean_addr, size); } else { /* Only unsigned 32bit loads target 32bit registers. */ bool iss_sf =3D opc !=3D 0; =20 - do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false, + do_gpr_ld(s, tcg_rt, clean_addr, size, is_signed, false, true, rt, iss_sf, false); } - tcg_temp_free_i64(tcg_addr); + tcg_temp_free_i64(clean_addr); } =20 /* @@ -2697,7 +2713,8 @@ static void disas_ldst_pair(DisasContext *s, uint32_t= insn) bool postindex =3D false; bool wback =3D false; =20 - TCGv_i64 tcg_addr; /* calculated address */ + TCGv_i64 clean_addr, dirty_addr; + int size; =20 if (opc =3D=3D 3) { @@ -2753,23 +2770,23 @@ static void disas_ldst_pair(DisasContext *s, uint32= _t insn) gen_check_sp_alignment(s); } =20 - tcg_addr =3D read_cpu_reg_sp(s, rn, 1); - + dirty_addr =3D read_cpu_reg_sp(s, rn, 1); if (!postindex) { - tcg_gen_addi_i64(tcg_addr, tcg_addr, offset); + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); } + clean_addr =3D clean_data_tbi(s, dirty_addr); =20 if (is_vector) { if (is_load) { - do_fp_ld(s, rt, tcg_addr, size); + do_fp_ld(s, rt, clean_addr, size); } else { - do_fp_st(s, rt, tcg_addr, size); + do_fp_st(s, rt, clean_addr, size); } - tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size); + tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); if (is_load) { - do_fp_ld(s, rt2, tcg_addr, size); + do_fp_ld(s, rt2, clean_addr, size); } else { - do_fp_st(s, rt2, tcg_addr, size); + do_fp_st(s, rt2, clean_addr, size); } } else { TCGv_i64 tcg_rt =3D cpu_reg(s, rt); @@ -2781,30 +2798,28 @@ static void disas_ldst_pair(DisasContext *s, uint32= _t insn) /* Do not modify tcg_rt before recognizing any exception * from the second load. */ - do_gpr_ld(s, tmp, tcg_addr, size, is_signed, false, + do_gpr_ld(s, tmp, clean_addr, size, is_signed, false, false, 0, false, false); - tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size); - do_gpr_ld(s, tcg_rt2, tcg_addr, size, is_signed, false, + tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); + do_gpr_ld(s, tcg_rt2, clean_addr, size, is_signed, false, false, 0, false, false); =20 tcg_gen_mov_i64(tcg_rt, tmp); tcg_temp_free_i64(tmp); } else { - do_gpr_st(s, tcg_rt, tcg_addr, size, + do_gpr_st(s, tcg_rt, clean_addr, size, false, 0, false, false); - tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size); - do_gpr_st(s, tcg_rt2, tcg_addr, size, + tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); + do_gpr_st(s, tcg_rt2, clean_addr, size, false, 0, false, false); } } =20 if (wback) { if (postindex) { - tcg_gen_addi_i64(tcg_addr, tcg_addr, offset - (1 << size)); - } else { - tcg_gen_subi_i64(tcg_addr, tcg_addr, 1 << size); + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); } - tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr); + tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr); } } =20 @@ -2841,7 +2856,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, bool post_index; bool writeback; =20 - TCGv_i64 tcg_addr; + TCGv_i64 clean_addr, dirty_addr; =20 if (is_vector) { size |=3D (opc & 2) << 1; @@ -2892,17 +2907,18 @@ static void disas_ldst_reg_imm9(DisasContext *s, ui= nt32_t insn, if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - tcg_addr =3D read_cpu_reg_sp(s, rn, 1); =20 + dirty_addr =3D read_cpu_reg_sp(s, rn, 1); if (!post_index) { - tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9); + tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); } + clean_addr =3D clean_data_tbi(s, dirty_addr); =20 if (is_vector) { if (is_store) { - do_fp_st(s, rt, tcg_addr, size); + do_fp_st(s, rt, clean_addr, size); } else { - do_fp_ld(s, rt, tcg_addr, size); + do_fp_ld(s, rt, clean_addr, size); } } else { TCGv_i64 tcg_rt =3D cpu_reg(s, rt); @@ -2910,10 +2926,10 @@ static void disas_ldst_reg_imm9(DisasContext *s, ui= nt32_t insn, bool iss_sf =3D disas_ldst_compute_iss_sf(size, is_signed, opc); =20 if (is_store) { - do_gpr_st_memidx(s, tcg_rt, tcg_addr, size, memidx, + do_gpr_st_memidx(s, tcg_rt, clean_addr, size, memidx, iss_valid, rt, iss_sf, false); } else { - do_gpr_ld_memidx(s, tcg_rt, tcg_addr, size, + do_gpr_ld_memidx(s, tcg_rt, clean_addr, size, is_signed, is_extended, memidx, iss_valid, rt, iss_sf, false); } @@ -2922,9 +2938,9 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, if (writeback) { TCGv_i64 tcg_rn =3D cpu_reg_sp(s, rn); if (post_index) { - tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9); + tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); } - tcg_gen_mov_i64(tcg_rn, tcg_addr); + tcg_gen_mov_i64(tcg_rn, dirty_addr); } } =20 @@ -2963,8 +2979,7 @@ static void disas_ldst_reg_roffset(DisasContext *s, u= int32_t insn, bool is_store =3D false; bool is_extended =3D false; =20 - TCGv_i64 tcg_rm; - TCGv_i64 tcg_addr; + TCGv_i64 tcg_rm, clean_addr, dirty_addr; =20 if (extract32(opt, 1, 1) =3D=3D 0) { unallocated_encoding(s); @@ -2998,27 +3013,28 @@ static void disas_ldst_reg_roffset(DisasContext *s,= uint32_t insn, if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - tcg_addr =3D read_cpu_reg_sp(s, rn, 1); + dirty_addr =3D read_cpu_reg_sp(s, rn, 1); =20 tcg_rm =3D read_cpu_reg(s, rm, 1); ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0); =20 - tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_rm); + tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm); + clean_addr =3D clean_data_tbi(s, dirty_addr); =20 if (is_vector) { if (is_store) { - do_fp_st(s, rt, tcg_addr, size); + do_fp_st(s, rt, clean_addr, size); } else { - do_fp_ld(s, rt, tcg_addr, size); + do_fp_ld(s, rt, clean_addr, size); } } else { TCGv_i64 tcg_rt =3D cpu_reg(s, rt); bool iss_sf =3D disas_ldst_compute_iss_sf(size, is_signed, opc); if (is_store) { - do_gpr_st(s, tcg_rt, tcg_addr, size, + do_gpr_st(s, tcg_rt, clean_addr, size, true, rt, iss_sf, false); } else { - do_gpr_ld(s, tcg_rt, tcg_addr, size, + do_gpr_ld(s, tcg_rt, clean_addr, size, is_signed, is_extended, true, rt, iss_sf, false); } @@ -3052,7 +3068,7 @@ static void disas_ldst_reg_unsigned_imm(DisasContext = *s, uint32_t insn, unsigned int imm12 =3D extract32(insn, 10, 12); unsigned int offset; =20 - TCGv_i64 tcg_addr; + TCGv_i64 clean_addr, dirty_addr; =20 bool is_store; bool is_signed =3D false; @@ -3085,24 +3101,25 @@ static void disas_ldst_reg_unsigned_imm(DisasContex= t *s, uint32_t insn, if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - tcg_addr =3D read_cpu_reg_sp(s, rn, 1); + dirty_addr =3D read_cpu_reg_sp(s, rn, 1); offset =3D imm12 << size; - tcg_gen_addi_i64(tcg_addr, tcg_addr, offset); + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); + clean_addr =3D clean_data_tbi(s, dirty_addr); =20 if (is_vector) { if (is_store) { - do_fp_st(s, rt, tcg_addr, size); + do_fp_st(s, rt, clean_addr, size); } else { - do_fp_ld(s, rt, tcg_addr, size); + do_fp_ld(s, rt, clean_addr, size); } } else { TCGv_i64 tcg_rt =3D cpu_reg(s, rt); bool iss_sf =3D disas_ldst_compute_iss_sf(size, is_signed, opc); if (is_store) { - do_gpr_st(s, tcg_rt, tcg_addr, size, + do_gpr_st(s, tcg_rt, clean_addr, size, true, rt, iss_sf, false); } else { - do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, is_extended, + do_gpr_ld(s, tcg_rt, clean_addr, size, is_signed, is_extended, true, rt, iss_sf, false); } } @@ -3128,7 +3145,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32= _t insn, int rs =3D extract32(insn, 16, 5); int rn =3D extract32(insn, 5, 5); int o3_opc =3D extract32(insn, 12, 4); - TCGv_i64 tcg_rn, tcg_rs; + TCGv_i64 tcg_rs, clean_addr; AtomicThreeOpFn *fn; =20 if (is_vector || !dc_isar_feature(aa64_atomics, s)) { @@ -3171,7 +3188,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32= _t insn, if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - tcg_rn =3D cpu_reg_sp(s, rn); + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); tcg_rs =3D read_cpu_reg(s, rs, true); =20 if (o3_opc =3D=3D 1) { /* LDCLR */ @@ -3181,7 +3198,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32= _t insn, /* The tcg atomic primitives are all full barriers. Therefore we * can ignore the Acquire and Release bits of this instruction. */ - fn(cpu_reg(s, rt), tcg_rn, tcg_rs, get_mem_index(s), + fn(cpu_reg(s, rt), clean_addr, tcg_rs, get_mem_index(s), s->be_data | size | MO_ALIGN); } =20 @@ -3207,7 +3224,7 @@ static void disas_ldst_pac(DisasContext *s, uint32_t = insn, bool is_wback =3D extract32(insn, 11, 1); bool use_key_a =3D !extract32(insn, 23, 1); int offset; - TCGv_i64 tcg_addr, tcg_rt; + TCGv_i64 clean_addr, dirty_addr, tcg_rt; =20 if (size !=3D 3 || is_vector || !dc_isar_feature(aa64_pauth, s)) { unallocated_encoding(s); @@ -3217,29 +3234,31 @@ static void disas_ldst_pac(DisasContext *s, uint32_= t insn, if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - tcg_addr =3D read_cpu_reg_sp(s, rn, 1); + dirty_addr =3D read_cpu_reg_sp(s, rn, 1); =20 if (s->pauth_active) { if (use_key_a) { - gen_helper_autda(tcg_addr, cpu_env, tcg_addr, cpu_X[31]); + gen_helper_autda(dirty_addr, cpu_env, dirty_addr, cpu_X[31]); } else { - gen_helper_autdb(tcg_addr, cpu_env, tcg_addr, cpu_X[31]); + gen_helper_autdb(dirty_addr, cpu_env, dirty_addr, cpu_X[31]); } } =20 /* Form the 10-bit signed, scaled offset. */ offset =3D (extract32(insn, 22, 1) << 9) | extract32(insn, 12, 9); offset =3D sextract32(offset << size, 0, 10 + size); - tcg_gen_addi_i64(tcg_addr, tcg_addr, offset); + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); + + /* Note that "clean" and "dirty" here refer to TBI not PAC. */ + clean_addr =3D clean_data_tbi(s, dirty_addr); =20 tcg_rt =3D cpu_reg(s, rt); - - do_gpr_ld(s, tcg_rt, tcg_addr, size, /* is_signed */ false, + do_gpr_ld(s, tcg_rt, clean_addr, size, /* is_signed */ false, /* extend */ false, /* iss_valid */ !is_wback, /* iss_srt */ rt, /* iss_sf */ true, /* iss_ar */ false); =20 if (is_wback) { - tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr); + tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr); } } =20 @@ -3308,7 +3327,7 @@ static void disas_ldst_multiple_struct(DisasContext *= s, uint32_t insn) bool is_store =3D !extract32(insn, 22, 1); bool is_postidx =3D extract32(insn, 23, 1); bool is_q =3D extract32(insn, 30, 1); - TCGv_i64 tcg_addr, tcg_rn, tcg_ebytes; + TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; TCGMemOp endian =3D s->be_data; =20 int ebytes; /* bytes per element */ @@ -3391,8 +3410,7 @@ static void disas_ldst_multiple_struct(DisasContext *= s, uint32_t insn) elements =3D (is_q ? 16 : 8) / ebytes; =20 tcg_rn =3D cpu_reg_sp(s, rn); - tcg_addr =3D tcg_temp_new_i64(); - tcg_gen_mov_i64(tcg_addr, tcg_rn); + clean_addr =3D clean_data_tbi(s, tcg_rn); tcg_ebytes =3D tcg_const_i64(ebytes); =20 for (r =3D 0; r < rpt; r++) { @@ -3402,14 +3420,15 @@ static void disas_ldst_multiple_struct(DisasContext= *s, uint32_t insn) for (xs =3D 0; xs < selem; xs++) { int tt =3D (rt + r + xs) % 32; if (is_store) { - do_vec_st(s, tt, e, tcg_addr, size, endian); + do_vec_st(s, tt, e, clean_addr, size, endian); } else { - do_vec_ld(s, tt, e, tcg_addr, size, endian); + do_vec_ld(s, tt, e, clean_addr, size, endian); } - tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_ebytes); + tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); } } } + tcg_temp_free_i64(tcg_ebytes); =20 if (!is_store) { /* For non-quad operations, setting a slice of the low @@ -3427,13 +3446,11 @@ static void disas_ldst_multiple_struct(DisasContext= *s, uint32_t insn) =20 if (is_postidx) { if (rm =3D=3D 31) { - tcg_gen_mov_i64(tcg_rn, tcg_addr); + tcg_gen_addi_i64(tcg_rn, tcg_rn, rpt * elements * selem * ebyt= es); } else { tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); } } - tcg_temp_free_i64(tcg_ebytes); - tcg_temp_free_i64(tcg_addr); } =20 /* AdvSIMD load/store single structure @@ -3476,7 +3493,7 @@ static void disas_ldst_single_struct(DisasContext *s,= uint32_t insn) bool replicate =3D false; int index =3D is_q << 3 | S << 2 | size; int ebytes, xs; - TCGv_i64 tcg_addr, tcg_rn, tcg_ebytes; + TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; =20 if (extract32(insn, 31, 1)) { unallocated_encoding(s); @@ -3536,8 +3553,7 @@ static void disas_ldst_single_struct(DisasContext *s,= uint32_t insn) } =20 tcg_rn =3D cpu_reg_sp(s, rn); - tcg_addr =3D tcg_temp_new_i64(); - tcg_gen_mov_i64(tcg_addr, tcg_rn); + clean_addr =3D clean_data_tbi(s, tcg_rn); tcg_ebytes =3D tcg_const_i64(ebytes); =20 for (xs =3D 0; xs < selem; xs++) { @@ -3545,7 +3561,7 @@ static void disas_ldst_single_struct(DisasContext *s,= uint32_t insn) /* Load and replicate to all elements */ TCGv_i64 tcg_tmp =3D tcg_temp_new_i64(); =20 - tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, + tcg_gen_qemu_ld_i64(tcg_tmp, clean_addr, get_mem_index(s), s->be_data + scale); tcg_gen_gvec_dup_i64(scale, vec_full_reg_offset(s, rt), (is_q + 1) * 8, vec_full_reg_size(s), @@ -3554,24 +3570,23 @@ static void disas_ldst_single_struct(DisasContext *= s, uint32_t insn) } else { /* Load/store one element per register */ if (is_load) { - do_vec_ld(s, rt, index, tcg_addr, scale, s->be_data); + do_vec_ld(s, rt, index, clean_addr, scale, s->be_data); } else { - do_vec_st(s, rt, index, tcg_addr, scale, s->be_data); + do_vec_st(s, rt, index, clean_addr, scale, s->be_data); } } - tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_ebytes); + tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); rt =3D (rt + 1) % 32; } + tcg_temp_free_i64(tcg_ebytes); =20 if (is_postidx) { if (rm =3D=3D 31) { - tcg_gen_mov_i64(tcg_rn, tcg_addr); + tcg_gen_addi_i64(tcg_rn, tcg_rn, selem * ebytes); } else { tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); } } - tcg_temp_free_i64(tcg_ebytes); - tcg_temp_free_i64(tcg_addr); } =20 /* Loads and stores */ --=20 2.20.1 From nobody Sun May 5 05:05:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549387894107937.6078168540791; Tue, 5 Feb 2019 09:31:34 -0800 (PST) Received: from localhost ([127.0.0.1]:35578 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4ZE-0006Gw-0D for importer@patchew.org; Tue, 05 Feb 2019 12:31:28 -0500 Received: from eggs.gnu.org ([209.51.188.92]:36137) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4AX-0001y4-JY for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:06:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gr4AT-0000cQ-6p for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:57 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:37616) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gr4AS-0000Qz-MS for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:52 -0500 Received: by mail-wr1-x42c.google.com with SMTP id s12so4473393wrt.4 for ; Tue, 05 Feb 2019 09:05:35 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm5583164wmf.5.2019.02.05.09.05.32 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Feb 2019 09:05:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=qT5ac9Xbqwc5p5e64FE+VEBcJomIxNAlRbw65oVsF2E=; b=kYR3qKeEWq7473tqPvfNiW1HwiZ3G43kIUAo/WRU2w8KhhCQv8nu2SaZfGC5vsoF+C QeQOytQZO0kOtI20Fj4/ph4Hdf0AUcE9YWG5UEEpPLTsmjq+T2YFp4ndfpFrvRRRfP+a vBn4Bw9ofw8xN8FfZmOZPugnUQiCjQNkbSD3MVdIVRLbqvH5PKRnlSIzSLVpkp4QzDIc 4Q5ZohI81wNvZQekC/iUzciKOh22tTrQJ0jtoXXia9PX5dP4tQbpT5H2gpN2E9EnR4zZ qAnDhUJTLzCVFzY8i4GYnnRIGTzLd87wLy6L2FYYO0S5nH5CJ/JYdf5IH5/jhJrlBTXF GPyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qT5ac9Xbqwc5p5e64FE+VEBcJomIxNAlRbw65oVsF2E=; b=YnedbKPcG4qpnJxJWpQWnll818jhk7Hq3TmRhyZODMq2/xFdqyOY9hYunDRDvbRxnF AmBKxm6jYKjxiAvOHSmVCl1f4PLm+23CmWqX7vklZ2QrwRJiqNgQyXuzZyIoNwo8kx5c XPRqNsHseIOLQlA6Xgn2NXROLrzd+8uJMCbhv1NpdF7YilK4ejrhbwQSnBTwXIxj7mQy 7ehEVm1azvvjBZlLkw+bwuWCpcoqbxu8W6gSnBQEybeMxN+0d1XkMkFZFelS+3vAeqpc 871s6VLODKJamyT/IoH2ofXl5jAjxx//YtgFx3H3Ykj0o9DRoO4RxWR0MYDWxiwozeud 2P7g== X-Gm-Message-State: AHQUAubgucso+maLr1At0gOgTYLehdYkX42oemp0HpaDYiqRUzrbcSIp fiDwTZc5wGs9EhzUBdcK9SRh5+SlSkZGCA== X-Google-Smtp-Source: AHgI3Ib3uIKUtqOfZrOfZXArHh7f2GDe39bsme3va5c++TpmzbRWoesd2wUpfKqq4CBJSFZQ2W16ZA== X-Received: by 2002:adf:f009:: with SMTP id j9mr4385494wro.170.1549386334350; Tue, 05 Feb 2019 09:05:34 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 5 Feb 2019 17:05:02 +0000 Message-Id: <20190205170510.21984-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190205170510.21984-1-peter.maydell@linaro.org> References: <20190205170510.21984-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42c Subject: [Qemu-devel] [PULL 14/22] target/arm: Compute TB_FLAGS for TBI for user-only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Enables, but does not turn on, TBI for CONFIG_USER_ONLY. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20190204132126.3255-4-richard.henderson@linaro.org [PMM: adjusted #ifdeffery to placate clang, which otherwise complains about static functions that are unused in the CONFIG_USER_ONLY build] Signed-off-by: Peter Maydell --- target/arm/internals.h | 21 -------------------- target/arm/helper.c | 45 ++++++++++++++++++++++-------------------- 2 files changed, 24 insertions(+), 42 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index d01a3f9f44b..a4bd1becb75 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -963,30 +963,9 @@ typedef struct ARMVAParameters { bool using64k : 1; } ARMVAParameters; =20 -#ifdef CONFIG_USER_ONLY -static inline ARMVAParameters aa64_va_parameters_both(CPUARMState *env, - uint64_t va, - ARMMMUIdx mmu_idx) -{ - return (ARMVAParameters) { - /* 48-bit address space */ - .tsz =3D 16, - /* We can't handle tagged addresses properly in user-only mode */ - .tbi =3D false, - }; -} - -static inline ARMVAParameters aa64_va_parameters(CPUARMState *env, - uint64_t va, - ARMMMUIdx mmu_idx, bool d= ata) -{ - return aa64_va_parameters_both(env, va, mmu_idx); -} -#else ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx); ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data); -#endif =20 #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index 25d8ec38f8e..aaf5b0cd7ab 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7197,7 +7197,7 @@ uint32_t HELPER(rbit)(uint32_t x) return revbit32(x); } =20 -#if defined(CONFIG_USER_ONLY) +#ifdef CONFIG_USER_ONLY =20 /* These should probably raise undefined insn exceptions. */ void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) @@ -9571,6 +9571,7 @@ void arm_cpu_do_interrupt(CPUState *cs) cs->interrupt_request |=3D CPU_INTERRUPT_EXITTB; } } +#endif /* !CONFIG_USER_ONLY */ =20 /* Return the exception level which controls this address translation regi= me */ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) @@ -9600,6 +9601,8 @@ static inline uint32_t regime_el(CPUARMState *env, AR= MMMUIdx mmu_idx) } } =20 +#ifndef CONFIG_USER_ONLY + /* Return the SCTLR value which controls this address translation regime */ static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) { @@ -9655,6 +9658,22 @@ static inline bool regime_translation_big_endian(CPU= ARMState *env, return (regime_sctlr(env, mmu_idx) & SCTLR_EE) !=3D 0; } =20 +/* Return the TTBR associated with this translation regime */ +static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, + int ttbrn) +{ + if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { + return env->cp15.vttbr_el2; + } + if (ttbrn =3D=3D 0) { + return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; + } else { + return env->cp15.ttbr1_el[regime_el(env, mmu_idx)]; + } +} + +#endif /* !CONFIG_USER_ONLY */ + /* Return the TCR controlling this translation regime */ static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) { @@ -9675,20 +9694,6 @@ static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mm= u_idx) return mmu_idx; } =20 -/* Return the TTBR associated with this translation regime */ -static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, - int ttbrn) -{ - if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { - return env->cp15.vttbr_el2; - } - if (ttbrn =3D=3D 0) { - return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; - } else { - return env->cp15.ttbr1_el[regime_el(env, mmu_idx)]; - } -} - /* Return true if the translation regime is using LPAE format page tables = */ static inline bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) @@ -9714,6 +9719,7 @@ bool arm_s1_regime_using_lpae_format(CPUARMState *env= , ARMMMUIdx mmu_idx) return regime_using_lpae_format(env, mmu_idx); } =20 +#ifndef CONFIG_USER_ONLY static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { @@ -10419,6 +10425,7 @@ static uint8_t convert_stage2_attrs(CPUARMState *en= v, uint8_t s2attrs) =20 return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint; } +#endif /* !CONFIG_USER_ONLY */ =20 ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx) @@ -10490,6 +10497,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env= , uint64_t va, return ret; } =20 +#ifndef CONFIG_USER_ONLY static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, ARMMMUIdx mmu_idx) { @@ -13746,11 +13754,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target= _ulong *pc, *pc =3D env->pc; flags =3D FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); =20 -#ifndef CONFIG_USER_ONLY - /* - * Get control bits for tagged addresses. Note that the - * translator only uses this for instruction addresses. - */ + /* Get control bits for tagged addresses. */ { ARMMMUIdx stage1 =3D stage_1_mmu_idx(mmu_idx); ARMVAParameters p0 =3D aa64_va_parameters_both(env, 0, stage1); @@ -13769,7 +13773,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, flags =3D FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); flags =3D FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); } -#endif =20 if (cpu_isar_feature(aa64_sve, cpu)) { int sve_el =3D sve_exception_el(env, current_el); --=20 2.20.1 From nobody Sun May 5 05:05:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549388269485321.15239219875457; Tue, 5 Feb 2019 09:37:49 -0800 (PST) Received: from localhost ([127.0.0.1]:35679 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4fH-0002lO-DV for importer@patchew.org; Tue, 05 Feb 2019 12:37:43 -0500 Received: from eggs.gnu.org ([209.51.188.92]:35968) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4AT-0001uZ-Gi for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gr4AR-0000ZU-US for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:53 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:37706) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gr4AR-0000RM-KG for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:51 -0500 Received: by mail-wr1-x444.google.com with SMTP id s12so4473467wrt.4 for ; Tue, 05 Feb 2019 09:05:36 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm5583164wmf.5.2019.02.05.09.05.34 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Feb 2019 09:05:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ft812SCqjDNcxm1YSB5FAtkk2YQoYTLtVW3eozeb91o=; b=uiEVqcclshG4ltomh0/YBadOVsU7Nmz2cYtwj6LT9Ba1mWLVkiQ2F9mqZXAhJMf/Ae hUJd71EumCK6tQzyVqaIKvTskNhaQzMw4ZQJ1y7Z71S9lfHtEqM9Nrs0EYJVGXiA68IR uwH+YVQdSDqHb/QtcCAjtzIfy0i1YLEbmzfAFvp65tanx1sfFbssNYo8W3ioHqvCmMCx 8IKroQbq5xN/9vTv6y55XKh3kSiD48L5ETNOs5iAmrPCjZUt91dNMbP6r9qlEGd5mXvh b0Eir1Rnc60a5seoB0nCal6HzxxS+pJDc8bSqnE/9kL1KZ/XeZWmGVdMWl+czpRK/kd4 FH3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ft812SCqjDNcxm1YSB5FAtkk2YQoYTLtVW3eozeb91o=; b=MVK08Ggodl7mF/XFUjZfTqoKQkmR1+De5XNettW4VEIv7f0WpqOP1MkhYlEE6Xtf7M Rr6G6h1bAGN8CV5binZQrZnyr82VMmk0ERPKdIYJxXVW6bpM4muPqxfEL4N6gu2PghvI uc2Lo+1yTV5I+ls8XQQMF6RmbZehl2FMpXPOsbgUoVijbzkrWaQNFoRHJpHA6rZ6MhDK JBXpzecBVnxsmYzy40wjZod5yGYsctZLiOJJNzmENe4dhgY88c7R0htEqsN6ur9W2lbP YFcDoXV3VHOvYWWTezfGWpxJ2G/WDkGbPRgmnJ606rYI21AprzYozEq/+wgNN+QuWKH0 p/bQ== X-Gm-Message-State: AHQUAuZYYuhRD4R3DEz9lwjtQMtDeBdzTFiFIzMHduf8uUI80vJxW6VB vmtrBGLYNEnnk1Lx8sXvIIWS+ZtU7VFKEQ== X-Google-Smtp-Source: AHgI3IY4/vJfGKcf1It5gCkKWKMuqHw4Kp+/lk00iVdqtBSQYbEI9UJL0NAhXyQax02u0deUEzTv0Q== X-Received: by 2002:a5d:44cd:: with SMTP id z13mr4286907wrr.69.1549386335655; Tue, 05 Feb 2019 09:05:35 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 5 Feb 2019 17:05:03 +0000 Message-Id: <20190205170510.21984-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190205170510.21984-1-peter.maydell@linaro.org> References: <20190205170510.21984-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PULL 15/22] target/arm: Enable TBI for user-only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Richard Henderson This has been enabled in the linux kernel since v3.11 (commit d50240a5f6cea, 2013-09-03, "arm64: mm: permit use of tagged pointers at EL0"). Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20190204132126.3255-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 3874dc98754..edf6e0e1f1c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -200,6 +200,12 @@ static void arm_cpu_reset(CPUState *s) env->vfp.zcr_el[1] =3D cpu->sve_max_vq - 1; env->vfp.zcr_el[2] =3D env->vfp.zcr_el[1]; env->vfp.zcr_el[3] =3D env->vfp.zcr_el[1]; + /* + * Enable TBI0 and TBI1. While the real kernel only enables TBI0, + * turning on both here will produce smaller code and otherwise + * make no difference to the user-level emulation. + */ + env->cp15.tcr_el[1].raw_tcr =3D (3ULL << 37); #else /* Reset into the highest available EL */ if (arm_feature(env, ARM_FEATURE_EL3)) { --=20 2.20.1 From nobody Sun May 5 05:05:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549389327139454.1940178462463; Tue, 5 Feb 2019 09:55:27 -0800 (PST) Received: from localhost ([127.0.0.1]:35995 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4wL-0000Ou-2x for importer@patchew.org; Tue, 05 Feb 2019 12:55:21 -0500 Received: from eggs.gnu.org ([209.51.188.92]:36111) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4AX-0001xZ-2y for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:06:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gr4AS-0000bm-TD for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:56 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:34828) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gr4AS-0000Rl-Ie for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:52 -0500 Received: by mail-wr1-x430.google.com with SMTP id z18so3711701wrh.2 for ; Tue, 05 Feb 2019 09:05:38 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm5583164wmf.5.2019.02.05.09.05.35 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Feb 2019 09:05:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=sRHyGt2WrxOz1ceatNUSLiFKWMvfFAX+kynWppRwgiI=; b=hWVpfg4Kbzv1dSm7rfYcitMEdjOsL5UHYI75s/IQhpyNdM0cP+XueKs3wk3wBr+RuP N2VM9LfdBy12ldOy1bR0cI6SNfpSEgchbYiMqCNN81/OocGnMdq/bv72ndKZjdITiUAq /iSbvwwLwTWiMWo28AsKO8HLrJL8a825mh3MfTzNZ6aOxdBuWMgvAG3UfcBvLKcvu0Ys 0FBz8a8nscna+/UY1LGzTPlMU3fX29IYhgBNl3E/33kZcY4OeGj4i7pmRDoXpNJ9EZhv +nxEQP/n6wBtlt5ov28Z/CUee9NNuPuoW3EkQQ5pCYvtNJT2ZCq4YSYsCNShuLN/ng1C 1PAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sRHyGt2WrxOz1ceatNUSLiFKWMvfFAX+kynWppRwgiI=; b=f7WMMH2LlW4ETbZpA3L4pI+wDw77cEGV4ns+xPZgVNimVbsEGxRF3CZg9sWaj/6EtL Kp9K/JjWLYmnQMUIB6a8qt2Uspx5gJ6w/kBCaCksiXibdsOq7lPiW5SBpYKAfl3Rs83K tz+n6zW9/Q1ydcFyyzRz92q9BqgII4Lm3jcTxAiXcjHUKQjbgJXobrvgU3kUiRpbhnmx D1NAQuPzMaHq0BEM50K4xczsSpa1cfHVy4iPp1oBEB0VDU1mLLYuIF+0Zo02aPWJ8QHN TGWq9ir5TqPL2Iu3yFDm6ZMEljthkuqPPJhP0jtMhkisDF35Rh5VyjOad6KqnCIIoF7L ojjA== X-Gm-Message-State: AHQUAuaarzy1wb0b7WBEqH1HmCXdFFGR0di+B9Sa7w7HYAVAluMqwX7N AFH7Ba6Moq95ABTDK20U675EV6XLgZZaLA== X-Google-Smtp-Source: AHgI3IYryEjFzdA4iT6vNtEXQ3K/lhrt6ZGSwaq7xv0ZgixIe2aJ/S6BMbN9T9YEoT4r/iwKaxi8/w== X-Received: by 2002:a5d:5008:: with SMTP id e8mr1694152wrt.57.1549386337004; Tue, 05 Feb 2019 09:05:37 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 5 Feb 2019 17:05:04 +0000 Message-Id: <20190205170510.21984-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190205170510.21984-1-peter.maydell@linaro.org> References: <20190205170510.21984-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::430 Subject: [Qemu-devel] [PULL 16/22] gdbstub: allow killing QEMU via vKill command X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Max Filippov With multiprocess extensions gdb uses 'vKill' packet instead of 'k' to kill the inferior. Handle 'vKill' the same way 'k' was handled in the presence of single process. Fixes: 7cf48f6752e5 ("gdbstub: add multiprocess support to (f|s)ThreadInfo and ThreadExtraInfo") Cc: Luc Michel Signed-off-by: Max Filippov Reviewed-by: Luc Michel Reviewed-by: KONRAD Frederic Tested-by: KONRAD Frederic Message-id: 20190130192403.13754-1-jcmvbkbc@gmail.com Signed-off-by: Peter Maydell --- gdbstub.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/gdbstub.c b/gdbstub.c index 3129b5c2842..a4be63f6eb4 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -1359,6 +1359,10 @@ static int gdb_handle_packet(GDBState *s, const char= *line_buf) =20 put_packet(s, buf); break; + } else if (strncmp(p, "Kill;", 5) =3D=3D 0) { + /* Kill the target */ + error_report("QEMU: Terminated via GDBstub"); + exit(0); } else { goto unknown_command; } --=20 2.20.1 From nobody Sun May 5 05:05:30 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549388625948525.7039583948132; Tue, 5 Feb 2019 09:43:45 -0800 (PST) Received: from localhost ([127.0.0.1]:35784 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4kw-0007zI-O5 for importer@patchew.org; Tue, 05 Feb 2019 12:43:34 -0500 Received: from eggs.gnu.org ([209.51.188.92]:36064) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4AV-0001vW-Db for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:06:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gr4AR-0000Z7-Ke for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:55 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:37705) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gr4AR-0000Rt-C0 for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:51 -0500 Received: by mail-wr1-x442.google.com with SMTP id s12so4473707wrt.4 for ; Tue, 05 Feb 2019 09:05:40 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm5583164wmf.5.2019.02.05.09.05.37 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Feb 2019 09:05:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=K5npKx6n/vRln5RFgvocN/O1CXk1/9HDCQe/KYXo6m0=; b=olnvcZyhNKBcbIWeczt/tugNhc+GnAhGcUMkpEwouAsnBS9WT3g3/Kfu9ZscYe/Dk5 CI4AWoKMWabFO88igHyHckY3HfA5PEOcSnHrzVkmLaW/exe1UFCZogV3xhkL9b3VQfNx f7I7tNDRD+FNgCvlujcTm9EGFk0njOSRhy/Nez9VDg1z/uELrKiMLSke+Jh8MOF+E/Tu ePsX4zpVpqCVhaC9zQRUaJS+E5HLJGUrrqHT088n4sS7fm5sjDRBIM6a72MmY07DiFeD tt9VFJAI8fUVx8rwU0y/tWZgT79VHEbrSZ/X/IPaW3oR3mKQ3C/aQ+xHbQaibdjXpIN3 Vjhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=K5npKx6n/vRln5RFgvocN/O1CXk1/9HDCQe/KYXo6m0=; b=gZzNYqHsKYVys3Wr4Z4Hv4pJMwpaalbG8RKvVTqDHAZv4XkzbP9XT7qGl4kGd5AeGl jt6PjqyZpMiUNAIljD8DqyID7m56bkYIh84hMTehPAveAV4hbLbV1y9CpxE5yLtPV97G GffDQYb/Ub972e5kKoM3S8SJpiDlh/3wiV9UO0RwpsCbLpb1MUmf8k1luaTQ1t/80rew 682C6Xzgl5oSeD20hricsFTf4QmdqrwIDWHmagylORweWnJcqfmubOvdkR7xY4Kl3kW/ WHX9Y1TydXx90YMKprFnszCunFSgazsD+vNddpNFZHiju5LRWU9KDVBKHFoYN5bhf8yP crAg== X-Gm-Message-State: AHQUAuY8BV92mVQhpBnbBdhCgZZGEz3DatEUSnY7prvD2oWQILlvFexe oC0dJGLj9bPajo9iVSSiBfTAJQhdvpVERg== X-Google-Smtp-Source: AHgI3IbSYXZ28EzdGFEJ7lqTI1LlLuoNvGV14wZ0fblxlX37LTQuGGDHsyo0DaZM4Klj5pFFBl5YdA== X-Received: by 2002:adf:9226:: with SMTP id 35mr4437291wrj.61.1549386338425; Tue, 05 Feb 2019 09:05:38 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 5 Feb 2019 17:05:05 +0000 Message-Id: <20190205170510.21984-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190205170510.21984-1-peter.maydell@linaro.org> References: <20190205170510.21984-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PULL 17/22] hw/arm/boot: Fix block comment style in arm_load_kernel() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Fix the block comment style in arm_load_kernel() to QEMU's current style preferences. This will allow us to do some refactoring of this function without checkpatch complaining about the code-motion patches. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Igor Mammedov Message-id: 20190131112240.8395-2-peter.maydell@linaro.org --- hw/arm/boot.c | 30 ++++++++++++++++++++---------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 05762d0fc1b..dcb93fdbe2c 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -961,7 +961,8 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info = *info) static const ARMInsnFixup *primary_loader; AddressSpace *as =3D arm_boot_address_space(cpu, info); =20 - /* CPU objects (unlike devices) are not automatically reset on system + /* + * CPU objects (unlike devices) are not automatically reset on system * reset, so we must always register a handler to do so. If we're * actually loading a kernel, the handler is also responsible for * arranging that we start it correctly. @@ -970,7 +971,8 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info = *info) qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); } =20 - /* The board code is not supposed to set secure_board_setup unless + /* + * The board code is not supposed to set secure_board_setup unless * running its code in secure mode is actually possible, and KVM * doesn't support secure. */ @@ -983,7 +985,8 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info = *info) if (!info->kernel_filename || info->firmware_loaded) { =20 if (have_dtb(info)) { - /* If we have a device tree blob, but no kernel to supply it t= o (or + /* + * If we have a device tree blob, but no kernel to supply it t= o (or * the kernel is supposed to be loaded by the bootloader), cop= y the * DTB to the base of RAM for the bootloader to pick up. */ @@ -998,7 +1001,8 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info= *info) try_decompressing_kernel =3D arm_feature(&cpu->env, ARM_FEATURE_AARCH64); =20 - /* Expose the kernel, the command line, and the initrd in fw_c= fg. + /* + * Expose the kernel, the command line, and the initrd in fw_c= fg. * We don't process them here at all, it's all left to the * firmware. */ @@ -1018,7 +1022,8 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_inf= o *info) } } =20 - /* We will start from address 0 (typically a boot ROM image) in the + /* + * We will start from address 0 (typically a boot ROM image) in the * same way as hardware. */ return; @@ -1045,7 +1050,8 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_inf= o *info) if (info->nb_cpus =3D=3D 0) info->nb_cpus =3D 1; =20 - /* We want to put the initrd far enough into RAM that when the + /* + * We want to put the initrd far enough into RAM that when the * kernel is uncompressed it will not clobber the initrd. However * on boards without much RAM we must ensure that we still leave * enough room for a decent sized initrd, and on boards with large @@ -1062,12 +1068,14 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_i= nfo *info) kernel_size =3D arm_load_elf(info, &elf_entry, &elf_low_addr, &elf_high_addr, elf_machine, as); if (kernel_size > 0 && have_dtb(info)) { - /* If there is still some room left at the base of RAM, try and put + /* + * If there is still some room left at the base of RAM, try and put * the DTB there like we do for images loaded with -bios or -pflas= h. */ if (elf_low_addr > info->loader_start || elf_high_addr < info->loader_start) { - /* Set elf_low_addr as address limit for arm_load_dtb if it ma= y be + /* + * Set elf_low_addr as address limit for arm_load_dtb if it ma= y be * pointing into RAM, otherwise pass '0' (no limit) */ if (elf_low_addr < info->loader_start) { @@ -1128,7 +1136,8 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_inf= o *info) fixupcontext[FIXUP_BOARDID] =3D info->board_id; fixupcontext[FIXUP_BOARD_SETUP] =3D info->board_setup_addr; =20 - /* for device tree boot, we pass the DTB directly in r2. Otherwise + /* + * for device tree boot, we pass the DTB directly in r2. Otherwise * we point to the kernel args. */ if (have_dtb(info)) { @@ -1181,7 +1190,8 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_inf= o *info) info->write_board_setup(cpu, info); } =20 - /* Notify devices which need to fake up firmware initialization + /* + * Notify devices which need to fake up firmware initialization * that we're doing a direct kernel boot. */ object_child_foreach_recursive(object_get_root(), --=20 2.20.1 From nobody Sun May 5 05:05:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549388344976236.12372133217934; Tue, 5 Feb 2019 09:39:04 -0800 (PST) Received: from localhost ([127.0.0.1]:35687 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4gS-0003gM-RW for importer@patchew.org; Tue, 05 Feb 2019 12:38:56 -0500 Received: from eggs.gnu.org ([209.51.188.92]:36134) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4AX-0001xx-Fe for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:06:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gr4AS-0000bW-QI for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:57 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:42445) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gr4AS-0000S3-D6 for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:52 -0500 Received: by mail-wr1-x443.google.com with SMTP id q18so4437537wrx.9 for ; Tue, 05 Feb 2019 09:05:41 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm5583164wmf.5.2019.02.05.09.05.38 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Feb 2019 09:05:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=r8pMtK2RfcmJu7msdfJvjid6eFMuDR8qDxKpRGadMs4=; b=UVJVT7+leifeM5zV7MNcJV8XDfDZdCqE6q46jqCM4MxPx9gzqQPEQ4ZUDSkz5qJg96 FAQ9qa6Oxbg1uBzXAOMUGEaKkdbkIntSQyfelnsgCOeXc4E9OSGEjE0LypLYfIfpksE9 wqbjKYgLZ5VKH2XSIeooKq4cWQ3GbyVYzWAwb7b/bvCElTXmJf0MIMoBJA7bUKvshNU4 ZLT3CkrE9sTRnkLFPDgDAHMVd0+0uipciWdnSrY6NXQ4DUINJpm4vuLALuG6blyWZXq6 KQF9S33GYwSARHhMZ4NT0tR/oRPFbocNmL1HWMrb8f1mlE033JgdPGPmC/t6Vbe3HGwO fcfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=r8pMtK2RfcmJu7msdfJvjid6eFMuDR8qDxKpRGadMs4=; b=VpioAwIStagV00L008OgfJppzkWPcl+RdYsx9f2++cP7ww+Vt5Y0o/Pwhnfp94GJBY upgtKjFVfBWlMdj38znfM4fmrampOoPG0JWdEspnLJ2D/N0cXdyAC3ImHIunadiPMZeh 1yhO12euOEUbKbSf1Mms+NU29SwxeMkkVEtkLo5l1C9pKV020u7NfrAZcS6KTFLRi+TQ KO1Ex81wfaTOQbJA60Voh07o6AiMafvZuJ5fOdSxy3nl8so3RtRt7+hmcS7BNHQtga1W NxRTqtumJAX8WBlhmUpUv859a+FKR3roy/pj/Se8JcRB6vEhB/3oYZsdasOdLmXRYjMh 9qSg== X-Gm-Message-State: AHQUAuZ+Rd0YC59a66vkIvpk4+9gCQO3tdRvE0+GYUl8hBZA3ChE8npg AzCybaDqKFO34KdYDFyFOcl/AXlIPc078g== X-Google-Smtp-Source: AHgI3IadvCgdFm2/NyjGdkN1NlE9rNyplf3wKVPtlae0ApjYDMxMoncYAWZ8dWh0KCA4JCVqql7eJQ== X-Received: by 2002:adf:f9ca:: with SMTP id w10mr4443294wrr.189.1549386339883; Tue, 05 Feb 2019 09:05:39 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 5 Feb 2019 17:05:06 +0000 Message-Id: <20190205170510.21984-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190205170510.21984-1-peter.maydell@linaro.org> References: <20190205170510.21984-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PULL 18/22] hw/arm/boot: Factor out "direct kernel boot" code into its own function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Factor out the "direct kernel boot" code path from arm_load_kernel() into its own function; this function is getting long enough that the code flow is a bit confusing. This commit only moves code around; no semantic changes. We leave the "load the dtb" code in arm_load_kernel() -- this is currently only used by the "direct kernel boot" path, but this is a bug which we will fix shortly. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Igor Mammedov Message-id: 20190131112240.8395-3-peter.maydell@linaro.org --- hw/arm/boot.c | 150 +++++++++++++++++++++++++++----------------------- 1 file changed, 80 insertions(+), 70 deletions(-) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index dcb93fdbe2c..cd7373a8da2 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -949,9 +949,12 @@ static uint64_t load_aarch64_image(const char *filenam= e, hwaddr mem_base, return size; } =20 -void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) +static void arm_setup_direct_kernel_boot(ARMCPU *cpu, + struct arm_boot_info *info) { + /* Set up for a direct boot of a kernel image file. */ CPUState *cs; + AddressSpace *as =3D arm_boot_address_space(cpu, info); int kernel_size; int initrd_size; int is_linux =3D 0; @@ -959,75 +962,6 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info= *info) int elf_machine; hwaddr entry; static const ARMInsnFixup *primary_loader; - AddressSpace *as =3D arm_boot_address_space(cpu, info); - - /* - * CPU objects (unlike devices) are not automatically reset on system - * reset, so we must always register a handler to do so. If we're - * actually loading a kernel, the handler is also responsible for - * arranging that we start it correctly. - */ - for (cs =3D first_cpu; cs; cs =3D CPU_NEXT(cs)) { - qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); - } - - /* - * The board code is not supposed to set secure_board_setup unless - * running its code in secure mode is actually possible, and KVM - * doesn't support secure. - */ - assert(!(info->secure_board_setup && kvm_enabled())); - - info->dtb_filename =3D qemu_opt_get(qemu_get_machine_opts(), "dtb"); - info->dtb_limit =3D 0; - - /* Load the kernel. */ - if (!info->kernel_filename || info->firmware_loaded) { - - if (have_dtb(info)) { - /* - * If we have a device tree blob, but no kernel to supply it t= o (or - * the kernel is supposed to be loaded by the bootloader), cop= y the - * DTB to the base of RAM for the bootloader to pick up. - */ - info->dtb_start =3D info->loader_start; - } - - if (info->kernel_filename) { - FWCfgState *fw_cfg; - bool try_decompressing_kernel; - - fw_cfg =3D fw_cfg_find(); - try_decompressing_kernel =3D arm_feature(&cpu->env, - ARM_FEATURE_AARCH64); - - /* - * Expose the kernel, the command line, and the initrd in fw_c= fg. - * We don't process them here at all, it's all left to the - * firmware. - */ - load_image_to_fw_cfg(fw_cfg, - FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, - info->kernel_filename, - try_decompressing_kernel); - load_image_to_fw_cfg(fw_cfg, - FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, - info->initrd_filename, false); - - if (info->kernel_cmdline) { - fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, - strlen(info->kernel_cmdline) + 1); - fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, - info->kernel_cmdline); - } - } - - /* - * We will start from address 0 (typically a boot ROM image) in the - * same way as hardware. - */ - return; - } =20 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { primary_loader =3D bootloader_aarch64; @@ -1202,6 +1136,82 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_in= fo *info) for (cs =3D first_cpu; cs; cs =3D CPU_NEXT(cs)) { ARM_CPU(cs)->env.boot_info =3D info; } +} + +void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) +{ + CPUState *cs; + AddressSpace *as =3D arm_boot_address_space(cpu, info); + + /* + * CPU objects (unlike devices) are not automatically reset on system + * reset, so we must always register a handler to do so. If we're + * actually loading a kernel, the handler is also responsible for + * arranging that we start it correctly. + */ + for (cs =3D first_cpu; cs; cs =3D CPU_NEXT(cs)) { + qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); + } + + /* + * The board code is not supposed to set secure_board_setup unless + * running its code in secure mode is actually possible, and KVM + * doesn't support secure. + */ + assert(!(info->secure_board_setup && kvm_enabled())); + + info->dtb_filename =3D qemu_opt_get(qemu_get_machine_opts(), "dtb"); + info->dtb_limit =3D 0; + + /* Load the kernel. */ + if (!info->kernel_filename || info->firmware_loaded) { + + if (have_dtb(info)) { + /* + * If we have a device tree blob, but no kernel to supply it t= o (or + * the kernel is supposed to be loaded by the bootloader), cop= y the + * DTB to the base of RAM for the bootloader to pick up. + */ + info->dtb_start =3D info->loader_start; + } + + if (info->kernel_filename) { + FWCfgState *fw_cfg; + bool try_decompressing_kernel; + + fw_cfg =3D fw_cfg_find(); + try_decompressing_kernel =3D arm_feature(&cpu->env, + ARM_FEATURE_AARCH64); + + /* + * Expose the kernel, the command line, and the initrd in fw_c= fg. + * We don't process them here at all, it's all left to the + * firmware. + */ + load_image_to_fw_cfg(fw_cfg, + FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, + info->kernel_filename, + try_decompressing_kernel); + load_image_to_fw_cfg(fw_cfg, + FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, + info->initrd_filename, false); + + if (info->kernel_cmdline) { + fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, + strlen(info->kernel_cmdline) + 1); + fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, + info->kernel_cmdline); + } + } + + /* + * We will start from address 0 (typically a boot ROM image) in the + * same way as hardware. + */ + return; + } else { + arm_setup_direct_kernel_boot(cpu, info); + } =20 if (!info->skip_dtb_autoload && have_dtb(info)) { if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) { --=20 2.20.1 From nobody Sun May 5 05:05:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549388109825917.2683186718125; Tue, 5 Feb 2019 09:35:09 -0800 (PST) Received: from localhost ([127.0.0.1]:35612 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4ch-0000U2-MN for importer@patchew.org; Tue, 05 Feb 2019 12:35:03 -0500 Received: from eggs.gnu.org ([209.51.188.92]:36206) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4AZ-0001zf-W7 for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:06:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gr4AT-0000cJ-7u for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:59 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:55007) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gr4AS-0000TV-OX for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:52 -0500 Received: by mail-wm1-x336.google.com with SMTP id a62so4449531wmh.4 for ; Tue, 05 Feb 2019 09:05:42 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm5583164wmf.5.2019.02.05.09.05.39 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Feb 2019 09:05:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=xP5Vb42Qvz2Z9D5/Z8GqBAI9BSFPshBAy9apTqTJVpE=; b=RABjv4wDHQY8gzp4KP5a6/LzsPTgCNjvfwXbh+UZMdpDDOIilmIx9JhsB7gcbHXVvv Es5rSi435PhZSKtpuFEALjsd5AlOOpjH1p2TjlwpxGnqKMZaW+a4ZNJyWaFdYuz9J1xT Wdgk/911ziGHaAR2O8qkfVcJ1a2qgvQHuaoHve5HXEMo5Srhdi6z9b6IzlQc7VRg6fpR ggpcRtHqF3QhJwWJXNQmY/oN+QIK/Kopr3j+68zFxywstrg7hVQZlgUCzjvW0vnO4U0u u7r0ISSnQxHDQld6hIimMPb+UTQyXYvT3dunqI/ZkxeDy67BOTbSeU4cvWnRMVeBunhN TpHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xP5Vb42Qvz2Z9D5/Z8GqBAI9BSFPshBAy9apTqTJVpE=; b=T+L0CdmZP2wv9NZ1kRegOtP1FZ1wHwayraeXBUce44CeniNBWd15EVCVQLoLtLBrCl pPKe0ETvTcGM+mdZvZwT4Z7dobK/mezmGMxJSS/iTSU9UuPMfYab5ZapVVMeYH5GLJX3 al1kzBDmulplE51Kdki/IwRQcv2Lvccjzv8IvqVIZcXGTYYQ7UBYxymik+s0uqxixTmV 2rmSWJH/WkoqzEFveCuZaVKvfaXGDFMmiv12byqU543ln3NpqaVVB5Wlgt5gCA/Npk5t U8/Mxzz7gALspr8Y0MEpVzSqbsShyirwWaK7qKJcKwDOd/BUFLa6LJbrBl9gWCc1QrkK BJBQ== X-Gm-Message-State: AHQUAua6G7grafvnkXsqVGW2dV7EZL0xDoT0m0ZUFWpjr3i+noXYKlBM 5JvsgbKxrt/fKHJ6yJegyXav0ZvaajhOJA== X-Google-Smtp-Source: AHgI3IbExoh4BAUQhD229d2DzlbWv3DIH1kTczOI5xp2mDCe5HYwaU+11HcL91B9KvHShMy/e9Jc1w== X-Received: by 2002:a1c:a895:: with SMTP id r143mr4320106wme.95.1549386341239; Tue, 05 Feb 2019 09:05:41 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 5 Feb 2019 17:05:07 +0000 Message-Id: <20190205170510.21984-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190205170510.21984-1-peter.maydell@linaro.org> References: <20190205170510.21984-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::336 Subject: [Qemu-devel] [PULL 19/22] hw/arm/boot: Factor out "set up firmware boot" code X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Factor out the "boot via firmware" code path from arm_load_kernel() into its own function. This commit only moves code around; no semantic changes. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Igor Mammedov Message-id: 20190131112240.8395-4-peter.maydell@linaro.org --- hw/arm/boot.c | 92 +++++++++++++++++++++++++++------------------------ 1 file changed, 49 insertions(+), 43 deletions(-) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index cd7373a8da2..2d4f710395f 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -1138,6 +1138,54 @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu, } } =20 +static void arm_setup_firmware_boot(ARMCPU *cpu, struct arm_boot_info *inf= o) +{ + /* Set up for booting firmware (which might load a kernel via fw_cfg) = */ + + if (have_dtb(info)) { + /* + * If we have a device tree blob, but no kernel to supply it to (or + * the kernel is supposed to be loaded by the bootloader), copy the + * DTB to the base of RAM for the bootloader to pick up. + */ + info->dtb_start =3D info->loader_start; + } + + if (info->kernel_filename) { + FWCfgState *fw_cfg; + bool try_decompressing_kernel; + + fw_cfg =3D fw_cfg_find(); + try_decompressing_kernel =3D arm_feature(&cpu->env, + ARM_FEATURE_AARCH64); + + /* + * Expose the kernel, the command line, and the initrd in fw_cfg. + * We don't process them here at all, it's all left to the + * firmware. + */ + load_image_to_fw_cfg(fw_cfg, + FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, + info->kernel_filename, + try_decompressing_kernel); + load_image_to_fw_cfg(fw_cfg, + FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, + info->initrd_filename, false); + + if (info->kernel_cmdline) { + fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, + strlen(info->kernel_cmdline) + 1); + fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, + info->kernel_cmdline); + } + } + + /* + * We will start from address 0 (typically a boot ROM image) in the + * same way as hardware. + */ +} + void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) { CPUState *cs; @@ -1165,49 +1213,7 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_in= fo *info) =20 /* Load the kernel. */ if (!info->kernel_filename || info->firmware_loaded) { - - if (have_dtb(info)) { - /* - * If we have a device tree blob, but no kernel to supply it t= o (or - * the kernel is supposed to be loaded by the bootloader), cop= y the - * DTB to the base of RAM for the bootloader to pick up. - */ - info->dtb_start =3D info->loader_start; - } - - if (info->kernel_filename) { - FWCfgState *fw_cfg; - bool try_decompressing_kernel; - - fw_cfg =3D fw_cfg_find(); - try_decompressing_kernel =3D arm_feature(&cpu->env, - ARM_FEATURE_AARCH64); - - /* - * Expose the kernel, the command line, and the initrd in fw_c= fg. - * We don't process them here at all, it's all left to the - * firmware. - */ - load_image_to_fw_cfg(fw_cfg, - FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, - info->kernel_filename, - try_decompressing_kernel); - load_image_to_fw_cfg(fw_cfg, - FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, - info->initrd_filename, false); - - if (info->kernel_cmdline) { - fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, - strlen(info->kernel_cmdline) + 1); - fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, - info->kernel_cmdline); - } - } - - /* - * We will start from address 0 (typically a boot ROM image) in the - * same way as hardware. - */ + arm_setup_firmware_boot(cpu, info); return; } else { arm_setup_direct_kernel_boot(cpu, info); --=20 2.20.1 From nobody Sun May 5 05:05:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549389669483246.20668289402283; Tue, 5 Feb 2019 10:01:09 -0800 (PST) Received: from localhost ([127.0.0.1]:36110 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr51r-0005dT-6O for importer@patchew.org; Tue, 05 Feb 2019 13:01:03 -0500 Received: from eggs.gnu.org ([209.51.188.92]:35995) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4AU-0001ub-2F for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:06:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gr4AR-0000Zf-Vd for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:53 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:42883) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gr4AR-0000U6-N7 for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:51 -0500 Received: by mail-wr1-x42c.google.com with SMTP id q18so4437705wrx.9 for ; Tue, 05 Feb 2019 09:05:43 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm5583164wmf.5.2019.02.05.09.05.41 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Feb 2019 09:05:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ZNrlTmh7hRCK4ChDppa6LEEimFwQDqMaFB6OVXrQOZs=; b=W3mZ24Fw8PMI0oWoGJ8p5bRKeOaHLVigPi5o3KF/WyhT3IfK0BTImPHoau2/awUW+E DSrXhW4Goc1gtMiDd0IWNGuk2Iqvz1/eVtx8STUrpQoZ5qrfZLsCpaE+eQjLzC40r8FM 8X4QK2b10fRCR0UkpeVr/Ium7c7szr/IGICJczir0DOD2UtPYeaPRDMd6fpiDXaE+A60 q+zB+VnfEhPxoZ+Y39WxOXLuRvCwfvqjcUQlG7wqjnuCdH4AtxguuOYuNmAJAMfg9idq YLt2sdr9YHTP/Whh6FS5OqR8fdD2JapjhpxGqKVlM636Zmw/OfDj9u4mPrvr6GLpwcQ/ H50Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZNrlTmh7hRCK4ChDppa6LEEimFwQDqMaFB6OVXrQOZs=; b=ndNhwG9XusFc6FLUkbrP24Scu2rMbOWtxIrhoE3dKxwyadmu1vCms3mqzI3wvbQevw 55+pWO+4G/Bx+yf1wph+vRkGm4lMQCGE207R+Umy1JqvofC1S8i8UyeV8DWU9UPgKrnP xLAJ+4fU4yiP5uyNuKJsZUCZkTkgqyITCbhtfe2/VLmG1HGmJpr/BKtc0Cv/pfkBgaL3 /CKCKcamzRQY8uiRjo/u/FOvbpNC03sGgAhXMK2BFZanbZSIcTXjaWL6ktY52xv000Tu SCe/t2JLf3U3ZVCPrQdChWDbiUbVbLcA3aCK2C+3EdfSlcWs4w1vA7+j5R/TeMo4pA9U gd0w== X-Gm-Message-State: AHQUAuZdCC+a8qoXVczhDUj0NV5hBhUB+cNcW8HkolSo6fCUZHnEuJoW f7G4OSBFixmAXJzYTsZaYdgZakgS3kn88A== X-Google-Smtp-Source: AHgI3IZE2jBC+mF8T9m/K9CFK/3J9t+pWtUE/GPdTZKJ1FhEgRg/mEIQtdUt0CKDW02hkrpa4g2fbw== X-Received: by 2002:a5d:47d1:: with SMTP id l17mr4364108wrs.319.1549386342430; Tue, 05 Feb 2019 09:05:42 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 5 Feb 2019 17:05:08 +0000 Message-Id: <20190205170510.21984-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190205170510.21984-1-peter.maydell@linaro.org> References: <20190205170510.21984-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42c Subject: [Qemu-devel] [PULL 20/22] hw/arm/boot: Clarify why arm_setup_firmware_boot() doesn't set env->boot_info X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The code path for booting firmware doesn't set env->boot_info. At first sight this looks odd, so add a comment saying why we don't. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Igor Mammedov Message-id: 20190131112240.8395-5-peter.maydell@linaro.org --- hw/arm/boot.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 2d4f710395f..328cc6bd245 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -1182,7 +1182,8 @@ static void arm_setup_firmware_boot(ARMCPU *cpu, stru= ct arm_boot_info *info) =20 /* * We will start from address 0 (typically a boot ROM image) in the - * same way as hardware. + * same way as hardware. Leave env->boot_info NULL, so that + * do_cpu_reset() knows it does not need to alter the PC on reset. */ } =20 --=20 2.20.1 From nobody Sun May 5 05:05:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549387762974744.2318047520813; Tue, 5 Feb 2019 09:29:22 -0800 (PST) Received: from localhost ([127.0.0.1]:35517 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4X6-0004O2-Un for importer@patchew.org; Tue, 05 Feb 2019 12:29:16 -0500 Received: from eggs.gnu.org ([209.51.188.92]:35918) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4AS-0001uV-M9 for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gr4AR-0000Yx-I2 for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:52 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:35761) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gr4AR-0000V1-7T for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:51 -0500 Received: by mail-wr1-x443.google.com with SMTP id z18so3712104wrh.2 for ; Tue, 05 Feb 2019 09:05:44 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm5583164wmf.5.2019.02.05.09.05.42 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Feb 2019 09:05:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=OfKY4K9BkMjjwiqunb7cujWZfwYnebUV8ouMZGLQAag=; b=n3Ngm2jtNtXEJPJ/m3Bmrj/n5p+Bzj1S99PEI4PCR4ejg8eIBlDPJcDzRAlzOsygJr T6eUh+yAKw1VoaQCQmBnFL9BxEHI0wK1Ja6I7vL3LE7o2E4mIuITlDMmMST95z2sxOas BbO6PBI0ipjzL1Y1yH/v+0sLjtJ9J7ViDl8/qjGHTlR0bu6MPDcTrJClKxoIESTXEQs+ mHaHdd5wQcwF7ZKcerdfwfvDoC05EF7O9VOnXTZ1jzGO6HkqaEfP3+hDyg9KNFeNXT1m ktFdPlgcoa3+Jin+VOjW/U/3oCR4UhoQSxYK6gaACwV7U5o+ZcnNPBArzAZ3+p+Evs9R rUlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OfKY4K9BkMjjwiqunb7cujWZfwYnebUV8ouMZGLQAag=; b=bDTz7H6JvqUmReWm2KTGwW1dAnEuJz0exMkACKkKXaC3z6qkxTm4rBcsIAXZgBIRRx Uobv0+HOkFCXf93yuPsMzlQA9a11v/5T3FwpzNsr1sv3ub2sds25Pzss9F1a8NuLiZTi 7PlYQgB1F/RpypkvR/kIj7DkKJXOsakdEEQQQ7lyv5ip57kNTZUKi/cleLjxGtNOObbo qQUTOrq8e/Tv8uPeRlU5Nzwfvogqi29vO084xmI7Fr75WtOaUIVxAx5K3Ogo71gFQkEj RMhOQQWqdhDUMDDLBBDZKIG8M6iNnyqa5cx9KmGZ8TQdjVuE8VW7M4ngsfG1tzKf+k+5 YTWA== X-Gm-Message-State: AHQUAuZSO6X6ZrC+s/BIH5ZSAaYGHBGyLbHrDkC40RxuPsanhS8tymgx rRCcvZ3nOU0go2RjZIswZJStLuuSgKIoyw== X-Google-Smtp-Source: AHgI3IbQiV0Cawwvyj/tGTRxzZ1i8vYAhKBmI/LfVJGzVVhvyDXapW5WCfpUAMschZb34fQmzQVdew== X-Received: by 2002:a5d:49cd:: with SMTP id t13mr4539111wrs.144.1549386343795; Tue, 05 Feb 2019 09:05:43 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 5 Feb 2019 17:05:09 +0000 Message-Id: <20190205170510.21984-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190205170510.21984-1-peter.maydell@linaro.org> References: <20190205170510.21984-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PULL 21/22] hw/arm/boot: Support DTB autoload for firmware-only boots X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The arm_boot_info struct has a skip_dtb_autoload flag: if this is set to true by the board code then arm_load_kernel() will not load the DTB itself, but will leave this for the board code to do itself later. However, the check for this is done in a code path which is only executed for the case where we load a kernel image file. If we're taking the "boot via firmware" code path then the flag isn't honoured and the DTB is never loaded. We didn't notice this because the only real user of "boot via firmware" that cares about the DTB is the virt board (for UEFI boot), and that always wants skip_dtb_autoload anyway. But the SBSA reference board model we're planning to add will want the flag to behave correctly. Now we've refactored the arm_load_kernel() function, the fix is simple: drop the early 'return' so we fall into the same "load the DTB" code the boot-direct-kernel path uses. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Igor Mammedov Message-id: 20190131112240.8395-6-peter.maydell@linaro.org --- hw/arm/boot.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 328cc6bd245..496c8c18b08 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -1215,7 +1215,6 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_inf= o *info) /* Load the kernel. */ if (!info->kernel_filename || info->firmware_loaded) { arm_setup_firmware_boot(cpu, info); - return; } else { arm_setup_direct_kernel_boot(cpu, info); } --=20 2.20.1 From nobody Sun May 5 05:05:30 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549388295661933.9546933422835; Tue, 5 Feb 2019 09:38:15 -0800 (PST) Received: from localhost ([127.0.0.1]:35685 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4fc-00032p-Gt for importer@patchew.org; Tue, 05 Feb 2019 12:38:04 -0500 Received: from eggs.gnu.org ([209.51.188.92]:36055) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr4AV-0001v4-2k for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:06:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gr4AS-0000ao-Hn for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:54 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:39089) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gr4AS-0000Vo-4C for qemu-devel@nongnu.org; Tue, 05 Feb 2019 12:05:52 -0500 Received: by mail-wr1-x430.google.com with SMTP id t27so4457572wra.6 for ; Tue, 05 Feb 2019 09:05:46 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w13sm5583164wmf.5.2019.02.05.09.05.43 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 05 Feb 2019 09:05:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=8z6OAizl3lsysfolwsgKCWRutlc3AKlSrSRaqOerGy8=; b=G++xZfITQFSMd587PD5QssqM9hUYJ09NiEUu7jE2gi6p9tFCVr5PUh9V+KrH8dsXdK ZE1PL2/7BoRb9j4u3qitaeVodqBnRvZbFIUR/oFblwdX447KtXF6wdLy/BSF3141K/MJ 5RCnHWYMOQqyPpLbYJGHFfJhSsUZGSZxOIPdSixlaYs+RKwJvrTW83mA8lVVtMAiap1g NrIlX8RggXoJWpoOptqBseJw6eI2QhlKeZWRvhZtqmlFiOp/nDTqrtxX4MdNjOeph8jS 3rh46KW1Ie2SwMuT7Um6yx4JVsrEADvacQQgzBV3VdDVrU2CHbXptvZoYtGobNHcdmx6 awJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8z6OAizl3lsysfolwsgKCWRutlc3AKlSrSRaqOerGy8=; b=eXqPprQF3Uav5alVXs25flSy5FVnR4oehjsCOWZuZebZub8HCIl2D9MwPm1hNNJRDV Q7IjTmPlIWJIjSiX9jrsG6M+EsZgrcmH4omjrXj+UJOD1hNx5V8kOSagf4MHaCKtWEye RRR1Yzr5lRVArQY54DUXwGWpvife11JEAP1V9GutoYCOz1FBbxoeVKM0UJYCHPyn0mQD S7fcvXmGv3umlyBCK0sASvUe06d8pLfqEE7hT9hl2XOUMNXm+dMGrbFDvz9XyzTj53iR YO+28GizWFLGQrG9yayYjDFiZj3/lzBf4E3teTNagMbG6AoVRg3dlgQ8SGrJ/Ge2RAPo MhQw== X-Gm-Message-State: AHQUAubf8Li7S3RIIEDpjPYdeOUsZlk/82/vGg2dMcDLQ+Exh+ayv4nH /pAG904bdYiDWfSVqFz6uQPGaAkJqzxKHg== X-Google-Smtp-Source: AHgI3IYn3uQl/SLcB+ABAxUlLlBRsY/OuaRll9e14XXAs9VToTCYcgltsgd+53Nurp5RGmNtmoRNTg== X-Received: by 2002:adf:c589:: with SMTP id m9mr4539576wrg.145.1549386344950; Tue, 05 Feb 2019 09:05:44 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 5 Feb 2019 17:05:10 +0000 Message-Id: <20190205170510.21984-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190205170510.21984-1-peter.maydell@linaro.org> References: <20190205170510.21984-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::430 Subject: [Qemu-devel] [PULL 22/22] target/arm: Make FPSCR/FPCR trapped-exception bits RAZ/WI X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The {IOE, DZE, OFE, UFE, IXE, IDE} bits in the FPSCR/FPCR are for enabling trapped IEEE floating point exceptions (where IEEE exception conditions cause a CPU exception rather than updating the FPSR status bits). QEMU doesn't implement this (and nor does the hardware we're modelling), but for implementations which don't implement trapped exception handling these control bits are supposed to be RAZ/WI. This allows guest code to test for whether the feature is present by trying to write to the bit and checking whether it sticks. QEMU is incorrectly making these bits read as written. Make them RAZ/WI as the architecture requires. In particular this was causing problems for the NetBSD automatic test suite. Reported-by: Martin Husemann Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20190131130700.28392-1-peter.maydell@linaro.org --- target/arm/cpu.h | 6 ++++++ target/arm/helper.c | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ec14d3e228d..47238e42458 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1418,6 +1418,12 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val); #define FPSR_MASK 0xf800009f #define FPCR_MASK 0x07ff9f00 =20 +#define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable= */ +#define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ +#define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ +#define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ +#define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ +#define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ #define FPCR_DN (1 << 25) /* Default NaN enable bit */ diff --git a/target/arm/helper.c b/target/arm/helper.c index aaf5b0cd7ab..520ceea7a41 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12637,6 +12637,12 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint3= 2_t val) val &=3D ~FPCR_FZ16; } =20 + /* + * We don't implement trapped exception handling, so the + * trap enable bits are all RAZ/WI (not RES0!) + */ + val &=3D ~(FPCR_IDE | FPCR_IXE | FPCR_UFE | FPCR_OFE | FPCR_DZE | FPCR= _IOE); + changed =3D env->vfp.xregs[ARM_VFP_FPSCR]; env->vfp.xregs[ARM_VFP_FPSCR] =3D (val & 0xffc8ffff); env->vfp.vec_len =3D (val >> 16) & 7; --=20 2.20.1