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[81.133.38.158]) by smtp.gmail.com with ESMTPSA id l20sm30371534wrb.93.2019.02.04.05.21.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 04 Feb 2019 05:21:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jys3zZetk/4aZpt2Z4tdApTnslMweo+0rFVX+0Gfq4E=; b=D7Y91JhOF+bZHYWoZ8FYh5hrxaozGoxFTEyqa7YzTWNzkikbhPIHz/GLaVgeiN80Qr xQvQUrESKxxf02+EsMvx4FrrUMbosBQHZRmOZJ869kil8lP8LbODoegaEKlEXVny655q HUQ5vePGuQVJk0QIleTYoGmc04TDEPFThnHw8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jys3zZetk/4aZpt2Z4tdApTnslMweo+0rFVX+0Gfq4E=; b=A7wzjvbLMaJbOrQMedLrANPDnAH/dhOHZfaNhIUro30tbcYjgcm2FjJ8qcssMuFXtL G6AG23q0Q4LKSiCXT74Cuto941EG9UeiLWJ9pQUPZrjKYN+xxLvETX+ZScOwSAAnQs3w y3n9JgaM6ko+gF4iVzUnKlyzK+f3pq+Nf1iUTfw3emiCaimOQGvNYhzpYMPuJLaXfaPY nSM/ZIJbnBcMncG/xDey7Et7DRAiSB3qh5Wr9JHyZ/dBQZlEV9mUhCu5yzDy4l5nCCt4 XTI+YTZk4hpDkyf9w7EZfZByVxdJt1XMr+Nm5S1oA3kHk4CLxUrWsM7yRZOgzI37cOLR DIoQ== X-Gm-Message-State: AJcUuke1cSyS+hc0K/QCaokEj2+v5suKnrpm5dALtvJUgCXw9qCyG3vD X5Kklat1/2CLMkp+12BVMPMBnXhJvACByg== X-Google-Smtp-Source: ALg8bN76+4AWPAm5x3xvaL0v/28xaHEB1mnUOYDXzlPtvCAf6ckhGQqkCjdVebrCApUGoKhTvMd0Zg== X-Received: by 2002:adf:900f:: with SMTP id h15mr48985857wrh.18.1549286494237; Mon, 04 Feb 2019 05:21:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 4 Feb 2019 13:21:23 +0000 Message-Id: <20190204132126.3255-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190204132126.3255-1-richard.henderson@linaro.org> References: <20190204132126.3255-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH v2 1/4] target/arm: Add TBFLAG_A64_TBID, split out gen_top_byte_ignore X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Split out gen_top_byte_ignore in preparation of handling these data accesses; the new tbflags field is not yet honored. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Re-add some commentary wrt TBI bits. --- target/arm/cpu.h | 1 + target/arm/translate.h | 3 +- target/arm/helper.c | 1 + target/arm/translate-a64.c | 72 +++++++++++++++++++------------------- 4 files changed, 40 insertions(+), 37 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 366ab97db3..029f6cd60c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3058,6 +3058,7 @@ FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) FIELD(TBFLAG_A64, BT, 9, 1) FIELD(TBFLAG_A64, BTYPE, 10, 2) +FIELD(TBFLAG_A64, TBID, 12, 2) =20 static inline bool bswap_code(bool sctlr_b) { diff --git a/target/arm/translate.h b/target/arm/translate.h index f73939d7b4..17748ddfb9 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -26,7 +26,8 @@ typedef struct DisasContext { int user; #endif ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */ - uint8_t tbii; /* TBI1|TBI0 for EL0/1 or TBI for EL2/3 */ + uint8_t tbii; /* TBI1|TBI0 for insns */ + uint8_t tbid; /* TBI1|TBI0 for data */ bool ns; /* Use non-secure CPREG bank on access */ int fp_excp_el; /* FP exception EL or 0 if enabled */ int sve_excp_el; /* SVE exception EL or 0 if enabled */ diff --git a/target/arm/helper.c b/target/arm/helper.c index be0ec7de2a..25d8ec38f8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13767,6 +13767,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, } =20 flags =3D FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); + flags =3D FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); } #endif =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 37077138e3..0b4a09ca1c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -284,10 +284,10 @@ void gen_a64_set_pc_im(uint64_t val) tcg_gen_movi_i64(cpu_pc, val); } =20 -/* Load the PC from a generic TCG variable. +/* + * Handle Top Byte Ignore (TBI) bits. * - * If address tagging is enabled via the TCR TBI bits, then loading - * an address into the PC will clear out any tag in it: + * If address tagging is enabled via the TCR TBI bits: * + for EL2 and EL3 there is only one TBI bit, and if it is set * then the address is zero-extended, clearing bits [63:56] * + for EL0 and EL1, TBI0 controls addresses with bit 55 =3D=3D 0 @@ -295,45 +295,44 @@ void gen_a64_set_pc_im(uint64_t val) * If the appropriate TBI bit is set for the address then * the address is sign-extended from bit 55 into bits [63:56] * - * We can avoid doing this for relative-branches, because the - * PC + offset can never overflow into the tag bits (assuming - * that virtual addresses are less than 56 bits wide, as they - * are currently), but we must handle it for branch-to-register. + * Here We have concatenated TBI{1,0} into tbi. */ -static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) +static void gen_top_byte_ignore(DisasContext *s, TCGv_i64 dst, + TCGv_i64 src, int tbi) { - /* Note that TBII is TBI1:TBI0. */ - int tbi =3D s->tbii; - - if (s->current_el <=3D 1) { - if (tbi !=3D 0) { - /* Sign-extend from bit 55. */ - tcg_gen_sextract_i64(cpu_pc, src, 0, 56); - - if (tbi !=3D 3) { - TCGv_i64 tcg_zero =3D tcg_const_i64(0); - - /* - * The two TBI bits differ. - * If tbi0, then !tbi1: only use the extension if positive. - * if !tbi0, then tbi1: only use the extension if negative. - */ - tcg_gen_movcond_i64(tbi =3D=3D 1 ? TCG_COND_GE : TCG_COND_= LT, - cpu_pc, cpu_pc, tcg_zero, cpu_pc, src); - tcg_temp_free_i64(tcg_zero); - } - return; - } + if (tbi =3D=3D 0) { + /* Load unmodified address */ + tcg_gen_mov_i64(dst, src); + } else if (s->current_el >=3D 2) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + /* Force tag byte to all zero */ + tcg_gen_extract_i64(dst, src, 0, 56); } else { - if (tbi !=3D 0) { - /* Force tag byte to all zero */ - tcg_gen_extract_i64(cpu_pc, src, 0, 56); - return; + /* Sign-extend from bit 55. */ + tcg_gen_sextract_i64(dst, src, 0, 56); + + if (tbi !=3D 3) { + TCGv_i64 tcg_zero =3D tcg_const_i64(0); + + /* + * The two TBI bits differ. + * If tbi0, then !tbi1: only use the extension if positive. + * if !tbi0, then tbi1: only use the extension if negative. + */ + tcg_gen_movcond_i64(tbi =3D=3D 1 ? TCG_COND_GE : TCG_COND_LT, + dst, dst, tcg_zero, dst, src); + tcg_temp_free_i64(tcg_zero); } } +} =20 - /* Load unmodified address */ - tcg_gen_mov_i64(cpu_pc, src); +static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) +{ + /* + * If address tagging is enabled for instructions via the TCR TBI bits, + * then loading an address into the PC will clear out any tag. + */ + gen_top_byte_ignore(s, cpu_pc, src, s->tbii); } =20 typedef struct DisasCompare64 { @@ -14018,6 +14017,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, core_mmu_idx =3D FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX); dc->mmu_idx =3D core_to_arm_mmu_idx(env, core_mmu_idx); dc->tbii =3D FIELD_EX32(tb_flags, TBFLAG_A64, TBII); + dc->tbid =3D FIELD_EX32(tb_flags, TBFLAG_A64, TBID); dc->current_el =3D arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user =3D (dc->current_el =3D=3D 0); --=20 2.17.2