From nobody Thu Sep 19 01:52:26 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549271290510347.4847457068897; Mon, 4 Feb 2019 01:08:10 -0800 (PST) Received: from localhost ([127.0.0.1]:38979 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gqaEb-00054x-CM for importer@patchew.org; Mon, 04 Feb 2019 04:08:09 -0500 Received: from eggs.gnu.org ([209.51.188.92]:38400) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gqa8j-0000cT-8J for qemu-devel@nongnu.org; Mon, 04 Feb 2019 04:02:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gqa8h-0007lb-MJ for qemu-devel@nongnu.org; Mon, 04 Feb 2019 04:02:05 -0500 Received: from ozlabs.org ([2401:3900:2:1::2]:36557) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gqa8g-0007eu-VT; Mon, 04 Feb 2019 04:02:03 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 43tMC855p8z9sPJ; Mon, 4 Feb 2019 20:01:37 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1549270900; bh=F3ktTi/RAxBI5x0eKywn4I6zrQCxToo5Z47qVLK5U9I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EvT/dFC4WUQ2ujxyW31rZ+KH4riu7L81cT2J57g4aKna0zIa0/uEV+SkqYCDD+vuX mbjesgkEqaGpLkJx//ivffCaFtApaxY0Wu8RgqlC1lQ+a23GIoemoTV8deeS8qkk1p RNL1HuLrsQQg71tF20XANd5F5CWWjayo7WKQ0eiY= From: David Gibson To: peter.maydell@linaro.org Date: Mon, 4 Feb 2019 20:01:02 +1100 Message-Id: <20190204090124.26191-16-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190204090124.26191-1-david@gibson.dropbear.id.au> References: <20190204090124.26191-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 15/37] xive: add a get_tctx() method to the XiveRouter X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, qemu-devel@nongnu.org, groug@kaod.org, spopovyc@redhat.com, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: C=C3=A9dric Le Goater It provides a mean to retrieve the XiveTCTX of a CPU. This will become necessary with future changes which move the interrupt presenter object pointers under the PowerPCCPU machine_data. The PowerNV machine has an extra requirement on TIMA accesses that this new method addresses. The machine can perform indirect loads and stores on the TIMA on behalf of another CPU. The PIR being defined in the controller registers, we need a way to peek in the controller model to find the PIR value. The XiveTCTX is moved above the XiveRouter definition to avoid forward typedef declarations. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Greg Kurz Signed-off-by: David Gibson --- hw/intc/spapr_xive.c | 8 ++++++ hw/intc/xive.c | 16 +++++++----- include/hw/ppc/xive.h | 57 ++++++++++++++++++++++--------------------- 3 files changed, 47 insertions(+), 34 deletions(-) diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index d391177ab8..136d872f16 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -390,6 +390,13 @@ static int spapr_xive_write_nvt(XiveRouter *xrtr, uint= 8_t nvt_blk, g_assert_not_reached(); } =20 +static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) +{ + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + + return cpu->tctx; +} + static const VMStateDescription vmstate_spapr_xive_end =3D { .name =3D TYPE_SPAPR_XIVE "/end", .version_id =3D 1, @@ -454,6 +461,7 @@ static void spapr_xive_class_init(ObjectClass *klass, v= oid *data) xrc->write_end =3D spapr_xive_write_end; xrc->get_nvt =3D spapr_xive_get_nvt; xrc->write_nvt =3D spapr_xive_write_nvt; + xrc->get_tctx =3D spapr_xive_get_tctx; } =20 static const TypeInfo spapr_xive_info =3D { diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 7f567a57d2..2e9b8efd43 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -320,8 +320,7 @@ static const XiveTmOp *xive_tm_find_op(hwaddr offset, u= nsigned size, bool write) static void xive_tm_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { - PowerPCCPU *cpu =3D POWERPC_CPU(current_cpu); - XiveTCTX *tctx =3D cpu->tctx; + XiveTCTX *tctx =3D xive_router_get_tctx(XIVE_ROUTER(opaque), current_c= pu); const XiveTmOp *xto; =20 /* @@ -359,8 +358,7 @@ static void xive_tm_write(void *opaque, hwaddr offset, =20 static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size) { - PowerPCCPU *cpu =3D POWERPC_CPU(current_cpu); - XiveTCTX *tctx =3D cpu->tctx; + XiveTCTX *tctx =3D xive_router_get_tctx(XIVE_ROUTER(opaque), current_c= pu); const XiveTmOp *xto; =20 /* @@ -1107,6 +1105,13 @@ int xive_router_write_nvt(XiveRouter *xrtr, uint8_t = nvt_blk, uint32_t nvt_idx, return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number); } =20 +XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs) +{ + XiveRouterClass *xrc =3D XIVE_ROUTER_GET_CLASS(xrtr); + + return xrc->get_tctx(xrtr, cs); +} + /* * The thread context register words are in big-endian format. */ @@ -1182,8 +1187,7 @@ static bool xive_presenter_match(XiveRouter *xrtr, ui= nt8_t format, */ =20 CPU_FOREACH(cs) { - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - XiveTCTX *tctx =3D cpu->tctx; + XiveTCTX *tctx =3D xive_router_get_tctx(xrtr, cs); int ring; =20 /* diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 5d31c801ee..ec3bb2aae4 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -294,6 +294,33 @@ static inline void xive_source_irq_set(XiveSource *xsr= c, uint32_t srcno, =20 void xive_source_set_irq(void *opaque, int srcno, int val); =20 +/* + * XIVE Thread interrupt Management (TM) context + */ + +#define TYPE_XIVE_TCTX "xive-tctx" +#define XIVE_TCTX(obj) OBJECT_CHECK(XiveTCTX, (obj), TYPE_XIVE_TCTX) + +/* + * XIVE Thread interrupt Management register rings : + * + * QW-0 User event-based exception state + * QW-1 O/S OS context for priority management, interrupt acks + * QW-2 Pool hypervisor pool context for virtual processors dispa= tched + * QW-3 Physical physical thread context and security context + */ +#define XIVE_TM_RING_COUNT 4 +#define XIVE_TM_RING_SIZE 0x10 + +typedef struct XiveTCTX { + DeviceState parent_obj; + + CPUState *cs; + qemu_irq output; + + uint8_t regs[XIVE_TM_RING_COUNT * XIVE_TM_RING_SIZE]; +} XiveTCTX; + /* * XIVE Router */ @@ -324,6 +351,7 @@ typedef struct XiveRouterClass { XiveNVT *nvt); int (*write_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt, uint8_t word_number); + XiveTCTX *(*get_tctx)(XiveRouter *xrtr, CPUState *cs); } XiveRouterClass; =20 void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon); @@ -338,7 +366,7 @@ int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_b= lk, uint32_t nvt_idx, XiveNVT *nvt); int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_= idx, XiveNVT *nvt, uint8_t word_number); - +XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs); =20 /* * XIVE END ESBs @@ -371,33 +399,6 @@ typedef struct XiveENDSource { void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon); void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *= mon); =20 -/* - * XIVE Thread interrupt Management (TM) context - */ - -#define TYPE_XIVE_TCTX "xive-tctx" -#define XIVE_TCTX(obj) OBJECT_CHECK(XiveTCTX, (obj), TYPE_XIVE_TCTX) - -/* - * XIVE Thread interrupt Management register rings : - * - * QW-0 User event-based exception state - * QW-1 O/S OS context for priority management, interrupt acks - * QW-2 Pool hypervisor pool context for virtual processors dispa= tched - * QW-3 Physical physical thread context and security context - */ -#define XIVE_TM_RING_COUNT 4 -#define XIVE_TM_RING_SIZE 0x10 - -typedef struct XiveTCTX { - DeviceState parent_obj; - - CPUState *cs; - qemu_irq output; - - uint8_t regs[XIVE_TM_RING_COUNT * XIVE_TM_RING_SIZE]; -} XiveTCTX; - /* * XIVE Thread Interrupt Management Aera (TIMA) * --=20 2.20.1