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[81.133.38.158]) by smtp.gmail.com with ESMTPSA id r9sm25149962wmb.27.2019.02.03.21.27.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 03 Feb 2019 21:27:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bp56cEa4XjKsG9OQbdTUT00/i8slI/Xfj491IKRrqgU=; b=E9CJMcRZMeS/MW4XeShcBwPT86MFToFyCTxErl7xipiKdb0O1z8CbzJfZkKf/DoDTo Dj9N+NvRIYdLc7sUwpU8cFLf73nC+y6SWYYXHJ5rs897idX8ksEfzXz2rxpHjHww9/oK mfyjvZMZyn9jrog4Ci+9w9lOiqpS+AB++aURs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bp56cEa4XjKsG9OQbdTUT00/i8slI/Xfj491IKRrqgU=; b=kmpSv2bde3F/Ku407DxbDaWwABab1e3/dsCHUI9KNSg6so/TGRAQCB86cDbluVPUi6 4u6PO4gf9uK3p4MmpbB36BpixjlPIp1R9600V+8LX5hEeS8XlUQ0L6tE1Cl94GBeKIC6 GHbfuY9lnjvR/0VRrWKGY/5/Hp1lbMuNDB4JTGrS5FyoZlJioUH0ThIplQR1F8/KyHom +279mZRvBr4Q9eNi7ernfWv97vz7pxHLfIfnmhQGL9lQ4J7jKcV5smZz8yrPXxEO10+O 8KiGI/NRXBfsLdbEXgZ1y7VofW/OxuivPBip/IQ3Jf1+ZdeOrhfup7gNJFrn6z5kbD8s ch+w== X-Gm-Message-State: AHQUAubp0mkGUEmgaNYFtnZrN4C94vVpIvfHPj+aD+IWXT1/aD2cspSk WX8cRgETEm60Syp68YtrqLpZkurmaUJ+0g== X-Google-Smtp-Source: AHgI3IYKSmVE4Ye+Ul0pUd4etDGpyBecHgArH4+mQaAQHRTQQSM/FxdVhp3SxrS0J2PS/RA6g1OHgA== X-Received: by 2002:a7b:c854:: with SMTP id c20mr5529178wml.153.1549258038346; Sun, 03 Feb 2019 21:27:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 4 Feb 2019 05:27:10 +0000 Message-Id: <20190204052712.30833-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190204052712.30833-1-richard.henderson@linaro.org> References: <20190204052712.30833-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH 1/3] target/arm: Force result size into dp after operation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Rather than a complex set of cases testing for writeback, adjust DP after performing the operation. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 66cf28c8cb..eb25895876 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3970,6 +3970,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) tcg_gen_or_i32(tmp, tmp, tmp2); tcg_temp_free_i32(tmp2); gen_vfp_msr(tmp); + dp =3D 0; /* always a single precision result */ break; } case 7: /* vcvtt.f16.f32, vcvtt.f16.f64 */ @@ -3993,20 +3994,25 @@ static int disas_vfp_insn(DisasContext *s, uint32_t= insn) tcg_gen_or_i32(tmp, tmp, tmp2); tcg_temp_free_i32(tmp2); gen_vfp_msr(tmp); + dp =3D 0; /* always a single precision result */ break; } case 8: /* cmp */ gen_vfp_cmp(dp); + dp =3D -1; /* no write back */ break; case 9: /* cmpe */ gen_vfp_cmpe(dp); + dp =3D -1; /* no write back */ break; case 10: /* cmpz */ gen_vfp_cmp(dp); + dp =3D -1; /* no write back */ break; case 11: /* cmpez */ gen_vfp_F1_ld0(dp); gen_vfp_cmpe(dp); + dp =3D -1; /* no write back */ break; case 12: /* vrintr */ { @@ -4047,10 +4053,12 @@ static int disas_vfp_insn(DisasContext *s, uint32_t= insn) break; } case 15: /* single<->double conversion */ - if (dp) + if (dp) { gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_en= v); - else + } else { gen_helper_vfp_fcvtds(cpu_F0d, cpu_F0s, cpu_en= v); + } + dp =3D !dp; /* result size is opposite */ break; case 16: /* fuito */ gen_vfp_uito(dp, 0); @@ -4084,15 +4092,19 @@ static int disas_vfp_insn(DisasContext *s, uint32_t= insn) break; case 24: /* ftoui */ gen_vfp_toui(dp, 0); + dp =3D 0; /* always an integer result */ break; case 25: /* ftouiz */ gen_vfp_touiz(dp, 0); + dp =3D 0; /* always an integer result */ break; case 26: /* ftosi */ gen_vfp_tosi(dp, 0); + dp =3D 0; /* always an integer result */ break; case 27: /* ftosiz */ gen_vfp_tosiz(dp, 0); + dp =3D 0; /* always an integer result */ break; case 28: /* ftosh */ if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { @@ -4126,20 +4138,8 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) return 1; } =20 - /* Write back the result. */ - if (op =3D=3D 15 && (rn >=3D 8 && rn <=3D 11)) { - /* Comparison, do nothing. */ - } else if (op =3D=3D 15 && dp && ((rn & 0x1c) =3D=3D 0x18 = || - (rn & 0x1e) =3D=3D 0x6)) { - /* VCVT double to int: always integer result. - * VCVT double to half precision is always a single - * precision result. - */ - gen_mov_vreg_F0(0, rd); - } else if (op =3D=3D 15 && rn =3D=3D 15) { - /* conversion */ - gen_mov_vreg_F0(!dp, rd); - } else { + /* Write back the result, if any. */ + if (dp >=3D 0) { gen_mov_vreg_F0(dp, rd); } =20 --=20 2.17.2 From nobody Fri May 3 21:38:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549258903191642.850207877661; Sun, 3 Feb 2019 21:41:43 -0800 (PST) Received: from localhost ([127.0.0.1]:36314 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gqX0j-00045e-5k for importer@patchew.org; Mon, 04 Feb 2019 00:41:37 -0500 Received: from eggs.gnu.org ([209.51.188.92]:43317) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gqWwc-00017m-2v for qemu-devel@nongnu.org; Mon, 04 Feb 2019 00:37:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gqWn2-0002gp-4O for qemu-devel@nongnu.org; Mon, 04 Feb 2019 00:27:29 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:55555) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gqWmy-0002a6-1Y for qemu-devel@nongnu.org; Mon, 04 Feb 2019 00:27:26 -0500 Received: by mail-wm1-x342.google.com with SMTP id y139so11686098wmc.5 for ; Sun, 03 Feb 2019 21:27:20 -0800 (PST) Received: from cloudburst.twiddle.net (host81-133-38-158.in-addr.btopenworld.com. [81.133.38.158]) by smtp.gmail.com with ESMTPSA id r9sm25149962wmb.27.2019.02.03.21.27.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 03 Feb 2019 21:27:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8I5T5uoh7QBC/Ztx5KMfr0VjyqXfDsNWAzBv0p6cEpg=; b=G5gqzylejOk2bTmXCBzbZwS6RS7xuzniPzYg1CAi/+GNyzt1mmsJaDCcZydPQnZKKp hKD7IOqd9KXmHrUwEyK+z0EhvltKyp2EP0eq3eemlbqm1exAqEZWBjA6CQp6Z+fwWZVR ePoEkxUOAgdEtBDK8DenNPvfLz1vhDvSFpcxY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8I5T5uoh7QBC/Ztx5KMfr0VjyqXfDsNWAzBv0p6cEpg=; b=eqibdOa3WOIR0Se6128u/23v3M7XVbxHxfqxwnuX5F2jQmKZ4JIDMRZKndKtPcDGRf c4ZrBnYTUfDAW5dD856ZPu5cak4Fj8WG4FiZWLxbYY0PPkoppqIlH2rh8fa6cjOFthzn GwXF5MQcL6NJ71obAkdZx6DPJVsGNr0MthLy2DCESn9hXaP39yJKhj5Pb6CpHV6BFM2a 3kqd/2BagjcdXUg28xhGzlg1yvfiWCD5sSgUW/udl48sXMnBJ8cKIXupLq9F+tKvpYmf Q5Wn2PAxB8x/tLaBbD721bVG2+NZfwUI0V0ikprBjh6vWzt/m04AV+VICnE9ExJ1zSUV ozNQ== X-Gm-Message-State: AHQUAuZVelukrzST6fTS41w4xOLtxHb2pBqPB/8cy+ZB9Kdcduu9O9Ds ALqz1a+GH0JTMVyhU8QovgDxpKBwh5ux2A== X-Google-Smtp-Source: AHgI3IYhkswQ4++wvNczG5CcLRkQBmIGsZZvdMNJzm5Q+z8ANk0Sw2mNqK3CddcZMi2tvpLDwnvT0w== X-Received: by 2002:a1c:414:: with SMTP id 20mr11851817wme.67.1549258039459; Sun, 03 Feb 2019 21:27:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 4 Feb 2019 05:27:11 +0000 Message-Id: <20190204052712.30833-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190204052712.30833-1-richard.henderson@linaro.org> References: <20190204052712.30833-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH 2/3] target/arm: Restructure disas_fp_int_conv X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For opcodes 0-5, move some if conditions into the structure of a switch statement. For opcodes 6 & 7, decode everything at once with a second switch. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 94 ++++++++++++++++++++------------------ 1 file changed, 49 insertions(+), 45 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a1997e3ae2..90298ac562 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -6473,68 +6473,72 @@ static void disas_fp_int_conv(DisasContext *s, uint= 32_t insn) int type =3D extract32(insn, 22, 2); bool sbit =3D extract32(insn, 29, 1); bool sf =3D extract32(insn, 31, 1); + bool itof =3D false; =20 if (sbit) { - unallocated_encoding(s); - return; + goto do_unallocated; } =20 - if (opcode > 5) { - /* FMOV */ - bool itof =3D opcode & 1; - - if (rmode >=3D 2) { - unallocated_encoding(s); - return; - } - - switch (sf << 3 | type << 1 | rmode) { - case 0x0: /* 32 bit */ - case 0xa: /* 64 bit */ - case 0xd: /* 64 bit to top half of quad */ - break; - case 0x6: /* 16-bit float, 32-bit int */ - case 0xe: /* 16-bit float, 64-bit int */ - if (dc_isar_feature(aa64_fp16, s)) { - break; - } - /* fallthru */ - default: - /* all other sf/type/rmode combinations are invalid */ - unallocated_encoding(s); - return; - } - - if (!fp_access_check(s)) { - return; - } - handle_fmov(s, rd, rn, type, itof); - } else { - /* actual FP conversions */ - bool itof =3D extract32(opcode, 1, 1); - - if (rmode !=3D 0 && opcode > 1) { - unallocated_encoding(s); - return; + switch (opcode) { + case 2: /* SCVTF */ + case 3: /* UCVTF */ + itof =3D true; + /* fallthru */ + case 4: /* FCVTAS */ + case 5: /* FCVTAU */ + if (rmode !=3D 0) { + goto do_unallocated; } + /* fallthru */ + case 0: /* FCVT[NPMZ]S */ + case 1: /* FCVT[NPMZ]U */ switch (type) { case 0: /* float32 */ case 1: /* float64 */ break; case 3: /* float16 */ - if (dc_isar_feature(aa64_fp16, s)) { - break; + if (!dc_isar_feature(aa64_fp16, s)) { + goto do_unallocated; } - /* fallthru */ + break; default: - unallocated_encoding(s); - return; + goto do_unallocated; } - if (!fp_access_check(s)) { return; } handle_fpfpcvt(s, rd, rn, opcode, itof, rmode, 64, sf, type); + break; + + default: + switch (sf << 6 | type << 5 | rmode << 3 | opcode) { + case 0b01100110: /* FMOV half <-> 32-bit int */ + case 0b01100111: + case 0b11100110: /* FMOV half <-> 64-bit int */ + case 0b11100111: + if (!dc_isar_feature(aa64_fp16, s)) { + goto do_unallocated; + } + /* fallthru */ + case 0b00000110: /* FMOV 32-bit */ + case 0b00000111: + case 0b10100110: /* FMOV 64-bit */ + case 0b10100111: + case 0b11001110: /* FMOV top half of 128-bit */ + case 0b11001111: + if (!fp_access_check(s)) { + return; + } + itof =3D opcode & 1; + handle_fmov(s, rd, rn, type, itof); + break; + + default: + do_unallocated: + unallocated_encoding(s); + return; + } + break; } } =20 --=20 2.17.2 From nobody Fri May 3 21:38:06 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549258775195228.09952388496288; Sun, 3 Feb 2019 21:39:35 -0800 (PST) Received: from localhost ([127.0.0.1]:36266 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gqWye-0002FP-OO for importer@patchew.org; Mon, 04 Feb 2019 00:39:28 -0500 Received: from eggs.gnu.org ([209.51.188.92]:43323) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gqWwb-00017n-MU for qemu-devel@nongnu.org; Mon, 04 Feb 2019 00:37:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gqWn2-0002gf-3o for qemu-devel@nongnu.org; Mon, 04 Feb 2019 00:27:29 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:40765) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gqWmy-0002cu-2t for qemu-devel@nongnu.org; Mon, 04 Feb 2019 00:27:26 -0500 Received: by mail-wr1-x444.google.com with SMTP id p4so12996237wrt.7 for ; Sun, 03 Feb 2019 21:27:22 -0800 (PST) Received: from cloudburst.twiddle.net (host81-133-38-158.in-addr.btopenworld.com. [81.133.38.158]) by smtp.gmail.com with ESMTPSA id r9sm25149962wmb.27.2019.02.03.21.27.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 03 Feb 2019 21:27:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CB6Rp8nT0ZAcE0b4lK30SxXYUkSjRO834/8KrwtWiF4=; b=DAw2LCQCoifHhO9zTkiBSemLTGskYMGqMuadU3fANSaXhz35Ub4ytDnfQ44FIxsXi1 JU0vEnN5TM/LzizvO6gQwmBxpZaFbrMXGR+TIM9yCnie2PVQBS6GyIURnlEAAU0YBi80 aVuZCQw/Cb9LXMxn289XO8SzaPVTJ82L6uojc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CB6Rp8nT0ZAcE0b4lK30SxXYUkSjRO834/8KrwtWiF4=; b=lejdrI1y0KfTXx3+JR0jtMJ/12JAOEGE/napQGsEsqa5WW2McpSvq+7pxSs0+caJnY 307bDjSBgEAvAFb7Xr9SukgoY/q31anpM31g0dYk8900Qw6yTz4Sgy4YOFKvwNuZfi97 DflRipTTSscwNhPNV2lwA1ynE71BvVxupXu7KjTAvx6kud0TtgkmcL1B6Je5aNnaEC1p oaxHHs4P1uKmfOge3YkCLXsnzOPnp9slEqvgP0KvI4UCo8HQ0i/VPsPCAWuOltT4PmJf zJg3niJchn0bLejk60KtUMmIYKMn6tFEk4lEWxHfRNFtf8rVXitDXqAizDU9Nw8sSqyg Cwow== X-Gm-Message-State: AJcUukf16ETSdSU8SRbezJWZU+2czMz2hh9ic1aKlulnfixewFUqD3tH tz9OydFDTDzDn6bhp3zj51/aXQQqj4ho5w== X-Google-Smtp-Source: ALg8bN6+7vtIsHVEdqUPL4pzFSN6wC+Y2tHMBCQk/MgOsRh/HZF+zEFTevkniVdxfw00yAy36qUdTQ== X-Received: by 2002:adf:ea11:: with SMTP id q17mr45651221wrm.328.1549258040802; Sun, 03 Feb 2019 21:27:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 4 Feb 2019 05:27:12 +0000 Message-Id: <20190204052712.30833-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190204052712.30833-1-richard.henderson@linaro.org> References: <20190204052712.30833-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH 3/3] target/arm: Implement ARMv8.3-JSConv X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/cpu.h | 10 +++++ target/arm/helper.h | 2 + target/arm/cpu.c | 1 + target/arm/cpu64.c | 2 + target/arm/op_helper.c | 91 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 26 +++++++++++ target/arm/translate.c | 15 +++++++ 7 files changed, 147 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a68bcc9fed..d2c2e2b0cf 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3209,6 +3209,11 @@ static inline bool isar_feature_aa32_vcma(const ARMI= SARegisters *id) return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) !=3D 0; } =20 +static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) !=3D 0; +} + static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) { return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) !=3D 0; @@ -3287,6 +3292,11 @@ static inline bool isar_feature_aa64_dp(const ARMISA= Registers *id) return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) !=3D 0; } =20 +static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) !=3D 0; +} + static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) !=3D 0; diff --git a/target/arm/helper.h b/target/arm/helper.h index 53a38188c6..6998f7e8d5 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -218,6 +218,8 @@ DEF_HELPER_FLAGS_2(rintd_exact, TCG_CALL_NO_RWG, f64, f= 64, ptr) DEF_HELPER_FLAGS_2(rints, TCG_CALL_NO_RWG, f32, f32, ptr) DEF_HELPER_FLAGS_2(rintd, TCG_CALL_NO_RWG, f64, f64, ptr) =20 +DEF_HELPER_FLAGS_2(fjcvtzs, TCG_CALL_NO_RWG, i64, f64, ptr) + /* neon_helper.c */ DEF_HELPER_FLAGS_3(neon_qadd_u8, TCG_CALL_NO_RWG, i32, env, i32, i32) DEF_HELPER_FLAGS_3(neon_qadd_s8, TCG_CALL_NO_RWG, i32, env, i32, i32) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 3874dc9875..2eb2ce6c8c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1995,6 +1995,7 @@ static void arm_max_initfn(Object *obj) cpu->isar.id_isar5 =3D t; =20 t =3D cpu->isar.id_isar6; + t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); cpu->isar.id_isar6 =3D t; =20 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 7107ec8d7e..43d8ff047c 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -311,6 +311,7 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_aa64isar0 =3D t; =20 t =3D cpu->isar.id_aa64isar1; + t =3D FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); t =3D FIELD_DP64(t, ID_AA64ISAR1, APA, 1); /* PAuth, architected o= nly */ t =3D FIELD_DP64(t, ID_AA64ISAR1, API, 0); @@ -340,6 +341,7 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_isar5 =3D u; =20 u =3D cpu->isar.id_isar6; + u =3D FIELD_DP32(u, ID_ISAR6, JSCVT, 1); u =3D FIELD_DP32(u, ID_ISAR6, DP, 1); cpu->isar.id_isar6 =3D u; =20 diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index c998eadfaa..a7259a7194 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -24,6 +24,7 @@ #include "internals.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" +#include "fpu/softfloat.h" =20 #define SIGNBIT (uint32_t)0x80000000 #define SIGNBIT64 ((uint64_t)1 << 63) @@ -1376,3 +1377,93 @@ uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x= , uint32_t i) return ((uint32_t)x >> shift) | (x << (32 - shift)); } } + +/* + * Implement float64 to int32_t conversion without saturation; + * the result is supplied modulo 2^32. + */ +uint64_t HELPER(fjcvtzs)(float64 value, void *vstatus) +{ + float_status *status =3D vstatus; + uint32_t result, exp, sign; + uint64_t frac; + uint32_t inexact; /* !Z */ + + sign =3D extract64(value, 63, 1); + exp =3D extract64(value, 52, 11); + frac =3D extract64(value, 0, 52); + + if (exp =3D=3D 0) { + /* While not inexact for IEEE FP, -0.0 is inexact for JavaScript. = */ + inexact =3D sign; + result =3D 0; + if (frac !=3D 0) { + if (status->flush_inputs_to_zero) { + float_raise(float_flag_input_denormal, status); + } else { + float_raise(float_flag_inexact, status); + inexact =3D 1; + } + } + } else if (exp =3D=3D 0x7ff) { + if (frac =3D=3D 0) { + /* Infinity. */ + result =3D 0; + } else { + /* NaN */ + result =3D INT32_MAX; + } + /* This operation raises Invalid for both NaN and overflow (Inf). = */ + float_raise(float_flag_invalid, status); + inexact =3D 1; + } else { + int shift, true_exp; + + true_exp =3D exp - 1023; + shift =3D 52 - true_exp; + + /* Restore implicit bit. */ + frac |=3D 1ull << 52; + + /* Shift the fraction into place. */ + if (shift <=3D -64) { + /* + * The number is so large the fraction is shifted out entirely. + * The result mod 2^32 is 0 and will match the overflow case. + */ + inexact =3D 1; + frac =3D 0; + } else if (shift <=3D 0) { + /* The number is so large we must shift the fraction left. */ + inexact =3D 1; + frac <<=3D -shift; + } else if (shift < 64) { + /* Normal case -- shift right and notice if bits shift out. */ + inexact =3D (frac << (64 - shift)) !=3D 0; + frac >>=3D shift; + } else { + /* The number is so small the fraction is shifted out entirely= . */ + inexact =3D 1; + frac =3D 0; + } + + /* Notice overflow or inexact exceptions. */ + if (true_exp > 31 + || frac > (sign ? 0x80000000ull : 0x7fffffff)) { + /* Overflow, for which this operation raises invalid. */ + float_raise(float_flag_invalid, status); + inexact =3D 1; + } else if (inexact) { + float_raise(float_flag_inexact, status); + } + + /* Produce the result mod 2^32. */ + if (sign) { + frac =3D -frac; + } + result =3D frac; + } + + /* Pack the result and the env->ZF representation of Z together. */ + return deposit64(result, 32, 32, inexact); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 90298ac562..49289bf1d8 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -6458,6 +6458,24 @@ static void handle_fmov(DisasContext *s, int rd, int= rn, int type, bool itof) } } =20 +static void handle_fjcvtzs(DisasContext *s, int rd, int rn) +{ + TCGv_i64 t =3D read_fp_dreg(s, rn); + TCGv_ptr fpstatus =3D get_fpstatus_ptr(false); + + gen_helper_fjcvtzs(t, t, fpstatus); + + tcg_temp_free_ptr(fpstatus); + + tcg_gen_ext32u_i64(cpu_reg(s, rd), t); + tcg_gen_extrh_i64_i32(cpu_ZF, t); + tcg_gen_movi_i32(cpu_CF, 0); + tcg_gen_movi_i32(cpu_NF, 0); + tcg_gen_movi_i32(cpu_VF, 0); + + tcg_temp_free_i64(t); +} + /* Floating point <-> integer conversions * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4= 0 * +----+---+---+-----------+------+---+-------+-----+-------------+----+-= ---+ @@ -6533,6 +6551,14 @@ static void disas_fp_int_conv(DisasContext *s, uint3= 2_t insn) handle_fmov(s, rd, rn, type, itof); break; =20 + case 0b00111110: /* FJCVTZS */ + if (!dc_isar_feature(aa64_jscvt, s)) { + goto do_unallocated; + } else if (fp_access_check(s)) { + handle_fjcvtzs(s, rd, rn); + } + break; + default: do_unallocated: unallocated_encoding(s); diff --git a/target/arm/translate.c b/target/arm/translate.c index eb25895876..a92d06b05b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4066,6 +4066,21 @@ static int disas_vfp_insn(DisasContext *s, uint32_t = insn) case 17: /* fsito */ gen_vfp_sito(dp, 0); break; + case 19: /* vjcvt */ + if (!dp || !dc_isar_feature(aa32_jscvt, s)) { + return 1; + } else { + TCGv_ptr fpst =3D get_fpstatus_ptr(0); + gen_helper_fjcvtzs(cpu_F0d, cpu_F0d, fpst); + tcg_temp_free_ptr(fpst); + + tcg_gen_extr_i64_i32(cpu_F0s, cpu_ZF, cpu_F0d); + tcg_gen_movi_i32(cpu_NF, 0); + tcg_gen_movi_i32(cpu_CF, 0); + tcg_gen_movi_i32(cpu_VF, 0); + dp =3D 0; /* always a single precision result = */ + } + break; case 20: /* fshto */ if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { return 1; --=20 2.17.2