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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n6sm2847250wmk.9.2019.02.01.08.07.42 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 Feb 2019 08:07:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=65hoE87QzTlx1RgWe4e2mzsptT81YWQ8G4GnPJjUlTY=; b=IAtYVHthd7imcY10dPHHw7DQDYrRm5PpcLmkLB8S89Y8n/uBQ4Fpe+fApce7udGrvf NK8eTsNH2Myi4pIDkaL3difA9UdHz5trCrC81jKowyV2ePAernWiHZ5pWKNAqCESroiQ Wc6Tqe/EHpa2LW6aRelg03/Lliyn6pe7fPyec= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=65hoE87QzTlx1RgWe4e2mzsptT81YWQ8G4GnPJjUlTY=; b=aFZaPqRrTkrNPLiwli2se6tvgVl0ZjWp8dzYvVmP5ZPgCS/zhSPH8J+pteLfM7bmRF 1mhFXidfTAO3Bfj1vkzP0gSVMKYzqCbXfNW+bQh8uXPFDF8gJd1NVHsabjybHVHwbZeR a0KTSgoqGeerdEPyFpREcCIdpKSjWFbgEgYmgTC7qU3/2glPskItbI0J5KfVx3aoYHCR kYTb0x712FfVdiu7chbMDrR0jpFN9p51PqGW5cPUaYBKc4pyaA+wkz58bAvlcNQDSajc XkDHR8kk/+bCiChW2cGtOP6GEOtDTIGCCdOmZKnGaH1WVbZCoqWpIxadPPbJ1KdtJx70 h2Hw== X-Gm-Message-State: AHQUAub5f/EabnD+6gUVNdSgO26ZjBStauuWWZv9pCD2o0WThEjeTf+V EJfsFYoEEhfOMox1wQQlqGH+huYpKDz6Pg== X-Google-Smtp-Source: AHgI3IYz5UKhv5ARjV3Vv+O8wVYhWMBrTSoIWN8d/uwMoVLz0oin6JmC+gVUkE/anPKfl7hH/+fDYw== X-Received: by 2002:a1c:9c15:: with SMTP id f21mr2896264wme.94.1549037263898; Fri, 01 Feb 2019 08:07:43 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 1 Feb 2019 16:06:44 +0000 Message-Id: <20190201160653.13829-39-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190201160653.13829-1-peter.maydell@linaro.org> References: <20190201160653.13829-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PULL 38/47] arm: Clarify the logic of set_pc() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Julia Suvorova Until now, the set_pc logic was unclear, which raised questions about whether it should be used directly, applying a value to PC or adding additional checks, for example, set the Thumb bit in Arm cpu. Let's set the set_pc logic for =E2=80=9CConfigure the PC, as was done in the ELF file= =E2=80=9D and implement synchronize_with_tb hook for preserving PC to cpu_tb_exec. Signed-off-by: Julia Suvorova Acked-by: Stefan Hajnoczi Message-id: 20190129121817.7109-1-jusual@mail.ru Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/qom/cpu.h | 16 ++++++++++++++-- hw/arm/boot.c | 4 ---- target/arm/arm-powerctl.c | 3 --- target/arm/cpu.c | 26 +++++++++++++++++++++++++- target/arm/cpu64.c | 15 --------------- 5 files changed, 39 insertions(+), 25 deletions(-) diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 4c2feb9c17b..1d6099e5d4b 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -103,9 +103,21 @@ struct TranslationBlock; * @get_arch_id: Callback for getting architecture-dependent CPU ID. * @get_paging_enabled: Callback for inquiring whether paging is enabled. * @get_memory_mapping: Callback for obtaining the memory mappings. - * @set_pc: Callback for setting the Program Counter register. + * @set_pc: Callback for setting the Program Counter register. This + * should have the semantics used by the target architecture when + * setting the PC from a source such as an ELF file entry point; + * for example on Arm it will also set the Thumb mode bit based + * on the least significant bit of the new PC value. + * If the target behaviour here is anything other than "set + * the PC register to the value passed in" then the target must + * also implement the synchronize_from_tb hook. * @synchronize_from_tb: Callback for synchronizing state from a TCG - * #TranslationBlock. + * #TranslationBlock. This is called when we abandon execution + * of a TB before starting it, and must set all parts of the CPU + * state which the previous TB in the chain may not have updated. + * This always includes at least the program counter; some targets + * will need to do more. If this hook is not implemented then the + * default is to call @set_pc(tb->pc). * @handle_mmu_fault: Callback for handling an MMU fault. * @get_phys_page_debug: Callback for obtaining a physical address. * @get_phys_page_attrs_debug: Callback for obtaining a physical address a= nd the diff --git a/hw/arm/boot.c b/hw/arm/boot.c index c7a67af7a97..05762d0fc1b 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -697,10 +697,6 @@ static void do_cpu_reset(void *opaque) g_assert_not_reached(); } =20 - if (!env->aarch64) { - env->thumb =3D info->entry & 1; - entry &=3D 0xfffffffe; - } cpu_set_pc(cs, entry); } else { /* If we are booting Linux then we need to check whether we are diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c index 2b856930fb7..f9de5164e55 100644 --- a/target/arm/arm-powerctl.c +++ b/target/arm/arm-powerctl.c @@ -120,11 +120,8 @@ static void arm_set_cpu_on_async_work(CPUState *target= _cpu_state, =20 if (info->target_aa64) { target_cpu->env.xregs[0] =3D info->context_id; - target_cpu->env.thumb =3D false; } else { target_cpu->env.regs[0] =3D info->context_id; - target_cpu->env.thumb =3D info->entry & 1; - info->entry &=3D 0xfffffffe; } =20 /* Start the new CPU at the requested address */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 8a9cd0900d2..f00d450d0bd 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -40,8 +40,31 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value) { ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; =20 - cpu->env.regs[15] =3D value; + if (is_a64(env)) { + env->pc =3D value; + env->thumb =3D 0; + } else { + env->regs[15] =3D value & ~1; + env->thumb =3D value & 1; + } +} + +static void arm_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + /* + * It's OK to look at env for the current mode here, because it's + * never possible for an AArch64 TB to chain to an AArch32 TB. + */ + if (is_a64(env)) { + env->pc =3D tb->pc; + } else { + env->regs[15] =3D tb->pc; + } } =20 static bool arm_cpu_has_work(CPUState *cs) @@ -2099,6 +2122,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->cpu_exec_interrupt =3D arm_cpu_exec_interrupt; cc->dump_state =3D arm_cpu_dump_state; cc->set_pc =3D arm_cpu_set_pc; + cc->synchronize_from_tb =3D arm_cpu_synchronize_from_tb; cc->gdb_read_register =3D arm_cpu_gdb_read_register; cc->gdb_write_register =3D arm_cpu_gdb_write_register; #ifdef CONFIG_USER_ONLY diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index e9bc461c362..8653cecd032 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -480,20 +480,6 @@ static void aarch64_cpu_finalizefn(Object *obj) { } =20 -static void aarch64_cpu_set_pc(CPUState *cs, vaddr value) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - /* It's OK to look at env for the current mode here, because it's - * never possible for an AArch64 TB to chain to an AArch32 TB. - * (Otherwise we would need to use synchronize_from_tb instead.) - */ - if (is_a64(&cpu->env)) { - cpu->env.pc =3D value; - } else { - cpu->env.regs[15] =3D value; - } -} - static gchar *aarch64_gdb_arch_name(CPUState *cs) { return g_strdup("aarch64"); @@ -504,7 +490,6 @@ static void aarch64_cpu_class_init(ObjectClass *oc, voi= d *data) CPUClass *cc =3D CPU_CLASS(oc); =20 cc->cpu_exec_interrupt =3D arm_cpu_exec_interrupt; - cc->set_pc =3D aarch64_cpu_set_pc; cc->gdb_read_register =3D aarch64_cpu_gdb_read_register; cc->gdb_write_register =3D aarch64_cpu_gdb_write_register; cc->gdb_num_core_regs =3D 34; --=20 2.20.1