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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n6sm2847250wmk.9.2019.02.01.08.06.57 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 Feb 2019 08:06:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=UuVW7tpTbDI/qssggkHCCe5zSzAPxwdivNU6kF+NI+c=; b=QVufptqcd/B7I7r+uUKaQKmAnO2k6f4sB1y6W/nIPlhuLogYfSRnJdIUbeFoL+2Q5x hOxiC0ZDuW8mC14qExJABgQLoBFo5erD5829GKzYZJNSU9tRsUDMUkFAUGE2MJ16siq/ HSEJDQNImAyxkfQ7tWJbwapssu/toq2RR/aR4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UuVW7tpTbDI/qssggkHCCe5zSzAPxwdivNU6kF+NI+c=; b=WugdlYxmFe4KENbZVJ5b7TGMJXkjJXeVhvpx4SPJOgYT4wB28V9FziHe2UDTggRHvx 6pjc3ydWsKRd5AeRS/shYdIdg9BQFJLuE9B/r89Gg7NiJKpxP2D1CWmOjuzpmp4KLTUU Xeu4yCC5uAphcTL7Joh4jLM8bYrt7xt9omZR5g9qGg0e5x5vNQ109YepPo5JZMA1hqV0 WWHzzK4ddhG+BtdcJvMtvj+rWOpANiyeE7f304+4sd9/o7K/kAMibIznjpiIFa9DiM0M IGLYgbNmYN684h++fl/DgyIjryI2LCzd5gtfF9oHUOid6CQj6BqOdiro76jY5pj+P+tk Xs8Q== X-Gm-Message-State: AJcUukeoPJhmqlPNZ+E78o51lhtiXkanMdZ4s7Ffj29S77qMO1bL525F iFjpqmaoryrZ2wWpfjabtgLuQlE2f+bP9A== X-Google-Smtp-Source: ALg8bN68+aY771zPojJjhbTNFEPMev9qkjU8s6fL88OzM2j0yHqY5NeqttO56MKFKrU4jfEGzQvQEw== X-Received: by 2002:adf:9d85:: with SMTP id p5mr37610285wre.41.1549037218532; Fri, 01 Feb 2019 08:06:58 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 1 Feb 2019 16:06:08 +0000 Message-Id: <20190201160653.13829-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190201160653.13829-1-peter.maydell@linaro.org> References: <20190201160653.13829-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::430 Subject: [Qemu-devel] [PULL 02/47] armv7m: Don't assume the NVIC's CPU is CPU 0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Currently the ARMv7M NVIC object's realize method assumes that the CPU the NVIC is attached to is CPU 0, because it thinks there can only ever be one CPU in the system. To allow a dual-Cortex-M33 setup we need to remove this assumption; instead the armv7m wrapper object tells the NVIC its CPU, in the same way that it already tells the CPU what the NVIC is. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20190121185118.18550-2-peter.maydell@linaro.org --- hw/arm/armv7m.c | 6 ++++-- hw/intc/armv7m_nvic.c | 3 +-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index f4446528307..f9aa83d20ef 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -178,10 +178,12 @@ static void armv7m_realize(DeviceState *dev, Error **= errp) } } =20 - /* Tell the CPU where the NVIC is; it will fail realize if it doesn't - * have one. + /* + * Tell the CPU where the NVIC is; it will fail realize if it doesn't + * have one. Similarly, tell the NVIC where its CPU is. */ s->cpu->env.nvic =3D &s->nvic; + s->nvic.cpu =3D s->cpu; =20 object_property_set_bool(OBJECT(s->cpu), true, "realized", &err); if (err !=3D NULL) { diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 0beefb05d44..790a3d95849 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2274,8 +2274,7 @@ static void armv7m_nvic_realize(DeviceState *dev, Err= or **errp) Error *err =3D NULL; int regionlen; =20 - s->cpu =3D ARM_CPU(qemu_get_cpu(0)); - + /* The armv7m container object will have set our CPU pointer */ if (!s->cpu || !arm_feature(&s->cpu->env, ARM_FEATURE_M)) { error_setg(errp, "The NVIC can only be used with a Cortex-M CPU"); return; --=20 2.20.1