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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n6sm2847250wmk.9.2019.02.01.08.07.26 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 Feb 2019 08:07:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ddxrppjz4iXH4w1jigFjxw+FhNBgdMRMsFsr9FMtHbY=; b=HhIxaZBL5wRiSUpx3e8+IPF6P/TazDJpM8TPcENIaRqTiHEi+CWUrWeLoNLJyxzxoN o2ihEIgqDrYxIplGVEgDsybH39/48LJhqqdyBf1Nm/4xTcRoR8ownCczKHAN1ukPOmQk jPImTrRCl9p5NfETg7/wtt8CmcFfZi7YkUm1A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ddxrppjz4iXH4w1jigFjxw+FhNBgdMRMsFsr9FMtHbY=; b=Fsw/oeQHIjqGVSW2Zwm+ixubsdcofhuirPlyOUgAH9tD+p9HHFFHndIZ15LbUswmXx WytqxYdK/30cj0MZnSvgW5113kkUoS7fyrZFdakFMzpwPOYSKgghwEtxjifX1d3rEMJg TA4CAhYhjrTgnGoMngoOx8vlSA/Xlzrs4XiJPviwHdKrleWeQOnPzcmSuoRX0F4wKo8j ch4JtJA3FA6fSfjHwBTRGs/PfkXAMyYa3xD5lK9MkZrf9n7ak1EkglGE9yq/wZdoylHS YWQsL9t/sUNmuc5q5f/p1jUmSfn+rQkSGlWOSraVfkBTOl1s5XFiETIw3DIVPq/RbInZ ks5Q== X-Gm-Message-State: AHQUAuaECE4KsDQBVJplvfXDh58p1TfU+T+9IP2rw1b3dOPiDKecYjhp H1y5UBWn6+SQuN3f3KE6xBcL8lkhedOp2A== X-Google-Smtp-Source: AHgI3IYlzHInear8qA9k5mEyoqj4fIQTBL1KQl9pL7nFj5LEAGGFIBi98SIHEUJNo7hnTFT7Jydrww== X-Received: by 2002:a1c:1f83:: with SMTP id f125mr2969259wmf.56.1549037247370; Fri, 01 Feb 2019 08:07:27 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 1 Feb 2019 16:06:30 +0000 Message-Id: <20190201160653.13829-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190201160653.13829-1-peter.maydell@linaro.org> References: <20190201160653.13829-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PULL 24/47] hw/arm/mps2-tz: Add mps2-an521 model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add a model of the MPS2 FPGA image described in Application Note AN521. This is identical to the AN505 image, except that it uses the SSE-200 rather than the IoTKit and so has two Cortex-M33 CPUs. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20190121185118.18550-24-peter.maydell@linaro.org --- hw/arm/mps2-tz.c | 38 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 95adcd478ab..f5f0b0e0fa5 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -15,6 +15,7 @@ * as seen by the guest depend significantly on the FPGA image. * This source file covers the following FPGA images, for TrustZone cores: * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505 + * "mps2-an521" -- Dual Cortex-M33 as documented in Application Note AN521 * * Links to the TRM for the board itself and to the various Application * Notes which document the FPGA images can be found here: @@ -24,10 +25,16 @@ * http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_06_en/vers= atile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_techni= cal_reference_100112_0200_06_en.pdf * Application Note AN505: * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html + * Application Note AN521: + * http://infocenter.arm.com/help/topic/com.arm.doc.dai0521c/index.html * * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Gu= ide * (ARM ECM0601256) for the details of some of the device layout: * http://infocenter.arm.com/help/index.jsp?topic=3D/com.arm.doc.ecm0601= 256/index.html + * Similarly, the AN521 uses the SSE-200, and the SSE-200 TRM defines + * most of the device layout: + * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/cor= elink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_= 00_en.pdf + * */ =20 #include "qemu/osdep.h" @@ -64,6 +71,7 @@ typedef struct { MachineClass parent; MPS2TZFPGAType fpga_type; uint32_t scc_id; + const char *armsse_type; } MPS2TZMachineClass; =20 typedef struct { @@ -93,6 +101,7 @@ typedef struct { =20 #define TYPE_MPS2TZ_MACHINE "mps2tz" #define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505") +#define TYPE_MPS2TZ_AN521_MACHINE MACHINE_TYPE_NAME("mps2-an521") =20 #define MPS2TZ_MACHINE(obj) \ OBJECT_CHECK(MPS2TZMachineState, obj, TYPE_MPS2TZ_MACHINE) @@ -379,7 +388,7 @@ static void mps2tz_common_init(MachineState *machine) } =20 sysbus_init_child_obj(OBJECT(machine), "iotkit", &mms->iotkit, - sizeof(mms->iotkit), TYPE_IOTKIT); + sizeof(mms->iotkit), mmc->armsse_type); iotkitdev =3D DEVICE(&mms->iotkit); object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory), "memory", &error_abort); @@ -632,7 +641,6 @@ static void mps2tz_class_init(ObjectClass *oc, void *da= ta) IDAUInterfaceClass *iic =3D IDAU_INTERFACE_CLASS(oc); =20 mc->init =3D mps2tz_common_init; - mc->max_cpus =3D 1; iic->check =3D mps2_tz_idau_check; } =20 @@ -642,9 +650,28 @@ static void mps2tz_an505_class_init(ObjectClass *oc, v= oid *data) MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_CLASS(oc); =20 mc->desc =3D "ARM MPS2 with AN505 FPGA image for Cortex-M33"; + mc->default_cpus =3D 1; + mc->min_cpus =3D mc->default_cpus; + mc->max_cpus =3D mc->default_cpus; mmc->fpga_type =3D FPGA_AN505; mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m33"); mmc->scc_id =3D 0x41045050; + mmc->armsse_type =3D TYPE_IOTKIT; +} + +static void mps2tz_an521_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_CLASS(oc); + + mc->desc =3D "ARM MPS2 with AN521 FPGA image for dual Cortex-M33"; + mc->default_cpus =3D 2; + mc->min_cpus =3D mc->default_cpus; + mc->max_cpus =3D mc->default_cpus; + mmc->fpga_type =3D FPGA_AN521; + mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m33"); + mmc->scc_id =3D 0x41045210; + mmc->armsse_type =3D TYPE_SSE200; } =20 static const TypeInfo mps2tz_info =3D { @@ -666,10 +693,17 @@ static const TypeInfo mps2tz_an505_info =3D { .class_init =3D mps2tz_an505_class_init, }; =20 +static const TypeInfo mps2tz_an521_info =3D { + .name =3D TYPE_MPS2TZ_AN521_MACHINE, + .parent =3D TYPE_MPS2TZ_MACHINE, + .class_init =3D mps2tz_an521_class_init, +}; + static void mps2tz_machine_init(void) { type_register_static(&mps2tz_info); type_register_static(&mps2tz_an505_info); + type_register_static(&mps2tz_an521_info); } =20 type_init(mps2tz_machine_init); --=20 2.20.1